OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_comp.v] - Blame information for rev 46

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 46 simont
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  8051 compare                                                ////
4
////                                                              ////
5
////  This file is part of the 8051 cores project                 ////
6
////  http://www.opencores.org/cores/8051/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////   compares selected inputs and set eq to 1 if they are equal ////
10
////   Is used for conditional jumps.                             ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   replace CSS_AZ with CSS_DES                                ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Simon Teran, simont@opencores.org                     ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// CVS Revision History
46
//
47
// $Log: not supported by cvs2svn $
48
//
49
 
50
// synopsys translate_off
51
`include "oc8051_timescale.v"
52
// synopsys translate_on
53
 
54
`include "oc8051_defines.v"
55
 
56
 
57
module oc8051_comp (sel, b_in, cy, acc, des, eq);
58
//
59
// sel          (in)  select whithc sourses to compare (look defines.v) [oc8051_decoder.comp_sel]
60
// b_in         (in)  bit in - output from bit addressable memory space [oc8051_ram_sel.bit_out]
61
// cy           (in)  carry flag [oc8051_psw.data_out[7] ]
62
// acc          (in)  accumulator [oc8051_acc.data_out]
63
// ram          (in)  input from ram [oc8051_ram_sel.out_data]
64
// op2          (in)  immediate data [oc8051_op_select.op2_out -r]
65
// des          (in)  destination from alu [oc8051_alu.des1 -r]
66
// eq           (out) if (src1 == src2) eq = 1  [oc8051_decoder.eq]
67
//
68
 
69
 
70
input [1:0] sel;
71
input b_in, cy;
72
input [7:0] acc, des;
73
 
74
output eq;
75
reg eq;
76
 
77
always @(sel or b_in or cy or acc or des)
78
begin
79
  case (sel)
80
    `OC8051_CSS_AZ : eq = (acc == 8'h00);
81
    `OC8051_CSS_DES : eq = (des == 8'h00);
82
    `OC8051_CSS_CY : eq = cy;
83
    `OC8051_CSS_BIT : eq = b_in;
84
    default: eq = 1'bx;
85
  endcase
86
end
87
 
88
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.