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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_divide.v] - Blame information for rev 185

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1 95 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// divide for 8051 Core                                         ////
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////                                                              ////
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//// This file is part of the 8051 cores project                  ////
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//// http://www.opencores.org/cores/8051/                         ////
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////                                                              ////
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//// Description                                                  ////
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//// Four cycle implementation of division used in alu.v          ////
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////                                                              ////
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//// To Do:                                                       ////
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////  check if compiler does proper optimizations of the code     ////
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////                                                              ////
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//// Author(s):                                                   ////
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//// - Simon Teran, simont@opencores.org                          ////
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//// - Marko Mlinar, markom@opencores.org                         ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE. See the GNU Lesser General Public License for more  ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.8  2002/09/30 17:15:31  simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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module oc8051_divide (clk, rst, enable, src1, src2, des1, des2, desOv);
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//
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// this module is part of alu
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// clk          (in)
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// rst          (in)
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// enable       (in)  starts divison
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// src1         (in)  first operand
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// src2         (in)  second operand
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// des1         (out) first result
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// des2         (out) second result
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// desOv        (out) Overflow output
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//
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input clk, rst, enable;
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input [7:0] src1, src2;
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output desOv;
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output [7:0] des1, des2;
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// wires
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wire desOv;
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wire div0, div1;
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wire [7:0] rem0, rem1, rem2;
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wire [8:0] sub0, sub1;
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wire [15:0] cmp0, cmp1;
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wire [7:0] div_out, rem_out;
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// real registers
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reg [1:0] cycle;
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reg [5:0] tmp_div;
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reg [7:0] tmp_rem;
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// The main logic
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assign cmp1 = src2 << ({2'h3 - cycle, 1'b0} + 3'h1);
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assign cmp0 = src2 << ({2'h3 - cycle, 1'b0} + 3'h0);
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assign rem2 = cycle != 0 ? tmp_rem : src1;
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assign sub1 = {1'b0, rem2} - {1'b0, cmp1[7:0]};
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assign div1 = |cmp1[15:8] ? 1'b0 : !sub1[8];
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assign rem1 = div1 ? sub1[7:0] : rem2[7:0];
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assign sub0 = {1'b0, rem1} - {1'b0, cmp0[7:0]};
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assign div0 = |cmp0[15:8] ? 1'b0 : !sub0[8];
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assign rem0 = div0 ? sub0[7:0] : rem1[7:0];
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//
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// in clock cycle 0 we first calculate two MSB bits, ...
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// till finally in clock cycle 3 we calculate two LSB bits
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assign div_out = {tmp_div, div1, div0};
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assign rem_out = rem0;
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assign desOv = src2 == 8'h0;
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//
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// divider works in four clock cycles -- 0, 1, 2 and 3
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    cycle <= #1 2'b0;
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    tmp_div <= #1 6'h0;
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    tmp_rem <= #1 8'h0;
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  end else begin
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    if (enable) cycle <= #1 cycle + 2'b1;
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    tmp_div <= #1 div_out[5:0];
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    tmp_rem <= #1 rem_out;
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  end
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end
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//
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// assign outputs
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assign des1 = rem_out;
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assign des2 = div_out;
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endmodule

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