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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 instruction cache                                      ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////  8051 instruction cache                                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2003/06/20 13:36:37  simont
// ram modules added.
//
// Revision 1.7  2003/05/05 10:35:35  simont
// change to fit xrom.
//
// Revision 1.6  2003/04/03 19:15:37  simont
// fix some bugs, use oc8051_cache_ram.
//
// Revision 1.5  2003/04/02 11:22:15  simont
// fix bug.
//
// Revision 1.4  2003/01/21 14:08:18  simont
// fix bugs
//
// Revision 1.3  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.2  2002/10/24 13:34:02  simont
// add parameters for instruction cache
//
// Revision 1.1  2002/10/23 16:55:36  simont
// fix bugs in instruction interface
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_icache (rst, clk,
             adr_i, dat_o, stb_i, ack_o, cyc_i,
             adr_o, dat_i, stb_o, ack_i, cyc_o
`ifdef OC8051_BIST
         ,
         scanb_rst,
         scanb_clk,
         scanb_si,
         scanb_so,
         scanb_en
`endif
             );
//
// rst           (in)  reset - pin
// clk           (in)  clock - pini
input rst, clk;
 
//
// interface to oc8051 cpu
//
// adr_i    (in)  address
// dat_o    (out) data output
// stb_i    (in)  strobe
// ack_o    (out) acknowledge
// cyc_i    (in)  cycle
input         stb_i,
              cyc_i;
input  [15:0] adr_i;
output        ack_o;
output [31:0] dat_o;
reg    [31:0] dat_o;
 
//
// interface to instruction rom
//
// adr_o    (out) address
// dat_i    (in)  data input
// stb_o    (out) strobe
// ack_i    (in) acknowledge
// cyc_o    (out)  cycle
input         ack_i;
input  [31:0] dat_i;
output        stb_o,
              cyc_o;
output [15:0] adr_o;
reg           stb_o,
              cyc_o;
 
`ifdef OC8051_BIST
input   scanb_rst;
input   scanb_clk;
input   scanb_si;
output  scanb_so;
input   scanb_en;
`endif
 
parameter ADR_WIDTH = 6; // cache address wihth
parameter LINE_WIDTH = 2; // line address width (2 => 4x32)
parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width
parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)
parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
 
//
// internal buffers adn wires
//
// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache
reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];
// valid[x]=1 if block x is valid;
reg [BL_NUM:0] valid;
// con0, con2 contain temporal control information of current address and corrent address+2
// part of con_buf memory
reg [13-ADR_WIDTH:0] con0, con2;
//current upper address,
reg [13-ADR_WIDTH:0] cadr0, cadr2;
reg stb_b;
// byte_select in 32 bit line (adr_i[1:0])
reg [1:0] byte_sel;
// read cycle
reg [LINE_WIDTH-1:0] cyc;
// data input from cache ram
reg [31:0] data1_i;
// temporaly data from ram
reg [15:0] tmp_data1;
reg wr1, wr1_t, stb_it;
 
////////////////
 
reg vaild_h, vaild_l;
 
 
wire [31:0] data0, data1_o;
wire cy, cy1;
wire [BL_WIDTH-1:0] adr_i2;
wire hit, hit_l, hit_h;
wire [ADR_WIDTH-1:0] adr_r, addr1;
reg [ADR_WIDTH-1:0] adr_w;
reg [15:0] mis_adr;
wire [15:0] data1;
wire [LINE_WIDTH-1:0] adr_r1;
 
 
assign cy = &adr_i[LINE_WIDTH+1:1];
assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;
assign hit_l = (con0==cadr0) & vaild_l;
assign hit_h = (con2==cadr2) & vaild_h;
assign hit = hit_l && hit_h;
 
assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];
assign addr1 = wr1 ? adr_w : adr_r;
assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;
assign ack_o = hit && stb_it;
 
assign data1 = wr1_t ? tmp_data1 : data1_o[15:0];
 
assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};
 
 
oc8051_ram_64x32_dual_bist oc8051_cache_ram(
                           .clk     ( clk        ),
                           .rst     ( rst        ),
                           .adr0    ( adr_i[ADR_WIDTH+1:2] ),
                           .dat0_o  ( data0      ),
                           .en0     ( 1'b1       ),
                           .adr1    ( addr1      ),
                           .dat1_o  ( data1_o    ),
                           .dat1_i  ( data1_i    ),
                           .en1     ( 1'b1       ),
                           .wr1     ( wr1        )
`ifdef OC8051_BIST
         ,
         .scanb_rst(scanb_rst),
         .scanb_clk(scanb_clk),
         .scanb_si(scanb_soi),
         .scanb_so(scanb_so),
         .scanb_en(scanb_en)
`endif
                           );
 
defparam oc8051_cache_ram.ADR_WIDTH = ADR_WIDTH;
 
 
always @(stb_b or data0 or data1 or byte_sel)
begin
  if (stb_b) begin
    case (byte_sel) /* synopsys full_case parallel_case */
      2'b00  : dat_o = data0;
      2'b01  : dat_o = {data1[7:0],   data0[31:8]};
      2'b10  : dat_o = {data1[15:0],  data0[31:16]};
      2'b11  : dat_o = {8'h00, data1, data0[31:24]};
    endcase
  end else begin
    dat_o = 32'h0;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    begin
        con0 <= #1 9'h0;
        con2 <= #1 9'h0;
        vaild_h <= #1 1'b0;
        vaild_l <= #1 1'b0;
    end
  else
    begin
        con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};
        con2 <= #1 {con_buf[adr_i2]};
        vaild_l <= #1 valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]];
        vaild_h <= #1 valid[adr_i2];
    end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    cadr0 <= #1 8'h00;
    cadr2 <= #1 8'h00;
  end else begin
    cadr0 <= #1 adr_i[15:ADR_WIDTH+2];
    cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    stb_b <= #1 1'b0;
    byte_sel <= #1 2'b00;
  end else begin
    stb_b <= #1 stb_i;
    byte_sel <= #1 adr_i[1:0];
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    begin
        cyc    <= #1 2'b00;
        cyc_o  <= #1 1'b0;
        stb_o  <= #1 1'b0;
        data1_i<= #1 32'h0;
        wr1    <= #1 1'b0;
        adr_w  <= #1 6'h0;
        valid  <= #1 16'h0;
    end
  else if (stb_b && !hit && !stb_o && !wr1)
    begin
        cyc     <= #1 2'b00;
        cyc_o   <= #1 1'b1;
        stb_o   <= #1 1'b1;
        data1_i <= #1 32'h0;
        wr1     <= #1 1'b0;
    end
  else if (stb_o && ack_i)
    begin
        data1_i<= #1 dat_i; ///??
        wr1    <= #1 1'b1;
        adr_w  <= #1 adr_o[ADR_WIDTH+1:2];
 
        if (&cyc)
          begin
              cyc   <= #1 2'b00;
              cyc_o <= #1 1'b0;
              stb_o <= #1 1'b0;
              valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;
          end
        else
          begin
              cyc   <= #1 cyc + 1'b1;
              cyc_o <= #1 1'b1;
              stb_o <= #1 1'b1;
              valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b0;
          end
    end
  else
    wr1 <= #1 1'b0;
end
 
//rih
always @(posedge clk)
  if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )
    con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];
 
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    mis_adr <= #1 1'b0;
  else if (!hit_l)
    mis_adr <= #1 adr_i;
  else if (!hit_h)
    mis_adr <= #1 adr_i+'d2;
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    tmp_data1 <= #1 1'b0;
  else if (!hit_h && wr1 && (cyc==adr_r1))
//    tmp_data1 <= #1 dat_i[31:16]; //???
    tmp_data1 <= #1 dat_i[15:0]; //???
  else if (!hit_l && hit_h && wr1)
//    tmp_data1 <= #1 data1_o[31:16];
    tmp_data1 <= #1 data1_o[15:0]; //??
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    wr1_t <= #1 1'b0;
    stb_it <= #1 1'b0;
  end else begin
    wr1_t <= #1 wr1;
    stb_it <= #1 stb_i;
  end
end
 
endmodule
 

Line No.	Rev	Author	Line
1	67	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 instruction cache ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 instruction cache ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43	62	simont	`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	179	simont	`// Revision 1.8 2003/06/20 13:36:37 simont`
48			`// ram modules added.`
49			`//`
50	174	simont	`// Revision 1.7 2003/05/05 10:35:35 simont`
51			`// change to fit xrom.`
52			`//`
53	137	simont	`// Revision 1.6 2003/04/03 19:15:37 simont`
54			`// fix some bugs, use oc8051_cache_ram.`
55			`//`
56	108	simont	`// Revision 1.5 2003/04/02 11:22:15 simont`
57			`// fix bug.`
58			`//`
59	94	simont	`// Revision 1.4 2003/01/21 14:08:18 simont`
60			`// fix bugs`
61			`//`
62	88	simont	`// Revision 1.3 2003/01/13 14:14:41 simont`
63			`// replace some modules`
64			`//`
65	82	simont	`// Revision 1.2 2002/10/24 13:34:02 simont`
66			`// add parameters for instruction cache`
67			`//`
68	67	simont	`// Revision 1.1 2002/10/23 16:55:36 simont`
69			`// fix bugs in instruction interface`
70	62	simont	`//`
71	67	simont	`//`
72	62	simont
73			`// synopsys translate_off`
74			`include "oc8051_timescale.v"
75			`// synopsys translate_on`
76
77	174	simont	`include "oc8051_defines.v"
78	62	simont
79	137	simont	`module oc8051_icache (rst, clk,`
80			`adr_i, dat_o, stb_i, ack_o, cyc_i,`
81			`adr_o, dat_i, stb_o, ack_i, cyc_o`
82	174	simont	`ifdef OC8051_BIST
83			`,`
84			`scanb_rst,`
85			`scanb_clk,`
86			`scanb_si,`
87			`scanb_so,`
88			`scanb_en`
89			`endif
90	137	simont	`);`
91	62	simont	`//`
92			`// rst (in) reset - pin`
93			`// clk (in) clock - pini`
94			`input rst, clk;`
95
96			`//`
97			`// interface to oc8051 cpu`
98			`//`
99			`// adr_i (in) address`
100			`// dat_o (out) data output`
101			`// stb_i (in) strobe`
102			`// ack_o (out) acknowledge`
103			`// cyc_i (in) cycle`
104	137	simont	`input stb_i,`
105			`cyc_i;`
106			`input [15:0] adr_i;`
107			`output ack_o;`
108	62	simont	`output [31:0] dat_o;`
109	137	simont	`reg [31:0] dat_o;`
110	62	simont
111			`//`
112			`// interface to instruction rom`
113			`//`
114			`// adr_o (out) address`
115			`// dat_i (in) data input`
116			`// stb_o (out) strobe`
117			`// ack_i (in) acknowledge`
118			`// cyc_o (out) cycle`
119	137	simont	`input ack_i;`
120			`input [31:0] dat_i;`
121			`output stb_o,`
122			`cyc_o;`
123	62	simont	`output [15:0] adr_o;`
124	137	simont	`reg stb_o,`
125			`cyc_o;`
126	62	simont
127	174	simont	`ifdef OC8051_BIST
128			`input scanb_rst;`
129			`input scanb_clk;`
130			`input scanb_si;`
131			`output scanb_so;`
132			`input scanb_en;`
133			`endif
134
135	67	simont	`parameter ADR_WIDTH = 6; // cache address wihth`
136			`parameter LINE_WIDTH = 2; // line address width (2 => 4x32)`
137			`parameter BL_WIDTH = ADR_WIDTH - LINE_WIDTH; // block address width`
138			`parameter BL_NUM = 15; // number of blocks (2^BL_WIDTH-1)`
139			`parameter CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)`
140
141	62	simont	`//`
142			`// internal buffers adn wires`
143			`//`
144	67	simont	`// con_buf control buffer, contains upper addresses [15:ADDR_WIDTH1] in cache`
145			`reg [13-ADR_WIDTH:0] con_buf [BL_NUM:0];`
146	88	simont	`// valid[x]=1 if block x is valid;`
147			`reg [BL_NUM:0] valid;`
148	62	simont	`// con0, con2 contain temporal control information of current address and corrent address+2`
149	67	simont	`// part of con_buf memory`
150	108	simont	`reg [13-ADR_WIDTH:0] con0, con2;`
151	67	simont	`//current upper address,`
152			`reg [13-ADR_WIDTH:0] cadr0, cadr2;`
153	62	simont	`reg stb_b;`
154	67	simont	`// byte_select in 32 bit line (adr_i[1:0])`
155	62	simont	`reg [1:0] byte_sel;`
156	67	simont	`// read cycle`
157			`reg [LINE_WIDTH-1:0] cyc;`
158			`// data input from cache ram`
159	62	simont	`reg [31:0] data1_i;`
160	67	simont	`// temporaly data from ram`
161	62	simont	`reg [15:0] tmp_data1;`
162			`reg wr1, wr1_t, stb_it;`
163
164	108	simont	`////////////////`
165
166			`reg vaild_h, vaild_l;`
167
168
169	62	simont	`wire [31:0] data0, data1_o;`
170			`wire cy, cy1;`
171	67	simont	`wire [BL_WIDTH-1:0] adr_i2;`
172	62	simont	`wire hit, hit_l, hit_h;`
173	67	simont	`wire [ADR_WIDTH-1:0] adr_r, addr1;`
174			`reg [ADR_WIDTH-1:0] adr_w;`
175	62	simont	`reg [15:0] mis_adr;`
176			`wire [15:0] data1;`
177	67	simont	`wire [LINE_WIDTH-1:0] adr_r1;`
178	62	simont
179	67	simont
180			`assign cy = &adr_i[LINE_WIDTH+1:1];`
181			`assign {cy1, adr_i2} = {1'b0, adr_i[ADR_WIDTH+1:LINE_WIDTH+2]}+cy;`
182	108	simont	`assign hit_l = (con0==cadr0) & vaild_l;`
183			`assign hit_h = (con2==cadr2) & vaild_h;`
184	62	simont	`assign hit = hit_l && hit_h;`
185
186	67	simont	`assign adr_r = adr_i[ADR_WIDTH+1:2] + adr_i[1];`
187	62	simont	`assign addr1 = wr1 ? adr_w : adr_r;`
188	67	simont	`assign adr_r1 = adr_r[LINE_WIDTH-1:0] + 2'b01;`
189	62	simont	`assign ack_o = hit && stb_it;`
190
191	137	simont	`assign data1 = wr1_t ? tmp_data1 : data1_o[15:0];`
192	62	simont
193	67	simont	`assign adr_o = {mis_adr[15:LINE_WIDTH+2], cyc, 2'b00};`
194
195
196	174	simont	`oc8051_ram_64x32_dual_bist oc8051_cache_ram(`
197			`.clk ( clk ),`
198			`.rst ( rst ),`
199			`.adr0 ( adr_i[ADR_WIDTH+1:2] ),`
200			`.dat0_o ( data0 ),`
201			`.en0 ( 1'b1 ),`
202			`.adr1 ( addr1 ),`
203			`.dat1_o ( data1_o ),`
204			`.dat1_i ( data1_i ),`
205			`.en1 ( 1'b1 ),`
206			`.wr1 ( wr1 )`
207			`ifdef OC8051_BIST
208			`,`
209			`.scanb_rst(scanb_rst),`
210			`.scanb_clk(scanb_clk),`
211			`.scanb_si(scanb_soi),`
212			`.scanb_so(scanb_so),`
213			`.scanb_en(scanb_en)`
214			`endif
215			`);`
216	108	simont
217	174	simont	`defparam oc8051_cache_ram.ADR_WIDTH = ADR_WIDTH;`
218	62	simont
219	67	simont
220	62	simont	`always @(stb_b or data0 or data1 or byte_sel)`
221			`begin`
222			`if (stb_b) begin`
223	179	simont	`case (byte_sel) /* synopsys full_case parallel_case */`
224	88	simont	`2'b00 : dat_o = data0;`
225	137	simont	`2'b01 : dat_o = {data1[7:0], data0[31:8]};`
226			`2'b10 : dat_o = {data1[15:0], data0[31:16]};`
227	179	simont	`2'b11 : dat_o = {8'h00, data1, data0[31:24]};`
228	62	simont	`endcase`
229	67	simont	`end else begin`
230	62	simont	`dat_o = 32'h0;`
231			`end`
232			`end`
233
234			`always @(posedge clk or posedge rst)`
235			`begin`
236	88	simont	`if (rst)`
237			`begin`
238			`con0 <= #1 9'h0;`
239			`con2 <= #1 9'h0;`
240	108	simont	`vaild_h <= #1 1'b0;`
241			`vaild_l <= #1 1'b0;`
242	88	simont	`end`
243			`else`
244			`begin`
245	108	simont	`con0 <= #1 {con_buf[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]]};`
246			`con2 <= #1 {con_buf[adr_i2]};`
247			`vaild_l <= #1 valid[adr_i[ADR_WIDTH+1:LINE_WIDTH+2]];`
248			`vaild_h <= #1 valid[adr_i2];`
249	88	simont	`end`
250	62	simont	`end`
251
252			`always @(posedge clk or posedge rst)`
253			`begin`
254			`if (rst) begin`
255			`cadr0 <= #1 8'h00;`
256			`cadr2 <= #1 8'h00;`
257			`end else begin`
258	67	simont	`cadr0 <= #1 adr_i[15:ADR_WIDTH+2];`
259			`cadr2 <= #1 adr_i[15:ADR_WIDTH+2]+ cy1;`
260	62	simont	`end`
261			`end`
262
263			`always @(posedge clk or posedge rst)`
264			`begin`
265			`if (rst) begin`
266			`stb_b <= #1 1'b0;`
267	67	simont	`byte_sel <= #1 2'b00;`
268	62	simont	`end else begin`
269			`stb_b <= #1 stb_i;`
270			`byte_sel <= #1 adr_i[1:0];`
271			`end`
272			`end`
273
274			`always @(posedge clk or posedge rst)`
275			`begin`
276	88	simont	`if (rst)`
277			`begin`
278			`cyc <= #1 2'b00;`
279			`cyc_o <= #1 1'b0;`
280			`stb_o <= #1 1'b0;`
281			`data1_i<= #1 32'h0;`
282			`wr1 <= #1 1'b0;`
283			`adr_w <= #1 6'h0;`
284			`valid <= #1 16'h0;`
285	108	simont	`end`
286	88	simont	`else if (stb_b && !hit && !stb_o && !wr1)`
287			`begin`
288			`cyc <= #1 2'b00;`
289			`cyc_o <= #1 1'b1;`
290			`stb_o <= #1 1'b1;`
291			`data1_i <= #1 32'h0;`
292			`wr1 <= #1 1'b0;`
293			`end`
294			`else if (stb_o && ack_i)`
295			`begin`
296	137	simont	`data1_i<= #1 dat_i; ///??`
297	88	simont	`wr1 <= #1 1'b1;`
298			`adr_w <= #1 adr_o[ADR_WIDTH+1:2];`
299
300			`if (&cyc)`
301			`begin`
302			`cyc <= #1 2'b00;`
303			`cyc_o <= #1 1'b0;`
304			`stb_o <= #1 1'b0;`
305			`valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b1;`
306			`end`
307			`else`
308			`begin`
309			`cyc <= #1 cyc + 1'b1;`
310			`cyc_o <= #1 1'b1;`
311			`stb_o <= #1 1'b1;`
312	108	simont	`valid[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 1'b0;`
313	88	simont	`end`
314	67	simont	`end`
315	88	simont	`else`
316	62	simont	`wr1 <= #1 1'b0;`
317			`end`
318
319	88	simont	`//rih`
320			`always @(posedge clk)`
321	94	simont	`if ( ~(stb_b && !hit && !stb_o && !wr1) & (stb_o && ack_i && cyc) )`
322	88	simont	`con_buf[mis_adr[ADR_WIDTH+1:LINE_WIDTH+2]] <= #1 mis_adr[15:ADR_WIDTH+2];`
323
324
325	62	simont	`always @(posedge clk or posedge rst)`
326			`begin`
327			`if (rst)`
328	88	simont	`mis_adr <= #1 1'b0;`
329	62	simont	`else if (!hit_l)`
330			`mis_adr <= #1 adr_i;`
331			`else if (!hit_h)`
332	67	simont	`mis_adr <= #1 adr_i+'d2;`
333			`end`
334	62	simont
335			`always @(posedge clk or posedge rst)`
336			`begin`
337			`if (rst)`
338	88	simont	`tmp_data1 <= #1 1'b0;`
339	62	simont	`else if (!hit_h && wr1 && (cyc==adr_r1))`
340	137	simont	`// tmp_data1 <= #1 dat_i[31:16]; //???`
341			`tmp_data1 <= #1 dat_i[15:0]; //???`
342	62	simont	`else if (!hit_l && hit_h && wr1)`
343	137	simont	`// tmp_data1 <= #1 data1_o[31:16];`
344			`tmp_data1 <= #1 data1_o[15:0]; //??`
345	67	simont	`end`
346	62	simont
347			`always @(posedge clk or posedge rst)`
348			`begin`
349			`if (rst) begin`
350			`wr1_t <= #1 1'b0;`
351			`stb_it <= #1 1'b0;`
352			`end else begin`
353			`wr1_t <= #1 wr1;`
354	67	simont	`stb_it <= #1 stb_i;`
355	62	simont	`end`
356			`end`
357
358			`endmodule`
359	88	simont

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