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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 116

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores interrupt control module                         ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   contains sfr's: tcon, ip, ie;                              ////
////   interrupt handling                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Jaka Simsic, jakas@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.6  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.5  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_int (clk, rst,
        wr_addr,
        data_in, bit_in,
        wr, wr_bit,
//timer interrupts
        tf0, tf1, t2_int,
        tr0, tr1,
//external interrupts
        ie0, ie1,
//uart interrupts
        uart_int,
//to cpu
        intr, reti, int_vec, ack,
//registers
        ie, tcon, ip);
 
input [7:0] wr_addr, data_in;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr;
output [7:0] int_vec,
             ie,
             tcon,
             ip;
 
reg [7:0] ip, ie, int_vec;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;
 
//
// isrc         processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg int_dept;
wire int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
 
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 1'b1;
assign cur_lev = int_lev[int_dept_1];
 
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
 
//
// int_ln       waiting interrupts on level n
// ip_ln        interrupts on level n
// int_src      interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
 
 
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
 
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
 
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
 
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
 
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
 
//
// IP
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
   ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
   ip[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// IE
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
   ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
   ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0])
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   int_vec <= #1 8'h00;
   int_dept <= #1 1'b0;
   isrc[0] <= #1 3'h0;
   isrc[1] <= #1 3'h0;
   int_proc <= #1 1'b0;
   int_lev[0] <= #1 1'b0;
   int_lev[1] <= #1 1'b0;
 end else if (reti) begin  // return from interrupt
   if (int_dept==2'b01)
     int_proc <= #1 1'b0;
   int_dept <= #1 int_dept - 2'b01;
  end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin  // interrupt on level 1
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l1[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 
 end else if ((ie[7]) & !int_proc & il0) begin  // interrupt on level 0
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l0[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 116

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores interrupt control module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// contains sfr's: tcon, ip, ie; ////`
10			`//// interrupt handling ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// - Jaka Simsic, jakas@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	116	simont	`// Revision 1.7 2003/03/28 17:45:57 simont`
50			`// change module name.`
51			`//`
52	90	simont	`// Revision 1.6 2003/01/13 14:14:41 simont`
53			`// replace some modules`
54			`//`
55	82	simont	`// Revision 1.5 2002/09/30 17:33:59 simont`
56			`// prepared header`
57			`//`
58			`//`
59
60
61			`include "oc8051_defines.v"
62
63			`//synopsys translate_off`
64			`include "oc8051_timescale.v"
65			`//synopsys translate_on`
66
67
68
69	116	simont	`module oc8051_int (clk, rst,`
70			`wr_addr,`
71			`data_in, bit_in,`
72			`wr, wr_bit,`
73	82	simont	`//timer interrupts`
74			`tf0, tf1, t2_int,`
75			`tr0, tr1,`
76			`//external interrupts`
77			`ie0, ie1,`
78			`//uart interrupts`
79			`uart_int,`
80			`//to cpu`
81	116	simont	`intr, reti, int_vec, ack,`
82			`//registers`
83			`ie, tcon, ip);`
84	82	simont
85	116	simont	`input [7:0] wr_addr, data_in;`
86	82	simont	`input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;`
87
88	116	simont	`output tr0, tr1, intr;`
89			`output [7:0] int_vec,`
90			`ie,`
91			`tcon,`
92			`ip;`
93	82	simont
94	116	simont	`reg [7:0] ip, ie, int_vec;`
95	82	simont
96			`reg [3:0] tcon_s;`
97	116	simont	`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;`
98	82	simont
99			`//`
100			`// isrc processing interrupt sources`
101			`// int_dept`
102			`wire [2:0] isrc_cur;`
103			`reg [2:0] isrc [1:0];`
104			`reg int_dept;`
105			`wire int_dept_1;`
106			`reg int_proc;`
107			`reg [1:0] int_lev [1:0];`
108			`wire cur_lev;`
109
110			`assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;`
111			`assign int_dept_1 = int_dept - 1'b1;`
112			`assign cur_lev = int_lev[int_dept_1];`
113
114			`//`
115			`// contains witch level of interrupts is running`
116			`//reg [1:0] int_levl, int_levl_w;`
117
118			`//`
119			`// int_ln waiting interrupts on level n`
120			`// ip_ln interrupts on level n`
121			`// int_src interrupt sources`
122			`wire [5:0] int_l0, int_l1;`
123			`wire [5:0] ip_l0, ip_l1;`
124			`wire [5:0] int_src;`
125			`wire il0, il1;`
126
127
128			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
129
130			`//`
131			`//interrupt priority`
132			`assign ip_l0 = ~ip[5:0];`
133			`assign ip_l1 = ip[5:0];`
134
135			`assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
136
137			`//`
138			`// waiting interrupts`
139			`assign int_l0 = ip_l0 & {ie[5:0]} & int_src;`
140			`assign int_l1 = ip_l1 & {ie[5:0]} & int_src;`
141			`assign il0 = \|int_l0;`
142			`assign il1 = \|int_l1;`
143
144			`//`
145			`// TCON`
146			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
147			`assign tr0 = tcon_s[2];`
148			`assign tr1 = tcon_s[3];`
149			`assign intr = \|int_vec;`
150
151
152			`//`
153			`// IP`
154			`always @(posedge clk or posedge rst)`
155			`begin`
156			`if (rst) begin`
157			ip <=#1 `OC8051_RST_IP;
158			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
159			`ip <= #1 data_in;`
160			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
161			`ip[wr_addr[2:0]] <= #1 bit_in;`
162			`end`
163
164			`//`
165			`// IE`
166			`always @(posedge clk or posedge rst)`
167			`begin`
168			`if (rst) begin`
169			ie <=#1 `OC8051_RST_IE;
170			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
171			`ie <= #1 data_in;`
172			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
173			`ie[wr_addr[2:0]] <= #1 bit_in;`
174			`end`
175
176			`//`
177			`// tcon_s`
178			`//`
179			`always @(posedge clk or posedge rst)`
180			`begin`
181			`if (rst) begin`
182			`tcon_s <=#1 4'b0000;`
183			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
184			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
185			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
186			`case (wr_addr[2:0])`
187			`3'b000: tcon_s[0] <= #1 bit_in;`
188			`3'b010: tcon_s[1] <= #1 bit_in;`
189			`3'b100: tcon_s[2] <= #1 bit_in;`
190			`3'b110: tcon_s[3] <= #1 bit_in;`
191			`endcase`
192			`end`
193			`end`
194
195			`//`
196			`// tf1 (tmod.7)`
197			`//`
198			`always @(posedge clk or posedge rst)`
199			`begin`
200			`if (rst) begin`
201			`tcon_tf1 <=#1 1'b0;`
202			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
203			`tcon_tf1 <= #1 data_in[7];`
204			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
205			`tcon_tf1 <= #1 bit_in;`
206			`end else if (!(tf1_buff) & (tf1)) begin`
207			`tcon_tf1 <= #1 1'b1;`
208			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
209			`tcon_tf1 <= #1 1'b0;`
210			`end`
211			`end`
212
213			`//`
214			`// tf0 (tmod.5)`
215			`//`
216			`always @(posedge clk or posedge rst)`
217			`begin`
218			`if (rst) begin`
219			`tcon_tf0 <=#1 1'b0;`
220			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
221			`tcon_tf0 <= #1 data_in[5];`
222			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
223			`tcon_tf0 <= #1 bit_in;`
224			`end else if (!(tf0_buff) & (tf0)) begin`
225			`tcon_tf0 <= #1 1'b1;`
226			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
227			`tcon_tf0 <= #1 1'b0;`
228			`end`
229			`end`
230
231
232			`//`
233			`// ie0 (tmod.1)`
234			`//`
235			`always @(posedge clk or posedge rst)`
236			`begin`
237			`if (rst) begin`
238			`tcon_ie0 <=#1 1'b0;`
239			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
240			`tcon_ie0 <= #1 data_in[1];`
241			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
242			`tcon_ie0 <= #1 bit_in;`
243			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
244			`tcon_ie0 <= #1 1'b1;`
245			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
246			`tcon_ie0 <= #1 1'b0;`
247			`end else if (!(tcon_s[0]) & (ie0)) begin`
248			`tcon_ie0 <= #1 1'b0;`
249			`end`
250			`end`
251
252
253			`//`
254			`// ie1 (tmod.3)`
255			`//`
256			`always @(posedge clk or posedge rst)`
257			`begin`
258			`if (rst) begin`
259			`tcon_ie1 <=#1 1'b0;`
260			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
261			`tcon_ie1 <= #1 data_in[3];`
262			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
263			`tcon_ie1 <= #1 bit_in;`
264			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
265			`tcon_ie1 <= #1 1'b1;`
266			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
267			`tcon_ie1 <= #1 1'b0;`
268			`end else if (!(tcon_s[1]) & (ie1)) begin`
269			`tcon_ie1 <= #1 1'b0;`
270			`end`
271			`end`
272
273			`//`
274			`// interrupt processing`
275			`always @(posedge clk or posedge rst)`
276			`begin`
277			`if (rst) begin`
278			`int_vec <= #1 8'h00;`
279			`int_dept <= #1 1'b0;`
280			`isrc[0] <= #1 3'h0;`
281			`isrc[1] <= #1 3'h0;`
282			`int_proc <= #1 1'b0;`
283			`int_lev[0] <= #1 1'b0;`
284			`int_lev[1] <= #1 1'b0;`
285			`end else if (reti) begin // return from interrupt`
286			`if (int_dept==2'b01)`
287			`int_proc <= #1 1'b0;`
288			`int_dept <= #1 int_dept - 2'b01;`
289			`end else if (((ie[7]) & (!cur_lev) \|\| !int_proc) & il1) begin // interrupt on level 1`
290			`int_proc <= #1 1'b1;`
291			int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
292			`int_dept <= #1 int_dept + 2'b01;`
293			`if (int_l1[0]) begin`
294			int_vec <= #1 `OC8051_INT_X0;
295			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
296			`end else if (int_l1[1]) begin`
297			int_vec <= #1 `OC8051_INT_T0;
298			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
299			`end else if (int_l1[2]) begin`
300			int_vec <= #1 `OC8051_INT_X1;
301			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
302			`end else if (int_l1[3]) begin`
303			int_vec <= #1 `OC8051_INT_T1;
304			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
305			`end else if (int_l1[4]) begin`
306			int_vec <= #1 `OC8051_INT_UART;
307			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
308			`end else if (int_l1[5]) begin`
309			int_vec <= #1 `OC8051_INT_T2;
310			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
311			`end`
312
313			`end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0`
314			`int_proc <= #1 1'b1;`
315			int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
316			`int_dept <= #1 int_dept + 2'b01;`
317			`if (int_l0[0]) begin`
318			int_vec <= #1 `OC8051_INT_X0;
319			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
320			`end else if (int_l0[1]) begin`
321			int_vec <= #1 `OC8051_INT_T0;
322			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
323			`end else if (int_l0[2]) begin`
324			int_vec <= #1 `OC8051_INT_X1;
325			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
326			`end else if (int_l0[3]) begin`
327			int_vec <= #1 `OC8051_INT_T1;
328			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
329			`end else if (int_l0[4]) begin`
330			int_vec <= #1 `OC8051_INT_UART;
331			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
332			`end else if (int_l0[5]) begin`
333			int_vec <= #1 `OC8051_INT_T2;
334			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
335			`end`
336			`end else begin`
337			`int_vec <= #1 8'h00;`
338			`end`
339			`end`
340
341
342			`always @(posedge clk or posedge rst)`
343			`if (rst) begin`
344			`tf0_buff <= #1 1'b0;`
345			`tf1_buff <= #1 1'b0;`
346			`ie0_buff <= #1 1'b0;`
347			`ie1_buff <= #1 1'b0;`
348			`end else begin`
349			`tf0_buff <= #1 tf0;`
350			`tf1_buff <= #1 tf1;`
351			`ie0_buff <= #1 ie0;`
352			`ie1_buff <= #1 ie1;`
353			`end`
354
355			`endmodule`