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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 17

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Line No. Rev Author Line
1 2 simont
//
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// version 1.0
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//
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//clk  clock (pin)
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//rst  reset (pin)
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//wr_addr  address for selecting different registers (input)
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//data_in  data input (input)
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//wr   read/write signal (input)
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//tf0  signal for timer interrupt 0 (input)
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//tf1  signal for timer interrupt 1 (input)
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//ie0   signal for external interrupt 0 (input)
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//ie1   signal for external interrupt 1 (input)
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//reti  return from interrupt signal (input)
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//int_src  describes interrupt source (output)
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//ip  ip register (internal)
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//ie  ie register (internal)
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//tcon  tcon register (internal)
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`include "oc8051_defines.v"
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//synopsys translate_off
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`include "oc8051_timescale.v"
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//synopsys translate_on
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33 4 markom
module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
34 2 simont
input [7:0] wr_addr, data_in, rd_addr;
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input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
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37 4 markom
output tr0, tr1, intr, bit_out;
38 2 simont
output [7:0] int_vec, data_out;
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40 17 simont
reg [7:0] ip, ie, int_vec, data_out;
41 2 simont
 
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reg [3:0] tcon_s;
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reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
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wire [7:0] tcon;
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//
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// isrc_cur     current interrupt source
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// isrc_w       waiting interrupt source
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reg [2:0] isrc_cur, isrc_w;
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//
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// contains witch level of interrupts is running
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reg [1:0] int_levl, int_levl_w;
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//
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// int_l0       waiting interrupts on level 0
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// int_l1       waiting interrupts on level 1
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wire [4:0] int_l0, int_l1;
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wire il0, il1;
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//reg set_tf0, set_tf1, set_ie0, set_ie1;
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reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
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//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
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assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
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assign tr0 = tcon_s[2];
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assign tr1 = tcon_s[3];
68 4 markom
assign intr = |int_vec;
69 2 simont
 
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assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
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assign il0 = |int_l0;
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assign il1 = |int_l1;
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   ip <=#1 `OC8051_RST_IP;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
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    ip <= #1 data_in;
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 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
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    ip[wr_addr[2:0]] <= #1 bit_in;
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end
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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   ie <=#1 `OC8051_RST_IE;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
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    ie <= #1 data_in;
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 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
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    ie[wr_addr[2:0]] <= #1 bit_in;
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end
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//
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// tcon_s
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//
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always @(posedge clk or posedge rst)
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begin
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 if (rst) begin
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//   tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
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   tcon_s <=#1 4'b0000;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
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 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
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   case (wr_addr[2:0])
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     3'b000: tcon_s[0] <= #1 bit_in;
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     3'b010: tcon_s[1] <= #1 bit_in;
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     3'b100: tcon_s[2] <= #1 bit_in;
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     3'b110: tcon_s[3] <= #1 bit_in;
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   endcase
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 end
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end
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//
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// tf1 (tmod.7)
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//
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always @(posedge clk or posedge rst)
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begin
120
 if (rst) begin
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//   tcon_tf1 <=#1 `OC8051_RST_TCON[7];
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   tcon_tf1 <=#1 1'b0;
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 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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   tcon_tf1 <= #1 data_in[7];
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 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
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   tcon_tf1 <= #1 bit_in;
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 end else if (!(tf1_buff) & (tf1)) begin
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   tcon_tf1 <= #1 1'b1;
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 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
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   tcon_tf1 <= #1 1'b0;
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 end
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end
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134
//
135
// tf0 (tmod.5)
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//
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always @(posedge clk or posedge rst)
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begin
139
 if (rst) begin
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//   tcon_tf0 <=#1 `OC8051_RST_TCON[5];
141
   tcon_tf0 <=#1 1'b0;
142
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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   tcon_tf0 <= #1 data_in[5];
144
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
145
   tcon_tf0 <= #1 bit_in;
146
 end else if (!(tf0_buff) & (tf0)) begin
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   tcon_tf0 <= #1 1'b1;
148
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
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   tcon_tf0 <= #1 1'b0;
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 end
151
end
152
 
153
 
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//
155
// ie0 (tmod.1)
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//
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always @(posedge clk or posedge rst)
158
begin
159
 if (rst) begin
160
//   tcon_ie0 <=#1 `OC8051_RST_TCON[1];
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   tcon_ie0 <=#1 1'b0;
162
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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   tcon_ie0 <= #1 data_in[1];
164
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
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   tcon_ie0 <= #1 bit_in;
166
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
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   tcon_ie0 <= #1 1'b1;
168
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
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   tcon_ie0 <= #1 1'b0;
170
 end else if (!(tcon_s[0]) & (ie0)) begin
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   tcon_ie0 <= #1 1'b0;
172
 end
173
end
174
 
175
 
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//
177
// ie1 (tmod.3)
178
//
179
always @(posedge clk or posedge rst)
180
begin
181
 if (rst) begin
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//   tcon_ie1 <=#1 `OC8051_RST_TCON[3];
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   tcon_ie1 <=#1 1'b0;
184
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
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   tcon_ie1 <= #1 data_in[3];
186
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
187
   tcon_ie1 <= #1 bit_in;
188
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
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   tcon_ie1 <= #1 1'b1;
190
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
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   tcon_ie1 <= #1 1'b0;
192
 end else if (!(tcon_s[1]) & (ie1)) begin
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   tcon_ie1 <= #1 1'b0;
194
 end
195
end
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always @(posedge clk or posedge rst)
199
begin
200
 if (rst) begin
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   int_vec <= #1 8'h00;
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   isrc_cur <= #1 `OC8051_ISRC_NO;
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   isrc_w <= #1 `OC8051_ISRC_NO;
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   int_levl <= #1 `OC8051_ILEV_NO;
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   int_levl_w <= #1 `OC8051_ILEV_NO;
206
 end else if (reti) begin  // return from interrupt
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   isrc_cur <= #1 isrc_w;
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   int_levl <= #1 int_levl_w;
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 end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin  // interrupt on level 1
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   isrc_w <= #1 isrc_cur;
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   int_levl <= #1 `OC8051_ILEV_L1;
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   int_levl_w <= #1 int_levl;
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   if (int_l1[0]) begin
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     int_vec <= #1 `OC8051_INT_X0;
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     isrc_cur <= #1 `OC8051_ISRC_IE0;
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   end else if (int_l1[1]) begin
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     int_vec <= #1 `OC8051_INT_T0;
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     isrc_cur <= #1 `OC8051_ISRC_TF0;
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   end else if (int_l1[2]) begin
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     int_vec <= #1 `OC8051_INT_X1;
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     isrc_cur <= #1 `OC8051_ISRC_IE1;
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   end else if (int_l1[3]) begin
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     int_vec <= #1 `OC8051_INT_T1;
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     isrc_cur <= #1 `OC8051_ISRC_TF1;
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   end else if (int_l1[4]) begin
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     int_vec <= #1 `OC8051_INT_UART;
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     isrc_cur <= #1 `OC8051_ISRC_UART;
228
   end
229
 end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin  // interrupt on level 0
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   int_levl <= #1 `OC8051_ILEV_L0;
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   if (int_l0[0]) begin
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     int_vec <= #1 `OC8051_INT_X0;
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     isrc_cur <= #1 `OC8051_ISRC_IE0;
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   end else if (int_l0[1]) begin
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     int_vec <= #1 `OC8051_INT_T0;
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     isrc_cur <= #1 `OC8051_ISRC_TF0;
237
   end else if (int_l0[2]) begin
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     int_vec <= #1 `OC8051_INT_X1;
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     isrc_cur <= #1 `OC8051_ISRC_IE1;
240
   end else if (int_l0[3]) begin
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     int_vec <= #1 `OC8051_INT_T1;
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     isrc_cur <= #1 `OC8051_ISRC_TF1;
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   end else if (int_l0[4]) begin
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     int_vec <= #1 `OC8051_INT_UART;
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     isrc_cur <= #1 `OC8051_ISRC_UART;
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   end
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 end else begin
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   int_vec <= #1 8'h00;
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 end
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end
251
 
252
 
253 4 markom
always @(posedge clk or posedge rst)
254 2 simont
begin
255 4 markom
  if (rst) data_out <= #1 8'h0;
256
  else if (wr & !wr_bit & (wr_addr==rd_addr) & (
257 2 simont
     (wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
258
    data_out <= #1 data_in;
259
  end else begin
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    case (rd_addr)
261
      `OC8051_SFR_IP: data_out <= #1 ip;
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      `OC8051_SFR_IE: data_out <= #1 ie;
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      default: data_out <= #1 tcon;
264
    endcase
265
  end
266
end
267
 
268 4 markom
always @(posedge clk or posedge rst)
269
  if (rst) begin
270
    tf0_buff <= #1 1'b0;
271
    tf1_buff <= #1 1'b0;
272
    ie0_buff <= #1 1'b0;
273
    ie1_buff <= #1 1'b0;
274
  end else begin
275
    tf0_buff <= #1 tf0;
276
    tf1_buff <= #1 tf1;
277
    ie0_buff <= #1 ie0;
278
    ie1_buff <= #1 ie1;
279
  end
280 2 simont
 
281 4 markom
always @(posedge clk or posedge rst)
282 2 simont
begin
283 4 markom
  if (rst) bit_out <= #1 1'b0;
284
  else if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) |
285 2 simont
     (wr_addr[7:3]==`OC8051_SFR_B_IE) | (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
286
    bit_out <= #1 bit_in;
287
  end else begin
288
    case (rd_addr[7:3])
289
      `OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
290
      `OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
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      default: bit_out <= #1 tcon[rd_addr[2:0]];
292
    endcase
293
  end
294
end
295
 
296
 
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endmodule

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