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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 17

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//
// version 1.0
//
 
 
 
//clk  clock (pin)
//rst  reset (pin)
//wr_addr  address for selecting different registers (input)
//data_in  data input (input)
//wr   read/write signal (input)
//tf0  signal for timer interrupt 0 (input)
//tf1  signal for timer interrupt 1 (input)
//ie0   signal for external interrupt 0 (input)
//ie1   signal for external interrupt 1 (input)
//reti  return from interrupt signal (input)
//int_src  describes interrupt source (output)
//ip  ip register (internal)
//ie  ie register (internal)
//tcon  tcon register (internal)
 
 
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc_cur     current interrupt source
// isrc_w       waiting interrupt source
reg [2:0] isrc_cur, isrc_w;
 
//
// contains witch level of interrupts is running
reg [1:0] int_levl, int_levl_w;
 
//
// int_l0       waiting interrupts on level 0
// int_l1       waiting interrupts on level 1
wire [4:0] int_l0, int_l1;
wire il0, il1;
 
//reg set_tf0, set_tf1, set_ie0, set_ie1;
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;
 
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
assign il0 = |int_l0;
assign il1 = |int_l1;
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
    ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
    ip[wr_addr[2:0]] <= #1 bit_in;
end
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
    ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
    ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0])
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_tf1 <=#1 `OC8051_RST_TCON[7];
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_tf0 <=#1 `OC8051_RST_TCON[5];
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie0 <=#1 `OC8051_RST_TCON[1];
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie1 <=#1 `OC8051_RST_TCON[3];
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   int_vec <= #1 8'h00;
   isrc_cur <= #1 `OC8051_ISRC_NO;
   isrc_w <= #1 `OC8051_ISRC_NO;
   int_levl <= #1 `OC8051_ILEV_NO;
   int_levl_w <= #1 `OC8051_ILEV_NO;
 end else if (reti) begin  // return from interrupt
   isrc_cur <= #1 isrc_w;
   int_levl <= #1 int_levl_w;
 end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin  // interrupt on level 1
   isrc_w <= #1 isrc_cur;
   int_levl <= #1 `OC8051_ILEV_L1;
   int_levl_w <= #1 int_levl;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc_cur <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc_cur <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc_cur <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc_cur <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc_cur <= #1 `OC8051_ISRC_UART;
   end
 end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin  // interrupt on level 0
   int_levl <= #1 `OC8051_ILEV_L0;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc_cur <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc_cur <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc_cur <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc_cur <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc_cur <= #1 `OC8051_ISRC_UART;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & (
     (wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_IP: data_out <= #1 ip;
      `OC8051_SFR_IE: data_out <= #1 ie;
      default: data_out <= #1 tcon;
    endcase
  end
end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) |
     (wr_addr[7:3]==`OC8051_SFR_B_IE) | (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
    bit_out <= #1 bit_in;
  end else begin
    case (rd_addr[7:3])
      `OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
      `OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
      default: bit_out <= #1 tcon[rd_addr[2:0]];
    endcase
  end
end
 
 
endmodule

Line No.	Rev	Author	Line
1	2	simont	`//`
2			`// version 1.0`
3			`//`
4
5
6
7			`//clk clock (pin)`
8			`//rst reset (pin)`
9			`//wr_addr address for selecting different registers (input)`
10			`//data_in data input (input)`
11			`//wr read/write signal (input)`
12			`//tf0 signal for timer interrupt 0 (input)`
13			`//tf1 signal for timer interrupt 1 (input)`
14			`//ie0 signal for external interrupt 0 (input)`
15			`//ie1 signal for external interrupt 1 (input)`
16			`//reti return from interrupt signal (input)`
17			`//int_src describes interrupt source (output)`
18			`//ip ip register (internal)`
19			`//ie ie register (internal)`
20			`//tcon tcon register (internal)`
21
22
23
24
25			`include "oc8051_defines.v"
26
27			`//synopsys translate_off`
28			`include "oc8051_timescale.v"
29			`//synopsys translate_on`
30
31
32
33	4	markom	`module oc0851_int (clk, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit, tf0, tf1, intr, ie0, ie1, rst, reti, int_vec, tr0, tr1, uart, ack);`
34	2	simont	`input [7:0] wr_addr, data_in, rd_addr;`
35			`input wr, tf0, tf1, ie0, ie1, clk, rst, reti, wr_bit, bit_in, uart, ack;`
36
37	4	markom	`output tr0, tr1, intr, bit_out;`
38	2	simont	`output [7:0] int_vec, data_out;`
39
40	17	simont	`reg [7:0] ip, ie, int_vec, data_out;`
41	2	simont
42			`reg [3:0] tcon_s;`
43			`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`
44			`wire [7:0] tcon;`
45
46			`//`
47			`// isrc_cur current interrupt source`
48			`// isrc_w waiting interrupt source`
49			`reg [2:0] isrc_cur, isrc_w;`
50
51			`//`
52			`// contains witch level of interrupts is running`
53			`reg [1:0] int_levl, int_levl_w;`
54
55			`//`
56			`// int_l0 waiting interrupts on level 0`
57			`// int_l1 waiting interrupts on level 1`
58			`wire [4:0] int_l0, int_l1;`
59			`wire il0, il1;`
60
61			`//reg set_tf0, set_tf1, set_ie0, set_ie1;`
62			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
63			`//reg tf0_ack, tf1_ack, ie0_ack, ie1_ack;`
64
65			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
66			`assign tr0 = tcon_s[2];`
67			`assign tr1 = tcon_s[3];`
68	4	markom	`assign intr = \|int_vec;`
69	2	simont
70			`assign int_l0 = ~ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
71			`assign int_l1 = ip[4:0] & ie[4:0] & {uart, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
72			`assign il0 = \|int_l0;`
73			`assign il1 = \|int_l1;`
74
75			`always @(posedge clk or posedge rst)`
76			`begin`
77			`if (rst) begin`
78			ip <=#1 `OC8051_RST_IP;
79			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
80			`ip <= #1 data_in;`
81			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
82			`ip[wr_addr[2:0]] <= #1 bit_in;`
83			`end`
84
85			`always @(posedge clk or posedge rst)`
86			`begin`
87			`if (rst) begin`
88			ie <=#1 `OC8051_RST_IE;
89			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
90			`ie <= #1 data_in;`
91			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
92			`ie[wr_addr[2:0]] <= #1 bit_in;`
93			`end`
94
95			`//`
96			`// tcon_s`
97			`//`
98			`always @(posedge clk or posedge rst)`
99			`begin`
100			`if (rst) begin`
101			// tcon_s <=#1 {`OC8051_RST_TCON[6], `OC8051_RST_TCON[4], `OC8051_RST_TCON[2], `OC8051_RST_TCON[0]};
102			`tcon_s <=#1 4'b0000;`
103			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
104			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
105			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
106			`case (wr_addr[2:0])`
107			`3'b000: tcon_s[0] <= #1 bit_in;`
108			`3'b010: tcon_s[1] <= #1 bit_in;`
109			`3'b100: tcon_s[2] <= #1 bit_in;`
110			`3'b110: tcon_s[3] <= #1 bit_in;`
111			`endcase`
112			`end`
113			`end`
114
115			`//`
116			`// tf1 (tmod.7)`
117			`//`
118			`always @(posedge clk or posedge rst)`
119			`begin`
120			`if (rst) begin`
121			// tcon_tf1 <=#1 `OC8051_RST_TCON[7];
122			`tcon_tf1 <=#1 1'b0;`
123			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
124			`tcon_tf1 <= #1 data_in[7];`
125			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
126			`tcon_tf1 <= #1 bit_in;`
127			`end else if (!(tf1_buff) & (tf1)) begin`
128			`tcon_tf1 <= #1 1'b1;`
129			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
130			`tcon_tf1 <= #1 1'b0;`
131			`end`
132			`end`
133
134			`//`
135			`// tf0 (tmod.5)`
136			`//`
137			`always @(posedge clk or posedge rst)`
138			`begin`
139			`if (rst) begin`
140			// tcon_tf0 <=#1 `OC8051_RST_TCON[5];
141			`tcon_tf0 <=#1 1'b0;`
142			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
143			`tcon_tf0 <= #1 data_in[5];`
144			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
145			`tcon_tf0 <= #1 bit_in;`
146			`end else if (!(tf0_buff) & (tf0)) begin`
147			`tcon_tf0 <= #1 1'b1;`
148			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
149			`tcon_tf0 <= #1 1'b0;`
150			`end`
151			`end`
152
153
154			`//`
155			`// ie0 (tmod.1)`
156			`//`
157			`always @(posedge clk or posedge rst)`
158			`begin`
159			`if (rst) begin`
160			// tcon_ie0 <=#1 `OC8051_RST_TCON[1];
161			`tcon_ie0 <=#1 1'b0;`
162			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
163			`tcon_ie0 <= #1 data_in[1];`
164			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
165			`tcon_ie0 <= #1 bit_in;`
166			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
167			`tcon_ie0 <= #1 1'b1;`
168			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
169			`tcon_ie0 <= #1 1'b0;`
170			`end else if (!(tcon_s[0]) & (ie0)) begin`
171			`tcon_ie0 <= #1 1'b0;`
172			`end`
173			`end`
174
175
176			`//`
177			`// ie1 (tmod.3)`
178			`//`
179			`always @(posedge clk or posedge rst)`
180			`begin`
181			`if (rst) begin`
182			// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
183			`tcon_ie1 <=#1 1'b0;`
184			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
185			`tcon_ie1 <= #1 data_in[3];`
186			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
187			`tcon_ie1 <= #1 bit_in;`
188			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
189			`tcon_ie1 <= #1 1'b1;`
190			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
191			`tcon_ie1 <= #1 1'b0;`
192			`end else if (!(tcon_s[1]) & (ie1)) begin`
193			`tcon_ie1 <= #1 1'b0;`
194			`end`
195			`end`
196
197
198			`always @(posedge clk or posedge rst)`
199			`begin`
200			`if (rst) begin`
201			`int_vec <= #1 8'h00;`
202			isrc_cur <= #1 `OC8051_ISRC_NO;
203			isrc_w <= #1 `OC8051_ISRC_NO;
204			int_levl <= #1 `OC8051_ILEV_NO;
205			int_levl_w <= #1 `OC8051_ILEV_NO;
206			`end else if (reti) begin // return from interrupt`
207			`isrc_cur <= #1 isrc_w;`
208			`int_levl <= #1 int_levl_w;`
209			end else if ((ie[7]) & (int_levl!=`OC8051_ILEV_L1) & (il1)) begin // interrupt on level 1
210			`isrc_w <= #1 isrc_cur;`
211			int_levl <= #1 `OC8051_ILEV_L1;
212			`int_levl_w <= #1 int_levl;`
213			`if (int_l1[0]) begin`
214			int_vec <= #1 `OC8051_INT_X0;
215			isrc_cur <= #1 `OC8051_ISRC_IE0;
216			`end else if (int_l1[1]) begin`
217			int_vec <= #1 `OC8051_INT_T0;
218			isrc_cur <= #1 `OC8051_ISRC_TF0;
219			`end else if (int_l1[2]) begin`
220			int_vec <= #1 `OC8051_INT_X1;
221			isrc_cur <= #1 `OC8051_ISRC_IE1;
222			`end else if (int_l1[3]) begin`
223			int_vec <= #1 `OC8051_INT_T1;
224			isrc_cur <= #1 `OC8051_ISRC_TF1;
225			`end else if (int_l1[4]) begin`
226			int_vec <= #1 `OC8051_INT_UART;
227			isrc_cur <= #1 `OC8051_ISRC_UART;
228			`end`
229			end else if ((ie[7]) & (int_levl==`OC8051_ILEV_NO) & (il0)) begin // interrupt on level 0
230			int_levl <= #1 `OC8051_ILEV_L0;
231			`if (int_l0[0]) begin`
232			int_vec <= #1 `OC8051_INT_X0;
233			isrc_cur <= #1 `OC8051_ISRC_IE0;
234			`end else if (int_l0[1]) begin`
235			int_vec <= #1 `OC8051_INT_T0;
236			isrc_cur <= #1 `OC8051_ISRC_TF0;
237			`end else if (int_l0[2]) begin`
238			int_vec <= #1 `OC8051_INT_X1;
239			isrc_cur <= #1 `OC8051_ISRC_IE1;
240			`end else if (int_l0[3]) begin`
241			int_vec <= #1 `OC8051_INT_T1;
242			isrc_cur <= #1 `OC8051_ISRC_TF1;
243			`end else if (int_l0[4]) begin`
244			int_vec <= #1 `OC8051_INT_UART;
245			isrc_cur <= #1 `OC8051_ISRC_UART;
246			`end`
247			`end else begin`
248			`int_vec <= #1 8'h00;`
249			`end`
250			`end`
251
252
253	4	markom	`always @(posedge clk or posedge rst)`
254	2	simont	`begin`
255	4	markom	`if (rst) data_out <= #1 8'h0;`
256			`else if (wr & !wr_bit & (wr_addr==rd_addr) & (`
257	2	simont	(wr_addr==`OC8051_SFR_IP) \| (wr_addr==`OC8051_SFR_IE) \| (wr_addr==`OC8051_SFR_TCON))) begin
258			`data_out <= #1 data_in;`
259			`end else begin`
260			`case (rd_addr)`
261			`OC8051_SFR_IP: data_out <= #1 ip;
262			`OC8051_SFR_IE: data_out <= #1 ie;
263			`default: data_out <= #1 tcon;`
264			`endcase`
265			`end`
266			`end`
267
268	4	markom	`always @(posedge clk or posedge rst)`
269			`if (rst) begin`
270			`tf0_buff <= #1 1'b0;`
271			`tf1_buff <= #1 1'b0;`
272			`ie0_buff <= #1 1'b0;`
273			`ie1_buff <= #1 1'b0;`
274			`end else begin`
275			`tf0_buff <= #1 tf0;`
276			`tf1_buff <= #1 tf1;`
277			`ie0_buff <= #1 ie0;`
278			`ie1_buff <= #1 ie1;`
279			`end`
280	2	simont
281	4	markom	`always @(posedge clk or posedge rst)`
282	2	simont	`begin`
283	4	markom	`if (rst) bit_out <= #1 1'b0;`
284			else if (wr & wr_bit & (wr_addr==rd_addr) & ((wr_addr[7:3]==`OC8051_SFR_B_IP) \|
285	2	simont	(wr_addr[7:3]==`OC8051_SFR_B_IE) \| (wr_addr[7:3]==`OC8051_SFR_B_TCON))) begin
286			`bit_out <= #1 bit_in;`
287			`end else begin`
288			`case (rd_addr[7:3])`
289			`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
290			`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
291			`default: bit_out <= #1 tcon[rd_addr[2:0]];`
292			`endcase`
293			`end`
294			`end`
295
296
297			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 17