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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 82

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores interrupt control module                         ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   contains sfr's: tcon, ip, ie;                              ////
////   interrupt handling                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Jaka Simsic, jakas@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc0851_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,
//timer interrupts
        tf0, tf1, t2_int,
        tr0, tr1,
//external interrupts
        ie0, ie1,
//uart interrupts
        uart_int,
//to cpu
        intr, reti, int_vec, ack);
 
input [7:0] wr_addr, data_in, rd_addr;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr, bit_out;
output [7:0] int_vec, data_out;
 
reg [7:0] ip, ie, int_vec, data_out;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;
wire [7:0] tcon;
 
//
// isrc         processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg int_dept;
wire int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
 
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 1'b1;
assign cur_lev = int_lev[int_dept_1];
 
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
 
//
// int_ln       waiting interrupts on level n
// ip_ln        interrupts on level n
// int_src      interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
 
 
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
 
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
 
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
 
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
 
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
 
//
// IP
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
   ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
   ip[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// IE
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
   ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
   ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0])
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
//   tcon_ie1 <=#1 `OC8051_RST_TCON[3];
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   int_vec <= #1 8'h00;
   int_dept <= #1 1'b0;
   isrc[0] <= #1 3'h0;
   isrc[1] <= #1 3'h0;
   int_proc <= #1 1'b0;
   int_lev[0] <= #1 1'b0;
   int_lev[1] <= #1 1'b0;
 end else if (reti) begin  // return from interrupt
   if (int_dept==2'b01)
     int_proc <= #1 1'b0;
   int_dept <= #1 int_dept - 2'b01;
  end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin  // interrupt on level 1
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l1[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 
 end else if ((ie[7]) & !int_proc & il0) begin  // interrupt on level 0
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l0[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & (
     (wr_addr==`OC8051_SFR_IP) | (wr_addr==`OC8051_SFR_IE) | (wr_addr==`OC8051_SFR_TCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_IP: data_out <= #1 ip;
      `OC8051_SFR_IE: data_out <= #1 ie0;
      default: data_out <= #1 tcon;
    endcase
  end
end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
always @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (wr_addr==rd_addr)) begin
    bit_out <= #1 bit_in;
  end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin
    bit_out <= #1 data_in[rd_addr[2:0]];
  end else begin
    case (rd_addr[7:3])
      `OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
      `OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
      default: bit_out <= #1 tcon[rd_addr[2:0]];
    endcase
  end
end
 
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 82

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores interrupt control module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// contains sfr's: tcon, ip, ie; ////`
10			`//// interrupt handling ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// - Jaka Simsic, jakas@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49			`// Revision 1.5 2002/09/30 17:33:59 simont`
50			`// prepared header`
51			`//`
52			`//`
53
54
55			`include "oc8051_defines.v"
56
57			`//synopsys translate_off`
58			`include "oc8051_timescale.v"
59			`//synopsys translate_on`
60
61
62
63			`module oc0851_int (clk, rst, wr_addr, rd_addr, data_in, bit_in, data_out, bit_out, wr, wr_bit,`
64			`//timer interrupts`
65			`tf0, tf1, t2_int,`
66			`tr0, tr1,`
67			`//external interrupts`
68			`ie0, ie1,`
69			`//uart interrupts`
70			`uart_int,`
71			`//to cpu`
72			`intr, reti, int_vec, ack);`
73
74			`input [7:0] wr_addr, data_in, rd_addr;`
75			`input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;`
76
77			`output tr0, tr1, intr, bit_out;`
78			`output [7:0] int_vec, data_out;`
79
80			`reg [7:0] ip, ie, int_vec, data_out;`
81
82			`reg [3:0] tcon_s;`
83			`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0, bit_out;`
84			`wire [7:0] tcon;`
85
86			`//`
87			`// isrc processing interrupt sources`
88			`// int_dept`
89			`wire [2:0] isrc_cur;`
90			`reg [2:0] isrc [1:0];`
91			`reg int_dept;`
92			`wire int_dept_1;`
93			`reg int_proc;`
94			`reg [1:0] int_lev [1:0];`
95			`wire cur_lev;`
96
97			`assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;`
98			`assign int_dept_1 = int_dept - 1'b1;`
99			`assign cur_lev = int_lev[int_dept_1];`
100
101			`//`
102			`// contains witch level of interrupts is running`
103			`//reg [1:0] int_levl, int_levl_w;`
104
105			`//`
106			`// int_ln waiting interrupts on level n`
107			`// ip_ln interrupts on level n`
108			`// int_src interrupt sources`
109			`wire [5:0] int_l0, int_l1;`
110			`wire [5:0] ip_l0, ip_l1;`
111			`wire [5:0] int_src;`
112			`wire il0, il1;`
113
114
115			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
116
117			`//`
118			`//interrupt priority`
119			`assign ip_l0 = ~ip[5:0];`
120			`assign ip_l1 = ip[5:0];`
121
122			`assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
123
124			`//`
125			`// waiting interrupts`
126			`assign int_l0 = ip_l0 & {ie[5:0]} & int_src;`
127			`assign int_l1 = ip_l1 & {ie[5:0]} & int_src;`
128			`assign il0 = \|int_l0;`
129			`assign il1 = \|int_l1;`
130
131			`//`
132			`// TCON`
133			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
134			`assign tr0 = tcon_s[2];`
135			`assign tr1 = tcon_s[3];`
136			`assign intr = \|int_vec;`
137
138
139			`//`
140			`// IP`
141			`always @(posedge clk or posedge rst)`
142			`begin`
143			`if (rst) begin`
144			ip <=#1 `OC8051_RST_IP;
145			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
146			`ip <= #1 data_in;`
147			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
148			`ip[wr_addr[2:0]] <= #1 bit_in;`
149			`end`
150
151			`//`
152			`// IE`
153			`always @(posedge clk or posedge rst)`
154			`begin`
155			`if (rst) begin`
156			ie <=#1 `OC8051_RST_IE;
157			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
158			`ie <= #1 data_in;`
159			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
160			`ie[wr_addr[2:0]] <= #1 bit_in;`
161			`end`
162
163			`//`
164			`// tcon_s`
165			`//`
166			`always @(posedge clk or posedge rst)`
167			`begin`
168			`if (rst) begin`
169			`tcon_s <=#1 4'b0000;`
170			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
171			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
172			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
173			`case (wr_addr[2:0])`
174			`3'b000: tcon_s[0] <= #1 bit_in;`
175			`3'b010: tcon_s[1] <= #1 bit_in;`
176			`3'b100: tcon_s[2] <= #1 bit_in;`
177			`3'b110: tcon_s[3] <= #1 bit_in;`
178			`endcase`
179			`end`
180			`end`
181
182			`//`
183			`// tf1 (tmod.7)`
184			`//`
185			`always @(posedge clk or posedge rst)`
186			`begin`
187			`if (rst) begin`
188			`tcon_tf1 <=#1 1'b0;`
189			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
190			`tcon_tf1 <= #1 data_in[7];`
191			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
192			`tcon_tf1 <= #1 bit_in;`
193			`end else if (!(tf1_buff) & (tf1)) begin`
194			`tcon_tf1 <= #1 1'b1;`
195			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
196			`tcon_tf1 <= #1 1'b0;`
197			`end`
198			`end`
199
200			`//`
201			`// tf0 (tmod.5)`
202			`//`
203			`always @(posedge clk or posedge rst)`
204			`begin`
205			`if (rst) begin`
206			`tcon_tf0 <=#1 1'b0;`
207			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
208			`tcon_tf0 <= #1 data_in[5];`
209			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
210			`tcon_tf0 <= #1 bit_in;`
211			`end else if (!(tf0_buff) & (tf0)) begin`
212			`tcon_tf0 <= #1 1'b1;`
213			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
214			`tcon_tf0 <= #1 1'b0;`
215			`end`
216			`end`
217
218
219			`//`
220			`// ie0 (tmod.1)`
221			`//`
222			`always @(posedge clk or posedge rst)`
223			`begin`
224			`if (rst) begin`
225			`tcon_ie0 <=#1 1'b0;`
226			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
227			`tcon_ie0 <= #1 data_in[1];`
228			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
229			`tcon_ie0 <= #1 bit_in;`
230			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
231			`tcon_ie0 <= #1 1'b1;`
232			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
233			`tcon_ie0 <= #1 1'b0;`
234			`end else if (!(tcon_s[0]) & (ie0)) begin`
235			`tcon_ie0 <= #1 1'b0;`
236			`end`
237			`end`
238
239
240			`//`
241			`// ie1 (tmod.3)`
242			`//`
243			`always @(posedge clk or posedge rst)`
244			`begin`
245			`if (rst) begin`
246			// tcon_ie1 <=#1 `OC8051_RST_TCON[3];
247			`tcon_ie1 <=#1 1'b0;`
248			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
249			`tcon_ie1 <= #1 data_in[3];`
250			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
251			`tcon_ie1 <= #1 bit_in;`
252			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
253			`tcon_ie1 <= #1 1'b1;`
254			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
255			`tcon_ie1 <= #1 1'b0;`
256			`end else if (!(tcon_s[1]) & (ie1)) begin`
257			`tcon_ie1 <= #1 1'b0;`
258			`end`
259			`end`
260
261			`//`
262			`// interrupt processing`
263			`always @(posedge clk or posedge rst)`
264			`begin`
265			`if (rst) begin`
266			`int_vec <= #1 8'h00;`
267			`int_dept <= #1 1'b0;`
268			`isrc[0] <= #1 3'h0;`
269			`isrc[1] <= #1 3'h0;`
270			`int_proc <= #1 1'b0;`
271			`int_lev[0] <= #1 1'b0;`
272			`int_lev[1] <= #1 1'b0;`
273			`end else if (reti) begin // return from interrupt`
274			`if (int_dept==2'b01)`
275			`int_proc <= #1 1'b0;`
276			`int_dept <= #1 int_dept - 2'b01;`
277			`end else if (((ie[7]) & (!cur_lev) \|\| !int_proc) & il1) begin // interrupt on level 1`
278			`int_proc <= #1 1'b1;`
279			int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
280			`int_dept <= #1 int_dept + 2'b01;`
281			`if (int_l1[0]) begin`
282			int_vec <= #1 `OC8051_INT_X0;
283			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
284			`end else if (int_l1[1]) begin`
285			int_vec <= #1 `OC8051_INT_T0;
286			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
287			`end else if (int_l1[2]) begin`
288			int_vec <= #1 `OC8051_INT_X1;
289			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
290			`end else if (int_l1[3]) begin`
291			int_vec <= #1 `OC8051_INT_T1;
292			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
293			`end else if (int_l1[4]) begin`
294			int_vec <= #1 `OC8051_INT_UART;
295			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
296			`end else if (int_l1[5]) begin`
297			int_vec <= #1 `OC8051_INT_T2;
298			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
299			`end`
300
301			`end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0`
302			`int_proc <= #1 1'b1;`
303			int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
304			`int_dept <= #1 int_dept + 2'b01;`
305			`if (int_l0[0]) begin`
306			int_vec <= #1 `OC8051_INT_X0;
307			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
308			`end else if (int_l0[1]) begin`
309			int_vec <= #1 `OC8051_INT_T0;
310			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
311			`end else if (int_l0[2]) begin`
312			int_vec <= #1 `OC8051_INT_X1;
313			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
314			`end else if (int_l0[3]) begin`
315			int_vec <= #1 `OC8051_INT_T1;
316			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
317			`end else if (int_l0[4]) begin`
318			int_vec <= #1 `OC8051_INT_UART;
319			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
320			`end else if (int_l0[5]) begin`
321			int_vec <= #1 `OC8051_INT_T2;
322			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
323			`end`
324			`end else begin`
325			`int_vec <= #1 8'h00;`
326			`end`
327			`end`
328
329
330			`always @(posedge clk or posedge rst)`
331			`begin`
332			`if (rst) data_out <= #1 8'h0;`
333			`else if (wr & !wr_bit & (wr_addr==rd_addr) & (`
334			(wr_addr==`OC8051_SFR_IP) \| (wr_addr==`OC8051_SFR_IE) \| (wr_addr==`OC8051_SFR_TCON))) begin
335			`data_out <= #1 data_in;`
336			`end else begin`
337			`case (rd_addr)`
338			`OC8051_SFR_IP: data_out <= #1 ip;
339			`OC8051_SFR_IE: data_out <= #1 ie0;
340			`default: data_out <= #1 tcon;`
341			`endcase`
342			`end`
343			`end`
344
345			`always @(posedge clk or posedge rst)`
346			`if (rst) begin`
347			`tf0_buff <= #1 1'b0;`
348			`tf1_buff <= #1 1'b0;`
349			`ie0_buff <= #1 1'b0;`
350			`ie1_buff <= #1 1'b0;`
351			`end else begin`
352			`tf0_buff <= #1 tf0;`
353			`tf1_buff <= #1 tf1;`
354			`ie0_buff <= #1 ie0;`
355			`ie1_buff <= #1 ie1;`
356			`end`
357
358			`always @(posedge clk or posedge rst)`
359			`begin`
360			`if (rst) bit_out <= #1 1'b0;`
361			`else if (wr & wr_bit & (wr_addr==rd_addr)) begin`
362			`bit_out <= #1 bit_in;`
363			`end else if ((rd_addr[7:3]==wr_addr[7:3]) & wr & !wr_bit) begin`
364			`bit_out <= #1 data_in[rd_addr[2:0]];`
365			`end else begin`
366			`case (rd_addr[7:3])`
367			`OC8051_SFR_B_IP: bit_out <= #1 ip[rd_addr[2:0]];
368			`OC8051_SFR_B_IE: bit_out <= #1 ie[rd_addr[2:0]];
369			`default: bit_out <= #1 tcon[rd_addr[2:0]];`
370			`endcase`
371			`end`
372			`end`
373
374
375			`endmodule`