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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_memory_interface.v] - Blame information for rev 140

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 memory interface                                       ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   comunication betwen cpu and memory                         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.5  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.4  2003/04/16 10:04:09  simont
// chance idat_ir to 24 bit wide
//
// Revision 1.3  2003/04/11 10:05:08  simont
// Change pc add value from 23'h to 16'h
//
// Revision 1.2  2003/04/09 16:24:03  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.1  2003/01/13 14:13:12  simont
// initial import
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_memory_interface (clk, rst,
//decoder
  wr_i, wr_bit_i, rd_sel, wr_sel,
  pc_wr_sel, pc_wr, pc, rd,
  mem_wait, mem_act, istb,
//internal ram
  wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,
 
  bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,
 
//program rom
  iadr_o, ea, ea_int,
  op1_out, op2_out, op3_out,
//internal
  op1_i, op2_i, op3_i,
//external
  iack_i, istb_o, idat_i,
 
//external data ram
  dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,
//interrupt interface
  intr, int_v, int_ack,
 
//alu
  des_acc, des1, des2,
 
//sfr's
  dptr, ri, sp,  sp_w, rn, acc, reti);
 
input bit_in, sfr_bit, dack_i;
input [2:0] mem_act;
input [7:0] in_ram, sfr, acc, sp_w;
input [31:0] idat_i;
 
output bit_out, mem_wait, reti;
output [7:0] iram_out, wr_dat;
 
reg bit_out, reti;
reg [7:0] iram_out, sp_r;
reg       rd_addr_r;
input clk, rst, wr_i, wr_bit_i;
output wr_o, wr_bit_o;
 
//????
reg dack_ir;
reg [7:0] ddat_ir;
reg [23:0] idat_ir;
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
input iack_i;
input [7:0] des_acc, des1, des2;
output [15:0] iadr_o;
 
wire ea_rom_sel;
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
input [7:0] ri, ddat_i;
input [15:0] dptr;
 
output dstb_o, dwe_o;
output [7:0] ddat_o;
output [15:0] dadr_o;
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
input [2:0] rd_sel, wr_sel;
input [4:0] rn;
input [7:0] sp;
 
output rd_ind, wr_ind;
output [7:0] wr_addr, rd_addr;
reg rd_ind, wr_ind;
reg [7:0] wr_addr, rd_addr;
 
reg [4:0] rn_r;
reg [7:0] ri_r, imm_r, imm2_r, op1_r;
wire [7:0] imm, imm2;
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
input intr, rd, ea, ea_int, istb;
input [7:0] op1_i, op2_i, op3_i, int_v;
output int_ack, istb_o;
output [7:0] op1_out, op3_out, op2_out;
 
reg int_ack_t, int_ack, int_ack_buff;
reg [7:0] int_vec_buff;
reg [7:0] op1_out, op2_buff, op3_buff;
reg [7:0] op1_o, op2_o, op3_o;
reg [7:0] op1_xt, op2_xt, op3_xt;
 
wire [7:0] op1, op2, op3, op2_direct;
//wire op_sel;
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
input [2:0] pc_wr_sel;
 
input pc_wr;
output [15:0] pc;
 
 
reg [15:0] pc;
 
//
//pc            program counter register, save current value
reg [15:0] pc_buf;
wire [15:0] alu;
 
//
// wr_lo        write low: used in reti instruction, write only low byte of pc
// ini_buff     interrupt buffer: used to prevent interrupting in the middle of executin instructions
reg int_buff, int_buff1;
 
 
//
//
////////////////////////////
reg istb_t, imem_wait, dstb_o, dwe_o;
//reg [3:0] mem_act_r;
reg [7:0] ddat_o;
reg [15:0] iadr_t, dadr_ot;
reg dmem_wait;
wire pc_wait;
wire [1:0] bank;
//wire pis_l;
wire [15:0] iadr_ot;
wire [7:0] isr_call;
 
assign bank = rn[4:3];
assign imm = op2_out;
assign imm2 = op3_out;
assign alu = {des2, des_acc};
assign ea_rom_sel = ea && ea_int;
assign wr_o = wr_i;
assign wr_bit_o = wr_bit_i;
 
assign mem_wait = dmem_wait || imem_wait;
assign istb_o = (istb || istb_t) && !dstb_o && !ea_rom_sel;
 
assign pc_wait = rd && (ea_rom_sel || (!istb_t && iack_i));
 
assign wr_dat = des1;
 
 
/////////////////////////////
//
//  ram_select
//
/////////////////////////////
always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)
begin
  if (rd_addr_r && !rd_ind) begin
    iram_out = sfr;
    bit_out = sfr_bit;
  end else begin
    iram_out = in_ram;
    bit_out = bit_in;
  end
end
 
/////////////////////////////
//
// ram_adr_sel
//
/////////////////////////////
 
always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)
begin
  case (rd_sel)
    `OC8051_RRS_RN   : rd_addr = {3'h0, rn};
    `OC8051_RRS_I    : rd_addr = ri;
    `OC8051_RRS_D    : rd_addr = imm;
    `OC8051_RRS_SP   : rd_addr = sp;
 
    `OC8051_RRS_B    : rd_addr = `OC8051_SFR_B;
    `OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
    `OC8051_RRS_PSW  : rd_addr = `OC8051_SFR_PSW;
    `OC8051_RRS_ACC  : rd_addr = `OC8051_SFR_ACC;
    default          : rd_addr = 2'bxx;
  endcase
 
end
 
 
//
//
always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])
begin
  case (wr_sel)
    `OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
    `OC8051_RWS_I  : wr_addr = ri_r;
    `OC8051_RWS_D  : wr_addr = imm_r;
    `OC8051_RWS_SP : wr_addr = sp_w;
    `OC8051_RWS_D3 : wr_addr = imm2_r;
    `OC8051_RWS_B  : wr_addr = `OC8051_SFR_B;
    default        : wr_addr = 2'bxx;
  endcase
end
 
always @(posedge clk or posedge rst)
  if (rst)
    rd_ind <= #1 1'b0;
  else if ((rd_sel==`OC8051_RRS_I) || (rd_sel==`OC8051_RRS_SP))
    rd_ind <= #1 1'b1;
  else
    rd_ind <= #1 1'b0;
 
always @(wr_sel)
  if ((wr_sel==`OC8051_RWS_I) || (wr_sel==`OC8051_RWS_SP))
    wr_ind = 1'b1;
  else
    wr_ind = 1'b0;
 
 
/////////////////////////////
//
//  rom_addr_sel
//
/////////////////////////////
//
// output address is alu destination
// (instructions MOVC)
 
assign iadr_ot = (istb_t & !iack_i) ? iadr_t : pc;
assign iadr_o = iadr_ot;
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    iadr_t <= #1 23'h0;
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 24'h0;
  end else if (iack_i) begin
    istb_t <= #1 1'b0;
    imem_wait <= #1 1'b0;
    idat_ir <= #1 idat_i [23:0];
  end else if (ea_rom_sel && imem_wait) begin
    imem_wait <= #1 1'b0;
  end else if (ea_rom_sel && !imem_wait && istb_t) begin
    istb_t <= #1 1'b0;
  end else if (mem_act==`OC8051_MAS_CODE) begin
    iadr_t <= #1 alu;
    istb_t <= #1 1'b1;
    imem_wait <= #1 1'b1;
  end
end
 
/////////////////////////////
//
// ext_addr_sel
//
/////////////////////////////
 
assign dadr_o = dadr_ot;
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    dwe_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
    dstb_o <= #1 1'b0;
    ddat_o <= #1 8'h00;
    dadr_ot <= #1 23'h0;
  end else if (dack_i) begin
    dwe_o <= #1 1'b0;
    dstb_o <= #1 1'b0;
    dmem_wait <= #1 1'b0;
  end else begin
    case (mem_act)
      `OC8051_MAS_DPTR_R: begin  // read from external rom: acc=(dptr)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_DPTR_W: begin  // write to external rom: (dptr)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {7'h0, dptr};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_R:   begin  // read from external rom: acc=(Ri)
        dwe_o <= #1 1'b0;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 8'h00;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
      `OC8051_MAS_RI_W: begin    // write to external rom: (Ri)=acc
        dwe_o <= #1 1'b1;
        dstb_o <= #1 1'b1;
        ddat_o <= #1 acc;
        dadr_ot <= #1 {15'h0, ri};
        dmem_wait <= #1 1'b1;
      end
    endcase
  end
end
 
/////////////////////////////
//
// op_select
//
/////////////////////////////
 
 
assign op1 = ea_rom_sel ? op1_i: op1_xt;
assign op2 = ea_rom_sel ? op2_i: op2_xt;
assign op3 = ea_rom_sel ? op3_i: op3_xt;
 
 
always @(dack_ir or ddat_ir or op1_o or iram_out)
  if (dack_ir)
    op1_out = ddat_ir;
  else
    op1_out = op1_o;
 
assign op3_out = (rd) ? op3_o : op3_buff;
assign op2_out = (rd) ? op2_o : op2_buff;
 
always @(idat_i or iack_i or idat_ir or rd)
begin
  if (iack_i) begin
    op1_xt = idat_i[7:0];
    op2_xt = idat_i[15:8];
    op3_xt = idat_i[23:16];
  end else if (!rd) begin
    op1_xt = idat_ir[7:0];
    op2_xt = idat_ir[15:8];
    op3_xt = idat_ir[23:16];
  end else begin
    op1_xt = 8'h00;
    op2_xt = 8'h00;
    op3_xt = 8'h00;
  end
end
 
 
//
// in case of interrupts
always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)
begin
  if (int_ack_t && (iack_i || ea_rom_sel)) begin
    op1_o = `OC8051_LCALL;
    op2_o = 8'h00;
    op3_o = int_vec_buff;
  end else begin
    op1_o = op1;
    op2_o = op2;
    op3_o = op3;
  end
end
 
//
//in case of reti
always @(posedge clk or posedge rst)
  if (rst) reti <= #1 1'b0;
  else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
  else reti <= #1 1'b0;
 
//
// remember inputs
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    op2_buff <= #1 8'h0;
    op3_buff <= #1 8'h0;
  end else if (rd) begin
    op2_buff <= #1 op2_o;
    op3_buff <= #1 op3_o;
  end
end
 
//
// remember interrupt
// we don't want to interrupt instruction in the middle of execution
always @(posedge clk or posedge rst)
 if (rst) begin
   int_ack_t <= #1 1'b0;
   int_vec_buff <= #1 8'h00;
 end else if (intr) begin
   int_ack_t <= #1 1'b1;
   int_vec_buff <= #1 int_v;
 end else if (rd && (ea_rom_sel || iack_i)) int_ack_t <= #1 1'b0;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack_buff <= #1 1'b0;
  else int_ack_buff <= #1 int_ack_t;
 
always @(posedge clk or posedge rst)
  if (rst) int_ack <= #1 1'b0;
  else begin
    if ((int_ack_buff) & !(int_ack_t))
      int_ack <= #1 1'b1;
    else int_ack <= #1 1'b0;
  end
 
 
/////////////////////////////
//
//  pc
//
/////////////////////////////
 
always @(pc_buf or op1_out or pc_wait or int_buff or int_buff1 or ea_rom_sel or iack_i)
begin
    if (int_buff || int_buff1) begin
//
//in case of interrupt hold valut, to be written to stack
      pc= pc_buf;
//    end else if (pis_l) begin
//      pc = {pc_buf[22:8], alu[7:0]};
    end else if (pc_wait) begin
        casex (op1_out)
          `OC8051_ACALL :  pc= pc_buf + 16'h2;
          `OC8051_AJMP :   pc= pc_buf + 16'h2;
 
        //op_code [7:3]
          `OC8051_CJNE_R : pc= pc_buf + 16'h3;
          `OC8051_DJNZ_R : pc= pc_buf + 16'h2;
          `OC8051_MOV_DR : pc= pc_buf + 16'h2;
          `OC8051_MOV_CR : pc= pc_buf + 16'h2;
          `OC8051_MOV_RD : pc= pc_buf + 16'h2;
 
        //op_code [7:1]
          `OC8051_CJNE_I : pc= pc_buf + 16'h3;
          `OC8051_MOV_ID : pc= pc_buf + 16'h2;
          `OC8051_MOV_DI : pc= pc_buf + 16'h2;
          `OC8051_MOV_CI : pc= pc_buf + 16'h2;
 
        //op_code [7:0]
          `OC8051_ADD_D :  pc= pc_buf + 16'h2;
          `OC8051_ADD_C :  pc= pc_buf + 16'h2;
          `OC8051_ADDC_D : pc= pc_buf + 16'h2;
          `OC8051_ADDC_C : pc= pc_buf + 16'h2;
          `OC8051_ANL_D :  pc= pc_buf + 16'h2;
          `OC8051_ANL_C :  pc= pc_buf + 16'h2;
          `OC8051_ANL_DD : pc= pc_buf + 16'h2;
          `OC8051_ANL_DC : pc= pc_buf + 16'h3;
          `OC8051_ANL_B :  pc= pc_buf + 16'h2;
          `OC8051_ANL_NB : pc= pc_buf + 16'h2;
          `OC8051_CJNE_D : pc= pc_buf + 16'h3;
          `OC8051_CJNE_C : pc= pc_buf + 16'h3;
          `OC8051_CLR_B :  pc= pc_buf + 16'h2;
          `OC8051_CPL_B :  pc= pc_buf + 16'h2;
          `OC8051_DEC_D :  pc= pc_buf + 16'h2;
          `OC8051_DJNZ_D : pc= pc_buf + 16'h3;
          `OC8051_INC_D :  pc= pc_buf + 16'h2;
          `OC8051_JB :     pc= pc_buf + 16'h3;
          `OC8051_JBC :    pc= pc_buf + 16'h3;
          `OC8051_JC :     pc= pc_buf + 16'h2;
          `OC8051_JNB :    pc= pc_buf + 16'h3;
          `OC8051_JNC :    pc= pc_buf + 16'h2;
          `OC8051_JNZ :    pc= pc_buf + 16'h2;
          `OC8051_JZ :     pc= pc_buf + 16'h2;
          `OC8051_LCALL :  pc= pc_buf + 16'h3;
          `OC8051_LJMP :   pc= pc_buf + 16'h3;
          `OC8051_MOV_D :  pc= pc_buf + 16'h2;
          `OC8051_MOV_C :  pc= pc_buf + 16'h2;
          `OC8051_MOV_DA : pc= pc_buf + 16'h2;
          `OC8051_MOV_DD : pc= pc_buf + 16'h3;
          `OC8051_MOV_CD : pc= pc_buf + 16'h3;
          `OC8051_MOV_BC : pc= pc_buf + 16'h2;
          `OC8051_MOV_CB : pc= pc_buf + 16'h2;
          `OC8051_MOV_DP : pc= pc_buf + 16'h3;
          `OC8051_ORL_D :  pc= pc_buf + 16'h2;
          `OC8051_ORL_C :  pc= pc_buf + 16'h2;
          `OC8051_ORL_AD : pc= pc_buf + 16'h2;
          `OC8051_ORL_CD : pc= pc_buf + 16'h3;
          `OC8051_ORL_B :  pc= pc_buf + 16'h2;
          `OC8051_ORL_NB : pc= pc_buf + 16'h2;
          `OC8051_POP :    pc= pc_buf + 16'h2;
          `OC8051_PUSH :   pc= pc_buf + 16'h2;
          `OC8051_SETB_B : pc= pc_buf + 16'h2;
          `OC8051_SJMP :   pc= pc_buf + 16'h2;
          `OC8051_SUBB_D : pc= pc_buf + 16'h2;
          `OC8051_SUBB_C : pc= pc_buf + 16'h2;
          `OC8051_XCH_D :  pc= pc_buf + 16'h2;
          `OC8051_XRL_D :  pc= pc_buf + 16'h2;
          `OC8051_XRL_C :  pc= pc_buf + 16'h2;
          `OC8051_XRL_AD : pc= pc_buf + 16'h2;
          `OC8051_XRL_CD : pc= pc_buf + 16'h3;
          default:         pc= pc_buf + 16'h1;
        endcase
//
//in case of instructions that use more than one clock hold current pc
    end else begin
      pc= pc_buf;
   end
end
 
 
//
//interrupt buffer
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff1 <= #1 1'b0;
  end else begin
    int_buff1 <= #1 int_buff;
  end
 
always @(posedge clk or posedge rst)
  if (rst) begin
    int_buff <= #1 1'b0;
  end else if (intr) begin
    int_buff <= #1 1'b1;
  end else if (pc_wait)
    int_buff <= #1 1'b0;
 
wire [7:0]  pcs_source;
reg  [15:0] pcs_result;
reg         pcs_cy;
 
assign pcs_source = pc_wr_sel[0] ? op3_out : op2_out;
 
always @(pcs_source or pc or pcs_cy)
begin
  if (pcs_source[7]) begin
    {pcs_cy, pcs_result[7:0]} = {1'b0, pc[7:0]} + {1'b0, pcs_source};
    pcs_result[15:8] = pc[15:8] - {7'h0, !pcs_cy};
  end else pcs_result = pc + {8'h00, pcs_source};
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    pc_buf <= #1 `OC8051_RST_PC;
  end else begin
    if (pc_wr) begin
//
//case of writing new value to pc (jupms)
      case (pc_wr_sel)
        `OC8051_PIS_ALU: pc_buf        <= #1 alu;
        `OC8051_PIS_AL:  pc_buf[7:0]   <= #1 alu[7:0];
        `OC8051_PIS_AH:  pc_buf[15:8]  <= #1 alu[7:0];
        `OC8051_PIS_I11: pc_buf[10:0]  <= #1 {op1_out[7:5], op2_out};
        `OC8051_PIS_I16: pc_buf        <= #1 {op2_out, op3_out};
        `OC8051_PIS_SO1: pc_buf        <= #1 pcs_result;
        `OC8051_PIS_SO2: pc_buf        <= #1 pcs_result;
      endcase
    end else
//
//or just remember current
      pc_buf <= #1 pc;
  end
end
 
 
always @(posedge clk or posedge rst)
  if (rst)
    ddat_ir <= #1 8'h00;
  else if (dack_i)
    ddat_ir <= #1 ddat_i;
 
////////////////////////
always @(posedge clk or posedge rst)
  if (rst) begin
    rn_r <= #1 5'd0;
    ri_r <= #1 8'h00;
    imm_r <= #1 8'h00;
    imm2_r <= #1 8'h00;
    rd_addr_r <= #1 1'b0;
    op1_r <= #1 8'h0;
    dack_ir <= #1 1'b0;
    sp_r <= #1 1'b0;
  end else begin
    rn_r <= #1 rn;
    ri_r <= #1 ri;
    imm_r <= #1 imm;
    imm2_r <= #1 imm2;
    rd_addr_r <= #1 rd_addr[7];
    op1_r <= #1 op1_out;
    dack_ir <= #1 dack_i;
    sp_r <= #1 sp;
  end
 
 
endmodule

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 memory interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// comunication betwen cpu and memory ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	140	simont	`// Revision 1.6 2003/05/05 15:46:37 simont`
48			`// add aditional alu destination to solve critical path.`
49			`//`
50	139	simont	`// Revision 1.5 2003/04/25 17:15:51 simont`
51			`// change branch instruction execution (reduse needed clock periods).`
52			`//`
53	132	simont	`// Revision 1.4 2003/04/16 10:04:09 simont`
54			`// chance idat_ir to 24 bit wide`
55			`//`
56	128	simont	`// Revision 1.3 2003/04/11 10:05:08 simont`
57			`// Change pc add value from 23'h to 16'h`
58			`//`
59	121	simont	`// Revision 1.2 2003/04/09 16:24:03 simont`
60			`// change wr_sft to 2 bit wire.`
61			`//`
62	118	simont	`// Revision 1.1 2003/01/13 14:13:12 simont`
63			`// initial import`
64	81	simont	`//`
65	118	simont	`//`
66	81	simont
67			`// synopsys translate_off`
68			`include "oc8051_timescale.v"
69			`// synopsys translate_on`
70
71			`include "oc8051_defines.v"
72
73
74			`module oc8051_memory_interface (clk, rst,`
75			`//decoder`
76			`wr_i, wr_bit_i, rd_sel, wr_sel,`
77			`pc_wr_sel, pc_wr, pc, rd,`
78			`mem_wait, mem_act, istb,`
79			`//internal ram`
80			`wr_o, wr_bit_o, rd_addr, wr_addr, rd_ind, wr_ind, wr_dat,`
81
82			`bit_in, in_ram, sfr, sfr_bit, bit_out, iram_out,`
83
84			`//program rom`
85			`iadr_o, ea, ea_int,`
86			`op1_out, op2_out, op3_out,`
87			`//internal`
88			`op1_i, op2_i, op3_i,`
89			`//external`
90			`iack_i, istb_o, idat_i,`
91
92			`//external data ram`
93			`dadr_o, dwe_o, dstb_o, dack_i, ddat_i, ddat_o,`
94			`//interrupt interface`
95			`intr, int_v, int_ack,`
96
97			`//alu`
98	139	simont	`des_acc, des1, des2,`
99	81	simont
100			`//sfr's`
101	139	simont	`dptr, ri, sp, sp_w, rn, acc, reti);`
102	81	simont
103			`input bit_in, sfr_bit, dack_i;`
104			`input [2:0] mem_act;`
105			`input [7:0] in_ram, sfr, acc, sp_w;`
106			`input [31:0] idat_i;`
107
108			`output bit_out, mem_wait, reti;`
109			`output [7:0] iram_out, wr_dat;`
110
111			`reg bit_out, reti;`
112			`reg [7:0] iram_out, sp_r;`
113	139	simont	`reg rd_addr_r;`
114	81	simont	`input clk, rst, wr_i, wr_bit_i;`
115			`output wr_o, wr_bit_o;`
116
117			`//????`
118			`reg dack_ir;`
119			`reg [7:0] ddat_ir;`
120			`reg [23:0] idat_ir;`
121
122			`/////////////////////////////`
123			`//`
124			`// rom_addr_sel`
125			`//`
126			`/////////////////////////////`
127			`input iack_i;`
128	139	simont	`input [7:0] des_acc, des1, des2;`
129	81	simont	`output [15:0] iadr_o;`
130
131			`wire ea_rom_sel;`
132
133			`/////////////////////////////`
134			`//`
135			`// ext_addr_sel`
136			`//`
137			`/////////////////////////////`
138	139	simont	`input [7:0] ri, ddat_i;`
139	81	simont	`input [15:0] dptr;`
140
141			`output dstb_o, dwe_o;`
142			`output [7:0] ddat_o;`
143			`output [15:0] dadr_o;`
144
145			`/////////////////////////////`
146			`//`
147			`// ram_adr_sel`
148			`//`
149			`/////////////////////////////`
150
151			`input [2:0] rd_sel, wr_sel;`
152			`input [4:0] rn;`
153			`input [7:0] sp;`
154
155			`output rd_ind, wr_ind;`
156			`output [7:0] wr_addr, rd_addr;`
157			`reg rd_ind, wr_ind;`
158			`reg [7:0] wr_addr, rd_addr;`
159
160			`reg [4:0] rn_r;`
161			`reg [7:0] ri_r, imm_r, imm2_r, op1_r;`
162			`wire [7:0] imm, imm2;`
163
164			`/////////////////////////////`
165			`//`
166			`// op_select`
167			`//`
168			`/////////////////////////////`
169
170			`input intr, rd, ea, ea_int, istb;`
171			`input [7:0] op1_i, op2_i, op3_i, int_v;`
172			`output int_ack, istb_o;`
173			`output [7:0] op1_out, op3_out, op2_out;`
174
175			`reg int_ack_t, int_ack, int_ack_buff;`
176			`reg [7:0] int_vec_buff;`
177			`reg [7:0] op1_out, op2_buff, op3_buff;`
178			`reg [7:0] op1_o, op2_o, op3_o;`
179			`reg [7:0] op1_xt, op2_xt, op3_xt;`
180
181			`wire [7:0] op1, op2, op3, op2_direct;`
182			`//wire op_sel;`
183
184			`/////////////////////////////`
185			`//`
186			`// pc`
187			`//`
188			`/////////////////////////////`
189			`input [2:0] pc_wr_sel;`
190
191			`input pc_wr;`
192			`output [15:0] pc;`
193
194
195			`reg [15:0] pc;`
196
197			`//`
198			`//pc program counter register, save current value`
199			`reg [15:0] pc_buf;`
200			`wire [15:0] alu;`
201
202			`//`
203			`// wr_lo write low: used in reti instruction, write only low byte of pc`
204			`// ini_buff interrupt buffer: used to prevent interrupting in the middle of executin instructions`
205			`reg int_buff, int_buff1;`
206
207
208			`//`
209			`//`
210			`////////////////////////////`
211			`reg istb_t, imem_wait, dstb_o, dwe_o;`
212			`//reg [3:0] mem_act_r;`
213			`reg [7:0] ddat_o;`
214			`reg [15:0] iadr_t, dadr_ot;`
215			`reg dmem_wait;`
216			`wire pc_wait;`
217			`wire [1:0] bank;`
218			`//wire pis_l;`
219			`wire [15:0] iadr_ot;`
220			`wire [7:0] isr_call;`
221
222			`assign bank = rn[4:3];`
223			`assign imm = op2_out;`
224			`assign imm2 = op3_out;`
225	139	simont	`assign alu = {des2, des_acc};`
226	81	simont	`assign ea_rom_sel = ea && ea_int;`
227			`assign wr_o = wr_i;`
228			`assign wr_bit_o = wr_bit_i;`
229
230			`assign mem_wait = dmem_wait \|\| imem_wait;`
231			`assign istb_o = (istb \|\| istb_t) && !dstb_o && !ea_rom_sel;`
232
233	140	simont	`assign pc_wait = rd && (ea_rom_sel \|\| (!istb_t && iack_i));`
234	81	simont
235			`assign wr_dat = des1;`
236
237
238			`/////////////////////////////`
239			`//`
240			`// ram_select`
241			`//`
242	140	simont	`/////////////////////////////`
243	139	simont	`always @(rd_addr_r or in_ram or sfr or bit_in or sfr_bit or rd_ind)`
244	81	simont	`begin`
245	139	simont	`if (rd_addr_r && !rd_ind) begin`
246	81	simont	`iram_out = sfr;`
247			`bit_out = sfr_bit;`
248			`end else begin`
249			`iram_out = in_ram;`
250			`bit_out = bit_in;`
251			`end`
252			`end`
253
254			`/////////////////////////////`
255			`//`
256			`// ram_adr_sel`
257			`//`
258			`/////////////////////////////`
259
260	140	simont	`always @(rd_sel or sp or ri or rn or imm or dadr_o[15:0] or bank)`
261	81	simont	`begin`
262	139	simont	`case (rd_sel)`
263			`OC8051_RRS_RN : rd_addr = {3'h0, rn};
264			`OC8051_RRS_I : rd_addr = ri;
265			`OC8051_RRS_D : rd_addr = imm;
266			`OC8051_RRS_SP : rd_addr = sp;
267	81	simont
268	139	simont	`OC8051_RRS_B : rd_addr = `OC8051_SFR_B;
269			`OC8051_RRS_DPTR : rd_addr = `OC8051_SFR_DPTR_LO;
270			`OC8051_RRS_PSW : rd_addr = `OC8051_SFR_PSW;
271			`OC8051_RRS_ACC : rd_addr = `OC8051_SFR_ACC;
272			`default : rd_addr = 2'bxx;`
273			`endcase`
274	81	simont
275			`end`
276
277
278			`//`
279			`//`
280			`always @(wr_sel or sp_w or rn_r or imm_r or ri_r or imm2_r or op1_r or dadr_o[15:0])`
281			`begin`
282	139	simont	`case (wr_sel)`
283			`OC8051_RWS_RN : wr_addr = {3'h0, rn_r};
284			`OC8051_RWS_I : wr_addr = ri_r;
285			`OC8051_RWS_D : wr_addr = imm_r;
286			`OC8051_RWS_SP : wr_addr = sp_w;
287			`OC8051_RWS_D3 : wr_addr = imm2_r;
288			`OC8051_RWS_B : wr_addr = `OC8051_SFR_B;
289			`default : wr_addr = 2'bxx;`
290			`endcase`
291	81	simont	`end`
292
293			`always @(posedge clk or posedge rst)`
294			`if (rst)`
295			`rd_ind <= #1 1'b0;`
296			else if ((rd_sel==`OC8051_RRS_I) \|\| (rd_sel==`OC8051_RRS_SP))
297			`rd_ind <= #1 1'b1;`
298			`else`
299			`rd_ind <= #1 1'b0;`
300
301			`always @(wr_sel)`
302			if ((wr_sel==`OC8051_RWS_I) \|\| (wr_sel==`OC8051_RWS_SP))
303			`wr_ind = 1'b1;`
304			`else`
305			`wr_ind = 1'b0;`
306
307
308			`/////////////////////////////`
309			`//`
310			`// rom_addr_sel`
311			`//`
312			`/////////////////////////////`
313			`//`
314			`// output address is alu destination`
315			`// (instructions MOVC)`
316
317	139	simont	`assign iadr_ot = (istb_t & !iack_i) ? iadr_t : pc;`
318	81	simont	`assign iadr_o = iadr_ot;`
319
320
321			`always @(posedge clk or posedge rst)`
322			`begin`
323			`if (rst) begin`
324			`iadr_t <= #1 23'h0;`
325			`istb_t <= #1 1'b0;`
326			`imem_wait <= #1 1'b0;`
327			`idat_ir <= #1 24'h0;`
328			`end else if (iack_i) begin`
329			`istb_t <= #1 1'b0;`
330			`imem_wait <= #1 1'b0;`
331	128	simont	`idat_ir <= #1 idat_i [23:0];`
332	81	simont	`end else if (ea_rom_sel && imem_wait) begin`
333			`imem_wait <= #1 1'b0;`
334			`end else if (ea_rom_sel && !imem_wait && istb_t) begin`
335			`istb_t <= #1 1'b0;`
336			end else if (mem_act==`OC8051_MAS_CODE) begin
337	139	simont	`iadr_t <= #1 alu;`
338	81	simont	`istb_t <= #1 1'b1;`
339			`imem_wait <= #1 1'b1;`
340			`end`
341			`end`
342
343			`/////////////////////////////`
344			`//`
345			`// ext_addr_sel`
346			`//`
347			`/////////////////////////////`
348
349			`assign dadr_o = dadr_ot;`
350
351			`always @(posedge clk or posedge rst)`
352			`begin`
353			`if (rst) begin`
354			`dwe_o <= #1 1'b0;`
355			`dmem_wait <= #1 1'b0;`
356			`dstb_o <= #1 1'b0;`
357			`ddat_o <= #1 8'h00;`
358			`dadr_ot <= #1 23'h0;`
359			`end else if (dack_i) begin`
360			`dwe_o <= #1 1'b0;`
361			`dstb_o <= #1 1'b0;`
362			`dmem_wait <= #1 1'b0;`
363			`end else begin`
364			`case (mem_act)`
365			`OC8051_MAS_DPTR_R: begin // read from external rom: acc=(dptr)
366			`dwe_o <= #1 1'b0;`
367			`dstb_o <= #1 1'b1;`
368			`ddat_o <= #1 8'h00;`
369			`dadr_ot <= #1 {7'h0, dptr};`
370			`dmem_wait <= #1 1'b1;`
371			`end`
372			`OC8051_MAS_DPTR_W: begin // write to external rom: (dptr)=acc
373			`dwe_o <= #1 1'b1;`
374			`dstb_o <= #1 1'b1;`
375			`ddat_o <= #1 acc;`
376			`dadr_ot <= #1 {7'h0, dptr};`
377			`dmem_wait <= #1 1'b1;`
378			`end`
379			`OC8051_MAS_RI_R: begin // read from external rom: acc=(Ri)
380			`dwe_o <= #1 1'b0;`
381			`dstb_o <= #1 1'b1;`
382			`ddat_o <= #1 8'h00;`
383			`dadr_ot <= #1 {15'h0, ri};`
384			`dmem_wait <= #1 1'b1;`
385			`end`
386			`OC8051_MAS_RI_W: begin // write to external rom: (Ri)=acc
387			`dwe_o <= #1 1'b1;`
388			`dstb_o <= #1 1'b1;`
389			`ddat_o <= #1 acc;`
390			`dadr_ot <= #1 {15'h0, ri};`
391			`dmem_wait <= #1 1'b1;`
392			`end`
393			`endcase`
394			`end`
395			`end`
396
397			`/////////////////////////////`
398			`//`
399			`// op_select`
400			`//`
401			`/////////////////////////////`
402
403
404			`assign op1 = ea_rom_sel ? op1_i: op1_xt;`
405			`assign op2 = ea_rom_sel ? op2_i: op2_xt;`
406			`assign op3 = ea_rom_sel ? op3_i: op3_xt;`
407
408
409			`always @(dack_ir or ddat_ir or op1_o or iram_out)`
410			`if (dack_ir)`
411			`op1_out = ddat_ir;`
412			`else`
413			`op1_out = op1_o;`
414
415			`assign op3_out = (rd) ? op3_o : op3_buff;`
416			`assign op2_out = (rd) ? op2_o : op2_buff;`
417
418			`always @(idat_i or iack_i or idat_ir or rd)`
419			`begin`
420			`if (iack_i) begin`
421	128	simont	`op1_xt = idat_i[7:0];`
422			`op2_xt = idat_i[15:8];`
423			`op3_xt = idat_i[23:16];`
424	81	simont	`end else if (!rd) begin`
425	128	simont	`op1_xt = idat_ir[7:0];`
426	81	simont	`op2_xt = idat_ir[15:8];`
427	128	simont	`op3_xt = idat_ir[23:16];`
428	81	simont	`end else begin`
429			`op1_xt = 8'h00;`
430			`op2_xt = 8'h00;`
431			`op3_xt = 8'h00;`
432			`end`
433			`end`
434
435
436			`//`
437			`// in case of interrupts`
438			`always @(op1 or op2 or op3 or int_ack_t or int_vec_buff or iack_i or ea_rom_sel)`
439			`begin`
440			`if (int_ack_t && (iack_i \|\| ea_rom_sel)) begin`
441			op1_o = `OC8051_LCALL;
442			`op2_o = 8'h00;`
443			`op3_o = int_vec_buff;`
444			`end else begin`
445			`op1_o = op1;`
446			`op2_o = op2;`
447			`op3_o = op3;`
448			`end`
449			`end`
450
451			`//`
452			`//in case of reti`
453			`always @(posedge clk or posedge rst)`
454			`if (rst) reti <= #1 1'b0;`
455			else if ((op1_o==`OC8051_RETI) & rd) reti <= #1 1'b1;
456			`else reti <= #1 1'b0;`
457
458			`//`
459			`// remember inputs`
460			`always @(posedge clk or posedge rst)`
461			`begin`
462			`if (rst) begin`
463			`op2_buff <= #1 8'h0;`
464			`op3_buff <= #1 8'h0;`
465			`end else if (rd) begin`
466			`op2_buff <= #1 op2_o;`
467			`op3_buff <= #1 op3_o;`
468			`end`
469			`end`
470
471			`//`
472			`// remember interrupt`
473			`// we don't want to interrupt instruction in the middle of execution`
474			`always @(posedge clk or posedge rst)`
475			`if (rst) begin`
476			`int_ack_t <= #1 1'b0;`
477			`int_vec_buff <= #1 8'h00;`
478			`end else if (intr) begin`
479			`int_ack_t <= #1 1'b1;`
480			`int_vec_buff <= #1 int_v;`
481			`end else if (rd && (ea_rom_sel \|\| iack_i)) int_ack_t <= #1 1'b0;`
482
483			`always @(posedge clk or posedge rst)`
484			`if (rst) int_ack_buff <= #1 1'b0;`
485			`else int_ack_buff <= #1 int_ack_t;`
486
487			`always @(posedge clk or posedge rst)`
488			`if (rst) int_ack <= #1 1'b0;`
489			`else begin`
490			`if ((int_ack_buff) & !(int_ack_t))`
491			`int_ack <= #1 1'b1;`
492			`else int_ack <= #1 1'b0;`
493			`end`
494
495
496			`/////////////////////////////`
497			`//`
498			`// pc`
499			`//`
500			`/////////////////////////////`

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