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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 116

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 port output                                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   8051 special function registers: port 0:3 - output         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.7  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.6  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk, rst,
                    bit_in, data_in,
                    wr, wr_bit,
                    wr_addr, rmw,
                    p0_out, p1_out, p2_out, p3_out,
                    p0_in, p1_in, p2_in, p3_in,
                    p0_data, p1_data, p2_data, p3_data);
//
// clk          (in)  clock
// rst          (in)  reset
// bit_in       (in)  bit input [oc8051_alu.desCy]
// data_in      (in)  data input (from alu destiantion 1) [oc8051_alu.des1]
// wr           (in)  write [oc8051_decoder.wr -r]
// wr_bit       (in)  write bit addresable [oc8051_decoder.bit_addr -r]
// wr_addr      (in)  write address [oc8051_ram_wr_sel.out]
// rd_addr      (in)  read address [oc8051_ram_rd_sel.out]
// rmw          (in)  read modify write feature [oc8051_decoder.rmw]
// data_out     (out) data output [oc8051_ram_sel.ports_in]
// p0_out, p1_out, p2_out, p3_out       (out) port outputs [pin]
// p0_in, p1_in, p2_in, p3_in           (in)  port inputs [pin]
//
 
 
input clk, rst, wr, wr_bit, bit_in, rmw;
input [7:0] wr_addr, data_in, p0_in, p1_in, p2_in, p3_in;
 
output [7:0] p0_out, p1_out, p2_out, p3_out;
output [7:0] p0_data, p1_data, p2_data, p3_data;
 
reg [7:0] p0_out, p1_out, p2_out, p3_out;
 
assign p0_data = rmw ? p0_out : p0_in;
assign p1_data = rmw ? p1_out : p1_in;
assign p2_data = rmw ? p2_out : p2_in;
assign p3_data = rmw ? p3_out : p3_in;
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    p0_out <= #1 `OC8051_RST_P0;
    p1_out <= #1 `OC8051_RST_P1;
    p2_out <= #1 `OC8051_RST_P2;
    p3_out <= #1 `OC8051_RST_P3;
  end else if (wr) begin
    if (!wr_bit) begin
      case (wr_addr)
//
// bytaddresable
        `OC8051_SFR_P0: p0_out <= #1 data_in;
        `OC8051_SFR_P1: p1_out <= #1 data_in;
        `OC8051_SFR_P2: p2_out <= #1 data_in;
        `OC8051_SFR_P3: p3_out <= #1 data_in;
      endcase
    end else begin
      case (wr_addr[7:3])
 
//
// bit addressable
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
      endcase
    end
  end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 port output ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function registers: port 0:3 - output ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	116	simont	`// Revision 1.7 2003/01/13 14:14:41 simont`
48			`// replace some modules`
49			`//`
50	82	simont	`// Revision 1.6 2002/09/30 17:33:59 simont`
51			`// prepared header`
52			`//`
53			`//`
54
55
56			`// synopsys translate_off`
57			`include "oc8051_timescale.v"
58			`// synopsys translate_on`
59
60			`include "oc8051_defines.v"
61
62
63	116	simont	`module oc8051_ports (clk, rst,`
64			`bit_in, data_in,`
65			`wr, wr_bit,`
66			`wr_addr, rmw,`
67			`p0_out, p1_out, p2_out, p3_out,`
68			`p0_in, p1_in, p2_in, p3_in,`
69			`p0_data, p1_data, p2_data, p3_data);`
70	82	simont	`//`
71			`// clk (in) clock`
72			`// rst (in) reset`
73			`// bit_in (in) bit input [oc8051_alu.desCy]`
74			`// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]`
75			`// wr (in) write [oc8051_decoder.wr -r]`
76			`// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]`
77			`// wr_addr (in) write address [oc8051_ram_wr_sel.out]`
78			`// rd_addr (in) read address [oc8051_ram_rd_sel.out]`
79			`// rmw (in) read modify write feature [oc8051_decoder.rmw]`
80			`// data_out (out) data output [oc8051_ram_sel.ports_in]`
81			`// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]`
82			`// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]`
83			`//`
84
85
86			`input clk, rst, wr, wr_bit, bit_in, rmw;`
87	116	simont	`input [7:0] wr_addr, data_in, p0_in, p1_in, p2_in, p3_in;`
88	82	simont
89	116	simont	`output [7:0] p0_out, p1_out, p2_out, p3_out;`
90			`output [7:0] p0_data, p1_data, p2_data, p3_data;`
91	82	simont
92	116	simont	`reg [7:0] p0_out, p1_out, p2_out, p3_out;`
93	82	simont
94	116	simont	`assign p0_data = rmw ? p0_out : p0_in;`
95			`assign p1_data = rmw ? p1_out : p1_in;`
96			`assign p2_data = rmw ? p2_out : p2_in;`
97			`assign p3_data = rmw ? p3_out : p3_in;`
98
99	82	simont	`//`
100			`// case of writing to port`
101			`always @(posedge clk or posedge rst)`
102			`begin`
103			`if (rst) begin`
104			p0_out <= #1 `OC8051_RST_P0;
105			p1_out <= #1 `OC8051_RST_P1;
106			p2_out <= #1 `OC8051_RST_P2;
107			p3_out <= #1 `OC8051_RST_P3;
108			`end else if (wr) begin`
109			`if (!wr_bit) begin`
110			`case (wr_addr)`
111			`//`
112			`// bytaddresable`
113			`OC8051_SFR_P0: p0_out <= #1 data_in;
114			`OC8051_SFR_P1: p1_out <= #1 data_in;
115			`OC8051_SFR_P2: p2_out <= #1 data_in;
116			`OC8051_SFR_P3: p3_out <= #1 data_in;
117			`endcase`
118			`end else begin`
119			`case (wr_addr[7:3])`
120
121			`//`
122			`// bit addressable`
123			`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
124			`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
125			`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
126			`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
127			`endcase`
128			`end`
129			`end`
130			`end`
131
132
133			`endmodule`
134

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 116