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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 22

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 port output                                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   8051 special function registers: port 0:3 - output         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// ver: 1
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,
                     p0_in, p1_in, p2_in, p3_in);
//
// clk          (in)  clock
// rst          (in)  reset
// bit_in       (in)  bit input [oc8051_alu.desCy]
// data_in      (in)  data input (from alu destiantion 1) [oc8051_alu.des1]
// wr           (in)  write [oc8051_decoder.wr -r]
// wr_bit       (in)  write bit addresable [oc8051_decoder.bit_addr -r]
// wr_addr      (in)  write address [oc8051_ram_wr_sel.out]
// rd_addr      (in)  read address [oc8051_ram_rd_sel.out]
// rmw          (in)  read modify write feature [oc8051_decoder.rmw]
// data_out     (out) data output [oc8051_ram_sel.ports_in]
// p0_out, p1_out, p2_out, p3_out       (out) port outputs [pin]
// p0_in, p1_in, p2_in, p3_in           (in)  port inputs [pin]
//
 
 
input clk, rst, wr, wr_bit, bit_in, rmw;
input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;
 
output bit_out;
output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
 
reg bit_out;
reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    p0_out <= #1 `OC8051_RST_P0;
    p1_out <= #1 `OC8051_RST_P1;
    p2_out <= #1 `OC8051_RST_P2;
    p3_out <= #1 `OC8051_RST_P3;
  end else if (wr) begin
    if (!wr_bit) begin
      case (wr_addr)
//
// bytaddresable
        `OC8051_SFR_P0: p0_out <= #1 data_in;
        `OC8051_SFR_P1: p1_out <= #1 data_in;
        `OC8051_SFR_P2: p2_out <= #1 data_in;
        `OC8051_SFR_P3: p3_out <= #1 data_in;
      endcase
    end else begin
      case (wr_addr[7:3])
 
//
// bit addressable
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
        `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
      endcase
    end
  end
end
 
//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)
always @(posedge clk or posedge rst)
begin
  if (rst)
    data_out <= #1 8'h0;
  else if (rmw) begin
    if ((rd_addr==wr_addr) & wr & !wr_bit)
      data_out <= #1 data_in;
    else begin
      case (rd_addr[5:4])
        2'b00: data_out <= #1 p0_out;
        2'b01: data_out <= #1 p1_out;
        2'b10: data_out <= #1 p2_out;
        2'b11: data_out <= #1 p3_out;
      endcase
     end
  end else
    case (rd_addr[5:4])
      2'b00: data_out <= #1 p0_in;
      2'b01: data_out <= #1 p1_in;
      2'b10: data_out <= #1 p2_in;
      2'b11: data_out <= #1 p3_in;
    endcase
end
 
//always  @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)
always @(posedge clk or posedge rst)
begin
  if (rst)
    bit_out <= #1 1'b0;
  else if (rmw) begin
    if ((wr_addr==rd_addr) & wr & wr_bit)
      bit_out <= #1 bit_in;
    else if ((wr_addr[7:3]==rd_addr[7:3]) & wr & !wr_bit)
      bit_out <= #1 data_in[rd_addr[2:0]];
    else begin
      case (rd_addr[7:3])
        `OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
        `OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
        `OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
        default: bit_out <= #1 p3_out[rd_addr[2:0]];
      endcase
    end
  end else begin
    case (rd_addr[7:3])
      `OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
      `OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
      `OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
      default: bit_out <= #1 p3_in[rd_addr[2:0]];
    endcase
  end
end
 
endmodule
 

Line No.	Rev	Author	Line
1	2	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 port output ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function registers: port 0:3 - output ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// ver: 1`
45			`//`
46
47
48			`// synopsys translate_off`
49			`include "oc8051_timescale.v"
50			`// synopsys translate_on`
51
52			`include "oc8051_defines.v"
53
54
55			`module oc8051_ports (clk, rst, bit_in, data_in, wr, wr_bit, wr_addr, rd_addr, rmw, data_out, bit_out, p0_out, p1_out, p2_out, p3_out,`
56			`p0_in, p1_in, p2_in, p3_in);`
57			`//`
58			`// clk (in) clock`
59			`// rst (in) reset`
60			`// bit_in (in) bit input [oc8051_alu.desCy]`
61			`// data_in (in) data input (from alu destiantion 1) [oc8051_alu.des1]`
62			`// wr (in) write [oc8051_decoder.wr -r]`
63			`// wr_bit (in) write bit addresable [oc8051_decoder.bit_addr -r]`
64			`// wr_addr (in) write address [oc8051_ram_wr_sel.out]`
65			`// rd_addr (in) read address [oc8051_ram_rd_sel.out]`
66			`// rmw (in) read modify write feature [oc8051_decoder.rmw]`
67			`// data_out (out) data output [oc8051_ram_sel.ports_in]`
68			`// p0_out, p1_out, p2_out, p3_out (out) port outputs [pin]`
69			`// p0_in, p1_in, p2_in, p3_in (in) port inputs [pin]`
70			`//`
71
72
73			`input clk, rst, wr, wr_bit, bit_in, rmw;`
74			`input [7:0] wr_addr, rd_addr, data_in, p0_in, p1_in, p2_in, p3_in;`
75
76			`output bit_out;`
77			`output [7:0] data_out, p0_out, p1_out, p2_out, p3_out;`
78
79			`reg bit_out;`
80			`reg [7:0] data_out, p0_out, p1_out, p2_out, p3_out;`
81
82			`//`
83			`// case of writing to port`
84			`always @(posedge clk or posedge rst)`
85			`begin`
86			`if (rst) begin`
87			p0_out <= #1 `OC8051_RST_P0;
88			p1_out <= #1 `OC8051_RST_P1;
89			p2_out <= #1 `OC8051_RST_P2;
90			p3_out <= #1 `OC8051_RST_P3;
91	5	markom	`end else if (wr) begin`
92			`if (!wr_bit) begin`
93			`case (wr_addr)`
94	2	simont	`//`
95	5	markom	`// bytaddresable`
96			`OC8051_SFR_P0: p0_out <= #1 data_in;
97			`OC8051_SFR_P1: p1_out <= #1 data_in;
98			`OC8051_SFR_P2: p2_out <= #1 data_in;
99			`OC8051_SFR_P3: p3_out <= #1 data_in;
100			`endcase`
101			`end else begin`
102			`case (wr_addr[7:3])`
103
104	2	simont	`//`
105			`// bit addressable`
106	5	markom	`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
107			`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
108			`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
109			`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
110			`endcase`
111			`end`
112			`end`
113	2	simont	`end`
114
115	15	simont	`//always @(p0_out or p0_in or p1_out or p1_in or p2_out or p2_in or p3_out or p3_in or rmw)`
116			`always @(posedge clk or posedge rst)`
117	2	simont	`begin`
118	15	simont	`if (rst)`
119			`data_out <= #1 8'h0;`
120			`else if (rmw) begin`
121			`if ((rd_addr==wr_addr) & wr & !wr_bit)`
122			`data_out <= #1 data_in;`
123			`else begin`
124			`case (rd_addr[5:4])`
125			`2'b00: data_out <= #1 p0_out;`
126			`2'b01: data_out <= #1 p1_out;`
127			`2'b10: data_out <= #1 p2_out;`
128			`2'b11: data_out <= #1 p3_out;`
129			`endcase`
130			`end`
131	2	simont	`end else`
132			`case (rd_addr[5:4])`
133	15	simont	`2'b00: data_out <= #1 p0_in;`
134			`2'b01: data_out <= #1 p1_in;`
135			`2'b10: data_out <= #1 p2_in;`
136			`2'b11: data_out <= #1 p3_in;`
137	2	simont	`endcase`
138			`end`
139
140	15	simont	`//always @(rmw or rd_addr or p0_out or p1_out or p2_out or p3_out or p0_in or p1_in or p2_in or p3_in)`
141			`always @(posedge clk or posedge rst)`
142	2	simont	`begin`
143	15	simont	`if (rst)`
144			`bit_out <= #1 1'b0;`
145			`else if (rmw) begin`
146			`if ((wr_addr==rd_addr) & wr & wr_bit)`
147			`bit_out <= #1 bit_in;`
148	22	simont	`else if ((wr_addr[7:3]==rd_addr[7:3]) & wr & !wr_bit)`
149			`bit_out <= #1 data_in[rd_addr[2:0]];`
150	15	simont	`else begin`
151			`case (rd_addr[7:3])`
152			`OC8051_SFR_B_P0: bit_out <= #1 p0_out[rd_addr[2:0]];
153			`OC8051_SFR_B_P1: bit_out <= #1 p1_out[rd_addr[2:0]];
154			`OC8051_SFR_B_P2: bit_out <= #1 p2_out[rd_addr[2:0]];
155			`default: bit_out <= #1 p3_out[rd_addr[2:0]];`
156			`endcase`
157			`end`
158	2	simont	`end else begin`
159			`case (rd_addr[7:3])`
160	15	simont	`OC8051_SFR_B_P0: bit_out <= #1 p0_in[rd_addr[2:0]];
161			`OC8051_SFR_B_P1: bit_out <= #1 p1_in[rd_addr[2:0]];
162			`OC8051_SFR_B_P2: bit_out <= #1 p2_in[rd_addr[2:0]];
163			`default: bit_out <= #1 p3_in[rd_addr[2:0]];`
164	2	simont	`endcase`
165			`end`
166			`end`
167
168			`endmodule`
169

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 22