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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_sp.v] - Blame information for rev 186

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Line No. Rev Author Line
1 76 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 stack pointer                                          ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   8051 special function register: stack pointer.             ////
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////                                                              ////
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////  To Do:                                                      ////
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////   nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
47 120 simont
// Revision 1.5  2003/01/13 14:14:41  simont
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// replace some modules
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//
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// Revision 1.4  2002/11/05 17:23:54  simont
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// add module oc8051_sfr, 256 bytes internal ram
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//
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// Revision 1.3  2002/09/30 17:33:59  simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_sp (clk, rst, ram_rd_sel, ram_wr_sel, wr_addr, wr, wr_bit, data_in, sp_out, sp_w);
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input clk, rst, wr, wr_bit;
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input [2:0] ram_rd_sel, ram_wr_sel;
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input [7:0] data_in, wr_addr;
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output [7:0] sp_out, sp_w;
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reg [7:0] sp_out, sp_w;
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reg pop;
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wire write;
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wire [7:0] sp_t;
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reg [7:0] sp;
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assign write = ((wr_addr==`OC8051_SFR_SP) & (wr) & !(wr_bit));
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assign sp_t= write ? data_in : sp;
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always @(posedge clk or posedge rst)
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begin
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  if (rst)
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    sp <= #1 `OC8051_RST_SP;
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  else if (write)
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    sp <= #1 data_in;
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  else
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    sp <= #1 sp_out;
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end
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always @(sp or ram_wr_sel)
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begin
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//
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// push
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  if (ram_wr_sel==`OC8051_RWS_SP) sp_w = sp + 8'h01;
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  else sp_w = sp;
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end
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always @(sp_t or ram_wr_sel or pop or write)
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begin
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//
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// push
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  if (write) sp_out = sp_t;
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  else if (ram_wr_sel==`OC8051_RWS_SP) sp_out = sp_t + 8'h01;
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  else sp_out = sp_t - {7'b0, pop};
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end
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always @(posedge clk or posedge rst)
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begin
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  if (rst)
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    pop <= #1 1'b0;
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  else if (ram_rd_sel==`OC8051_RRS_SP) pop <= #1 1'b1;
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  else pop <= #1 1'b0;
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end
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endmodule

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