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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Blame information for rev 118

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1 72 simont
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  8051 cores top level module                                 ////
4
////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  8051 definitions.                                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 54 simont
// $Log: not supported by cvs2svn $
47 118 simont
// Revision 1.21  2003/04/09 15:49:42  simont
48
// Register oc8051_sfr dato output, add signal wait_data.
49
//
50 117 simont
// Revision 1.20  2003/04/03 19:13:28  simont
51
// Include instruction cache.
52
//
53 107 simont
// Revision 1.19  2003/04/02 15:08:30  simont
54
// raname signals.
55
//
56 102 simont
// Revision 1.18  2003/01/13 14:14:41  simont
57
// replace some modules
58
//
59 82 simont
// Revision 1.17  2002/11/05 17:23:54  simont
60
// add module oc8051_sfr, 256 bytes internal ram
61
//
62 76 simont
// Revision 1.16  2002/10/28 14:55:00  simont
63
// fix bug in interface to external data ram
64
//
65 72 simont
// Revision 1.15  2002/10/23 16:53:39  simont
66
// fix bugs in instruction interface
67
//
68 62 simont
// Revision 1.14  2002/10/17 18:50:00  simont
69
// cahnge interface to instruction rom
70
//
71 54 simont
// Revision 1.13  2002/09/30 17:33:59  simont
72
// prepared header
73 72 simont
//
74
//
75
 
76
// synopsys translate_off
77
`include "oc8051_timescale.v"
78
// synopsys translate_on
79
 
80
 
81 102 simont
module oc8051_top (wb_rst_i, wb_clk_i,
82
//interface to instruction rom
83
                wbi_adr_o, wbi_dat_i, wbi_stb_o, wbi_ack_i, wbi_cyc_o, wbi_err_i,
84
//interface to data ram
85
                wbd_dat_i, wbd_dat_o,
86
                wbd_adr_o, wbd_we_o, wbd_ack_i, wbd_stb_o, wbd_cyc_o, wbd_err_i,
87
// interrupt interface
88
                int0_i, int1_i,
89
// external access (active low)
90
                ea_in,
91
// port interface
92
                p0_i, p1_i, p2_i, p3_i,
93
                p0_o, p1_o, p2_o, p3_o,
94
// serial interface
95
                rxd_i, txd_o,
96
// counter interface
97
                t0_i, t1_i, t2_i, t2ex_i);
98 72 simont
 
99
 
100
 
101 102 simont
input         wb_rst_i,         // reset input
102
              wb_clk_i,         // clock input
103
              int0_i,           // interrupt 0
104
              int1_i,           // interrupt 1
105
              ea_in,            // external access
106
              rxd_i,            // receive
107
              t0_i,             // counter 0 input
108
              t1_i,             // counter 1 input
109
              wbd_ack_i,        // data acknowalge
110
              wbi_ack_i,        // instruction acknowlage
111
              wbd_err_i,        // data error
112
              wbi_err_i,        // instruction error
113
              t2_i,             // counter 2 input
114
              t2ex_i;           // ???
115 72 simont
 
116 102 simont
input [7:0]   wbd_dat_i, // ram data input
117
              p0_i,             // port 0 input
118
              p1_i,             // port 1 input
119
              p2_i,             // port 2 input
120
              p3_i;             // port 3 input
121
input [31:0]  wbi_dat_i; // rom data input
122 72 simont
 
123 102 simont
output        wbd_we_o,         // data write enable
124
              txd_o,            // transnmit
125
              wbd_stb_o,        // data strobe
126
              wbd_cyc_o,        // data cycle
127
              wbi_stb_o,        // instruction strobe
128
              wbi_cyc_o;        // instruction cycle
129 82 simont
 
130 102 simont
output [7:0]  wbd_dat_o, // data output
131
              p0_o,             // port 0 output
132
              p1_o,             // port 1 output
133
              p2_o,             // port 2 output
134
              p3_o;             // port 3 output
135
 
136
output [15:0] wbd_adr_o, // data address
137
              wbi_adr_o;        // instruction address
138
 
139
 
140 82 simont
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, rn_mem, data_out;
141 54 simont
wire [7:0] op1, op2, op3;
142 76 simont
wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
143 82 simont
wire [7:0] sp, sp_w;
144 72 simont
 
145
wire [15:0] pc;
146
 
147 102 simont
assign wbd_cyc_o = wbd_stb_o;
148 107 simont
//assign wbi_cyc_o = wbi_stb_o;
149 72 simont
 
150
//
151
// ram_rd_sel    ram read (internal)
152
// ram_wr_sel    ram write (internal)
153
// src_sel1, src_sel2    from decoder to register
154 82 simont
wire src_sel3;
155 118 simont
wire [1:0] wr_sfr;
156
wire [2:0] ram_rd_sel, ram_wr_sel;
157 82 simont
wire [2:0] src_sel2, src_sel1;
158 72 simont
 
159
//
160
// wr_addr       ram write addres
161
// ram_out       data from ram
162
// rd_addr       data ram read addres
163
// rd_addr_r     data ram read addres registerd
164 82 simont
wire [7:0] ram_data, ram_out, sfr_out, wr_dat;
165
wire [7:0] wr_addr, rd_addr;
166 76 simont
wire sfr_bit;
167 72 simont
 
168
 
169
//
170
// cy_sel       carry select; from decoder to cy_selct1
171
// rom_addr_sel rom addres select; alu or pc
172
// ext_adddr_sel        external addres select; data pointer or Ri
173
// write_p      output from decoder; write to external ram, go to register;
174 82 simont
wire [1:0] cy_sel, bank_sel;
175
wire rom_addr_sel, rmw, ea_int;
176 72 simont
 
177
//
178
// int_uart     interrupt from uart
179
// tf0          interrupt from t/c 0
180
// tf1          interrupt from t/c 1
181
// tr0          timer 0 run
182
// tr1          timer 1 run
183 76 simont
wire reti, intr, int_ack, istb;
184 72 simont
wire [7:0] int_src;
185
 
186
//
187
//alu_op        alu operation (from decoder)
188
//psw_set       write to psw or not; from decoder to psw (through register)
189 82 simont
wire mem_wait;
190
wire [2:0] mem_act;
191
wire [3:0] alu_op;
192
wire [1:0] psw_set;
193 72 simont
 
194
//
195
// immediate1_r         from imediate_sel1 to alu_src1_sel1
196
// immediate2_r         from imediate_sel1 to alu_src2_sel1
197
// src1. src2, src2     alu sources
198
// des2, des2           alu destinations
199
// des1_r               destination 1 registerd (to comp1)
200
// desCy                carry out
201
// desAc
202
// desOv                overflow
203 82 simont
// wr                   write to data ram
204
wire [7:0] src1, src2, des1, des2, des1_r;
205
wire [7:0] src3;
206
wire desCy, desAc, desOv, alu_cy, wr, wr_o;
207 72 simont
 
208
 
209
//
210
// rd           read program rom
211
// pc_wr_sel    program counter write select (from decoder to pc)
212
wire rd, pc_wr;
213 82 simont
wire [2:0] pc_wr_sel;
214 72 simont
 
215
//
216
// op1_n                from op_select to decoder
217
// op2_n,         output of op_select, to immediate_sel1, pc1, comp1
218
// op3_n,         output of op_select, to immediate_sel1, ram_wr_sel1
219
// op2_dr,      output of op_select, to ram_rd_sel1, ram_wr_sel1
220 82 simont
wire [7:0] op1_n, op2_n, op3_n;
221 72 simont
 
222
//
223
// comp_sel     select source1 and source2 to compare
224
// eq           result (from comp1 to decoder)
225
wire [1:0] comp_sel;
226 82 simont
wire eq, srcAc, cy, rd_ind, wr_ind;
227
wire [2:0] op1_cur;
228 72 simont
 
229
 
230
//
231
// bit_addr     bit addresable instruction
232
// bit_data     bit data from ram to ram_select
233
// bit_out      bit data from ram_select to alu and cy_select
234 82 simont
wire bit_addr, bit_data, bit_out, bit_addr_o;
235 72 simont
 
236
//
237 107 simont
// cpu to cache/wb_interface
238
wire        iack_i,
239
            istb_o,
240
            icyc_o;
241
wire [31:0] idat_i;
242
wire [15:0] iadr_o;
243 117 simont
wire wait_data;
244 72 simont
 
245
 
246
//
247
// decoder
248 102 simont
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i), .rst(wb_rst_i), .op_in(op1_n), .op1_c(op1_cur),
249 117 simont
     .ram_rd_sel_o(ram_rd_sel), .ram_wr_sel_o(ram_wr_sel), .bit_addr(bit_addr),
250 82 simont
     .src_sel1(src_sel1), .src_sel2(src_sel2),
251 117 simont
     .src_sel3(src_sel3), .alu_op_o(alu_op), .psw_set(psw_set),
252
     .cy_sel(cy_sel), .wr_o(wr), .pc_wr(pc_wr),
253 76 simont
     .pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
254 117 simont
     .wr_sfr_o(wr_sfr), .rd(rd), .rmw(rmw),
255
     .istb(istb), .mem_act(mem_act), .mem_wait(mem_wait),
256
     .wait_data(wait_data));
257 72 simont
 
258
 
259
//
260
//alu
261 102 simont
oc8051_alu oc8051_alu1(.rst(wb_rst_i), .clk(wb_clk_i), .op_code(alu_op), .rd(rd),
262 82 simont
     .src1(src1), .src2(src2), .src3(src3), .srcCy(alu_cy), .srcAc(srcAc),
263
     .des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
264
     .desAc(desAc), .desOv(desOv), .bit_in(bit_out));
265 72 simont
 
266
//
267
//data ram
268 102 simont
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .rd_data(ram_data),
269 82 simont
          .wr_addr(wr_addr), .bit_addr(bit_addr_o), .wr_data(wr_dat), .wr(wr_o && (!wr_addr[7] || wr_ind)),
270 72 simont
          .bit_data_in(desCy), .bit_data_out(bit_data));
271
 
272
//
273
 
274 102 simont
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i), .rst(wb_rst_i), .rd(rd),
275 82 simont
     .sel1(src_sel1), .sel2(src_sel2), .sel3(src_sel3),
276
     .acc(acc), .ram(ram_out), .pc(pc), .dptr({dptr_hi, dptr_lo}),
277
     .op1(op1_n), .op2(op2_n), .op3(op3_n),
278
     .src1(src1), .src2(src2), .src3(src3));
279
 
280
 
281 72 simont
//
282
//
283 76 simont
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
284 72 simont
 
285
 
286
//
287
//program rom
288 107 simont
oc8051_rom oc8051_rom1(.rst(wb_rst_i), .clk(wb_clk_i), .ea_int(ea_int), .addr(iadr_o),
289 72 simont
                .data1(op1_i), .data2(op2_i), .data3(op3_i));
290
 
291
//
292
//
293 82 simont
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel), .cy_in(cy), .data_in(bit_out),
294 72 simont
                 .data_out(alu_cy));
295
//
296
//
297 102 simont
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i), .rst(wb_rst_i), .rd_addr(rd_addr), .wr_addr(wr_addr),
298 82 simont
      .data_in(wr_dat), .wr(wr_o), .wr_bit(bit_addr_o), .rn_out(rn_mem),
299
      .ri_out(ri), .sel(op1_cur), .bank(bank_sel));
300 72 simont
 
301
 
302 107 simont
 
303
assign icyc_o = istb_o;
304 72 simont
//
305
//
306 102 simont
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i), .rst(wb_rst_i),
307 107 simont
// internal ram
308 82 simont
   .wr_i(wr), .wr_o(wr_o), .wr_bit_i(bit_addr), .wr_bit_o(bit_addr_o), .wr_dat(wr_dat),
309 107 simont
   .des1(des1), .des2(des2),
310
   .rd_addr(rd_addr), .wr_addr(wr_addr),
311
   .wr_ind(wr_ind),
312
   .bit_in(bit_data), .in_ram(ram_data),
313
   .sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .iram_out(ram_out),
314 72 simont
 
315 107 simont
// external instrauction rom
316
   .iack_i(iack_i),
317
   .iadr_o(iadr_o),
318
   .idat_i(idat_i),
319
   .istb_o(istb_o),
320 82 simont
 
321 107 simont
// internal instruction rom
322
   .op1_i(op1_i), .op2_i(op2_i), .op3_i(op3_i),
323 82 simont
 
324 107 simont
// data memory
325
   .dadr_o(wbd_adr_o), .ddat_o(wbd_dat_o),
326
   .dwe_o(wbd_we_o), .dstb_o(wbd_stb_o),
327
   .ddat_i(wbd_dat_i), .dack_i(wbd_ack_i),
328
 
329
// from decoder
330
   .rd_sel(ram_rd_sel), .wr_sel(ram_wr_sel), .rn({bank_sel, op1_n[2:0]}),
331
   .rd_ind(rd_ind), .rd(rd),
332
   .mem_act(mem_act), .mem_wait(mem_wait),
333
 
334
// external access
335 102 simont
   .ea(ea_in), .ea_int(ea_int),
336 107 simont
 
337
// instructions outputs to cpu
338 82 simont
   .op1_out(op1_n), .op2_out(op2_n), .op3_out(op3_n),
339
 
340 107 simont
// interrupt interface
341
   .intr(intr), .int_v(int_src), .int_ack(int_ack), .istb(istb),
342
   .reti(reti),
343
 
344 82 simont
//pc
345
   .pc_wr_sel(pc_wr_sel), .pc_wr(pc_wr), .pc(pc),
346
 
347 107 simont
// sfr's
348
   .sp_w(sp_w), .dptr({dptr_hi, dptr_lo}),
349
   .ri(ri), .rn_mem(rn_mem),
350
   .acc(acc), .sp(sp)
351
   );
352 82 simont
 
353 107 simont
 
354 72 simont
//
355
//
356
 
357 102 simont
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i), .clk(wb_clk_i), .adr0(rd_addr[7:0]), .adr1(wr_addr[7:0]),
358 82 simont
       .dat0(sfr_out), .dat1(wr_dat), .dat2(des2), .we(wr_o && !wr_ind), .bit_in(desCy),
359 118 simont
       .bit_out(sfr_bit), .wr_bit(bit_addr_o), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
360
       .wr_sfr(wr_sfr),
361 76 simont
// acc
362 82 simont
       .acc(acc),
363 76 simont
// sp
364 82 simont
       .sp(sp), .sp_w(sp_w),
365 76 simont
// psw
366 82 simont
       .bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set),
367 76 simont
       .srcAc(srcAc), .cy(cy),
368
// ports
369 102 simont
       .rmw(rmw), .p0_out(p0_o), .p1_out(p1_o), .p2_out(p2_o), .p3_out(p3_o),
370
       .p0_in(p0_i), .p1_in(p1_i), .p2_in(p2_i), .p3_in(p3_i),
371 76 simont
// uart
372 102 simont
       .rxd(rxd_i), .txd(txd_o),
373 76 simont
// int
374 102 simont
       .int_ack(int_ack), .intr(intr), .int0(int0_i), .int1(int1_i),
375
       .reti(reti), .int_src(int_src),
376 76 simont
// t/c
377 102 simont
       .t0(t0_i), .t1(t1_i), .t2(t2_i), .t2ex(t2ex_i),
378 76 simont
// dptr
379 117 simont
       .dptr_hi(dptr_hi), .dptr_lo(dptr_lo),
380
       .wait_data(wait_data));
381 72 simont
 
382 82 simont
 
383 107 simont
 
384
 
385
`ifdef OC8051_CACHE
386
 
387
 
388
oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
389
// cpu
390
        .adr_i(iadr_o),
391
        .dat_o(idat_i),
392
        .stb_i(istb_o),
393
        .ack_o(iack_i),
394
        .cyc_i(icyc_o),
395
// pins
396
        .dat_i(wbi_dat_i),
397
        .stb_o(wbi_stb_o),
398
        .adr_o(wbi_adr_o),
399
        .ack_i(wbi_ack_i),
400
        .cyc_o(wbi_cyc_o));
401
 
402
defparam oc8051_icache1.ADR_WIDTH = 7;  // cache address wihth
403
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
404
defparam oc8051_icache1.BL_NUM = 31; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
405
defparam oc8051_icache1.CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
406
 
407
//
408
//    no cache
409
//
410
`else
411
 
412
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
413
// cpu
414
        .adr_i(iadr_o),
415
        .dat_o(idat_i),
416
        .stb_i(istb_o),
417
        .ack_o(iack_i),
418
        .cyc_i(icyc_o),
419
// external rom
420
        .dat_i(wbi_dat_i),
421
        .stb_o(wbi_stb_o),
422
        .adr_o(wbi_adr_o),
423
        .ack_i(wbi_ack_i),
424
        .cyc_o(wbi_cyc_o));
425
 
426
 
427
`endif
428
 
429
 
430
 
431 72 simont
endmodule

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