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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores top level module                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////  8051 definitions.                                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.29  2003/05/07 12:36:03  simont
// chsnge comp.des to des1
//
// Revision 1.28  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.26  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.25  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.24  2003/04/11 10:05:59  simont
// deifne OC8051_ROM added
//
// Revision 1.23  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.22  2003/04/09 16:24:04  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.21  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.20  2003/04/03 19:13:28  simont
// Include instruction cache.
//
// Revision 1.19  2003/04/02 15:08:30  simont
// raname signals.
//
// Revision 1.18  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.17  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.16  2002/10/28 14:55:00  simont
// fix bug in interface to external data ram
//
// Revision 1.15  2002/10/23 16:53:39  simont
// fix bugs in instruction interface
//
// Revision 1.14  2002/10/17 18:50:00  simont
// cahnge interface to instruction rom
//
// Revision 1.13  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
                wbi_adr_o,
                wbi_dat_i,
                wbi_stb_o,
                wbi_ack_i,
                wbi_cyc_o,
                wbi_err_i,
 
//interface to data ram
                wbd_dat_i,
                wbd_dat_o,
                wbd_adr_o,
                wbd_we_o,
                wbd_ack_i,
                wbd_stb_o,
                wbd_cyc_o,
                wbd_err_i,
 
// interrupt interface
                int0_i,
                int1_i,
 
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                p0_i,
                p0_o,
        `endif
 
        `ifdef OC8051_PORT1
                p1_i,
                p1_o,
        `endif
 
        `ifdef OC8051_PORT2
                p2_i,
                p2_o,
        `endif
 
        `ifdef OC8051_PORT3
                p3_i,
                p3_o,
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
                rxd_i, txd_o,
        `endif
 
// counter interface
        `ifdef OC8051_TC01
                t0_i, t1_i,
        `endif
 
        `ifdef OC8051_TC2
                t2_i, t2ex_i,
        `endif
 
// external access (active low)
                ea_in
                );
 
 
 
input         wb_rst_i,         // reset input
              wb_clk_i,         // clock input
              int0_i,           // interrupt 0
              int1_i,           // interrupt 1
              ea_in,            // external access
              wbd_ack_i,        // data acknowalge
              wbi_ack_i,        // instruction acknowlage
              wbd_err_i,        // data error
              wbi_err_i;        // instruction error
 
input [7:0]   wbd_dat_i; // ram data input
input [31:0]  wbi_dat_i; // rom data input
 
output        wbd_we_o,         // data write enable
              wbd_stb_o,        // data strobe
              wbd_cyc_o,        // data cycle
              wbi_stb_o,        // instruction strobe
              wbi_cyc_o;        // instruction cycle
 
output [7:0]  wbd_dat_o; // data output
 
output [15:0] wbd_adr_o, // data address
              wbi_adr_o;        // instruction address
 
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0]  p0_i;              // port 0 input
output [7:0]  p0_o;              // port 0 output
`endif
 
`ifdef OC8051_PORT1
input  [7:0]  p1_i;              // port 1 input
output [7:0]  p1_o;              // port 1 output
`endif
 
`ifdef OC8051_PORT2
input  [7:0]  p2_i;              // port 2 input
output [7:0]  p2_o;              // port 2 output
`endif
 
`ifdef OC8051_PORT3
input  [7:0]  p3_i;              // port 3 input
output [7:0]  p3_o;              // port 3 output
`endif
 
`endif
 
 
 
 
 
 
`ifdef OC8051_UART
input         rxd_i;            // receive
output        txd_o;            // transnmit
`endif
 
`ifdef OC8051_TC01
input         t0_i,             // counter 0 input
              t1_i;             // counter 1 input
`endif
 
`ifdef OC8051_TC2
input         t2_i,             // counter 2 input
              t2ex_i;           //
`endif
 
wire [7:0]  dptr_hi,
            dptr_lo,
            ri,
            data_out,
            op1,
            op2,
            op3,
            acc,
            p0_out,
            p1_out,
            p2_out,
            p3_out,
            sp,
            sp_w;
 
wire [31:0] idat_onchip;
 
wire [15:0] pc;
 
assign wbd_cyc_o = wbd_stb_o;
 
wire        src_sel3;
wire [1:0]  wr_sfr,
            src_sel2;
wire [2:0]  ram_rd_sel,  // ram read
            ram_wr_sel, // ram write
            src_sel1;
 
wire [7:0]  ram_data,
            ram_out,    //data from ram
            sfr_out,
            wr_dat,
            wr_addr,    //ram write addres
            rd_addr;    //data ram read addres
wire        sfr_bit;
 
wire [1:0]  cy_sel,      //carry select; from decoder to cy_selct1
            bank_sel;
wire        rom_addr_sel,       //rom addres select; alu or pc
            rmw,
            ea_int;
 
wire        reti,
            intr,
            int_ack,
            istb;
wire [7:0]  int_src;
 
wire        mem_wait;
wire [2:0]  mem_act;
wire [3:0]  alu_op;      //alu operation (from decoder)
wire [1:0]  psw_set;    //write to psw or not; from decoder to psw (through register)
 
wire [7:0]  src1,        //alu sources 1
            src2,       //alu sources 2
            src3,       //alu sources 3
            des_acc,
            des1,       //alu destination 1
            des2;       //alu destinations 2
wire        desCy,      //carry out
            desAc,
            desOv,      //overflow
            alu_cy,
            wr,         //write to data ram
            wr_o;
 
wire        rd,         //read program rom
            pc_wr;
wire [2:0]  pc_wr_sel;   //program counter write select (from decoder to pc)
 
wire [7:0]  op1_n, //from memory_interface to decoder
            op2_n,
            op3_n;
 
wire [1:0]  comp_sel;    //select source1 and source2 to compare
wire        eq,         //result (from comp1 to decoder)
            srcAc,
            cy,
            rd_ind,
            wr_ind,
            comp_wait;
wire [2:0]  op1_cur;
 
wire        bit_addr,   //bit addresable instruction
            bit_data,   //bit data from ram to ram_select
            bit_out,    //bit data from ram_select to alu and cy_select
            bit_addr_o,
            wait_data;
 
//
// cpu to cache/wb_interface
wire        iack_i,
            istb_o,
            icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
 
 
//
// decoder
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
                               .rst(wb_rst_i),
                               .op_in(op1_n),
                               .op1_c(op1_cur),
                               .ram_rd_sel_o(ram_rd_sel),
                               .ram_wr_sel_o(ram_wr_sel),
                               .bit_addr(bit_addr),
 
                               .src_sel1(src_sel1),
                               .src_sel2(src_sel2),
                               .src_sel3(src_sel3),
 
                               .alu_op_o(alu_op),
                               .psw_set(psw_set),
                               .cy_sel(cy_sel),
                               .wr_o(wr),
                               .pc_wr(pc_wr),
                               .pc_sel(pc_wr_sel),
                               .comp_sel(comp_sel),
                               .eq(eq),
                               .wr_sfr_o(wr_sfr),
                               .rd(rd),
                               .rmw(rmw),
                               .istb(istb),
                               .mem_act(mem_act),
                               .mem_wait(mem_wait),
                               .wait_data(wait_data));
 
 
wire [7:0] sub_result;
//
//alu
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .op_code(alu_op),
                       .src1(src1),
                       .src2(src2),
                       .src3(src3),
                       .srcCy(alu_cy),
                       .srcAc(srcAc),
                       .des_acc(des_acc),
                       .sub_result(sub_result),
                       .des1(des1),
                       .des2(des2),
                       .desCy(desCy),
                       .desAc(desAc),
                       .desOv(desOv),
                       .bit_in(bit_out));
 
//
//data ram
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
                               .rst(wb_rst_i),
                               .rd_addr(rd_addr),
                               .rd_data(ram_data),
                               .wr_addr(wr_addr),
                               .bit_addr(bit_addr_o),
                               .wr_data(wr_dat),
                               .wr(wr_o && (!wr_addr[7] || wr_ind)),
                               .bit_data_in(desCy),
                               .bit_data_out(bit_data));
 
//
 
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
                                       .rst(wb_rst_i),
                                       .rd(rd),
 
                                       .sel1(src_sel1),
                                       .sel2(src_sel2),
                                       .sel3(src_sel3),
 
                                       .acc(acc),
                                       .ram(ram_out),
                                       .pc(pc),
                                       .dptr({dptr_hi, dptr_lo}),
                                       .op1(op1_n),
                                       .op2(op2_n),
                                       .op3(op3_n),
 
                                       .src1(src1),
                                       .src2(src2),
                                       .src3(src3));
 
 
//
//
oc8051_comp oc8051_comp1(.sel(comp_sel),
                         .eq(eq),
                         .b_in(bit_out),
                         .cy(cy),
                         .acc(acc),
                         .des(sub_result)
                         );
 
 
//
//program rom
`ifdef OC8051_ROM
  oc8051_rom oc8051_rom1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .ea_int(ea_int),
                       .addr(iadr_o),
                       .data_o(idat_onchip)
                       );
`else
  assign ea_int = 1'b0;
  assign idat_onchip = 32'h0;
`endif
 
//
//
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
                                   .cy_in(cy),
                                   .data_in(bit_out),
                                   .data_out(alu_cy));
//
//
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
                                    .rst(wb_rst_i),
                                    .wr_addr(wr_addr),
                                    .data_in(wr_dat),
                                    .wr(wr_o),
                                    .wr_bit(bit_addr_o),
                                    .ri_out(ri),
                                    .sel(op1_cur[0]),
                                    .bank(bank_sel));
 
 
 
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
                       .rst(wb_rst_i),
// internal ram
                       .wr_i(wr),
                       .wr_o(wr_o),
                       .wr_bit_i(bit_addr),
                       .wr_bit_o(bit_addr_o),
                       .wr_dat(wr_dat),
                       .des_acc(des_acc),
                       .des1(des1),
                       .des2(des2),
                       .rd_addr(rd_addr),
                       .wr_addr(wr_addr),
                       .wr_ind(wr_ind),
                       .bit_in(bit_data),
                       .in_ram(ram_data),
                       .sfr(sfr_out),
                       .sfr_bit(sfr_bit),
                       .bit_out(bit_out),
                       .iram_out(ram_out),
 
// external instrauction rom
                       .iack_i(iack_i),
                       .iadr_o(iadr_o),
                       .idat_i(idat_i),
                       .istb_o(istb_o),
 
// internal instruction rom
                       .idat_onchip(idat_onchip),
 
// data memory
                       .dadr_o(wbd_adr_o),
                       .ddat_o(wbd_dat_o),
                       .dwe_o(wbd_we_o),
                       .dstb_o(wbd_stb_o),
                       .ddat_i(wbd_dat_i),
                       .dack_i(wbd_ack_i),
 
// from decoder
                       .rd_sel(ram_rd_sel),
                       .wr_sel(ram_wr_sel),
                       .rn({bank_sel, op1_cur}),
                       .rd_ind(rd_ind),
                       .rd(rd),
                       .mem_act(mem_act),
                       .mem_wait(mem_wait),
 
// external access
                       .ea(ea_in),
                       .ea_int(ea_int),
 
// instructions outputs to cpu
                       .op1_out(op1_n),
                       .op2_out(op2_n),
                       .op3_out(op3_n),
 
// interrupt interface
                       .intr(intr),
                       .int_v(int_src),
                       .int_ack(int_ack),
                       .istb(istb),
                       .reti(reti),
 
//pc
                       .pc_wr_sel(pc_wr_sel),
                       .pc_wr(pc_wr & comp_wait),
                       .pc(pc),
 
// sfr's
                       .sp_w(sp_w),
                       .dptr({dptr_hi, dptr_lo}),
                       .ri(ri),
                       .acc(acc),
                       .sp(sp)
                       );
 
 
//
//
 
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .adr0(rd_addr[7:0]),
                       .adr1(wr_addr[7:0]),
                       .dat0(sfr_out),
                       .dat1(wr_dat),
                       .dat2(des2),
                       .des_acc(des_acc),
                       .we(wr_o && !wr_ind),
                       .bit_in(desCy),
                       .bit_out(sfr_bit),
                       .wr_bit(bit_addr_o),
                       .ram_rd_sel(ram_rd_sel),
                       .ram_wr_sel(ram_wr_sel),
                       .wr_sfr(wr_sfr),
                       .comp_sel(comp_sel),
                       .comp_wait(comp_wait),
// acc
                       .acc(acc),
// sp
                       .sp(sp),
                       .sp_w(sp_w),
// psw
                       .bank_sel(bank_sel),
                       .desAc(desAc),
                       .desOv(desOv),
                       .psw_set(psw_set),
                       .srcAc(srcAc),
                       .cy(cy),
// ports
                       .rmw(rmw),
 
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                       .p0_out(p0_o),
                       .p0_in(p0_i),
        `endif
 
        `ifdef OC8051_PORT1
                       .p1_out(p1_o),
                       .p1_in(p1_i),
        `endif
 
        `ifdef OC8051_PORT2
                       .p2_out(p2_o),
                       .p2_in(p2_i),
        `endif
 
        `ifdef OC8051_PORT3
                       .p3_out(p3_o),
                       .p3_in(p3_i),
        `endif
  `endif
 
// uart
        `ifdef OC8051_UART
                       .rxd(rxd_i), .txd(txd_o),
        `endif
 
// int
                       .int_ack(int_ack),
                       .intr(intr),
                       .int0(int0_i),
                       .int1(int1_i),
                       .reti(reti),
                       .int_src(int_src),
 
// t/c 0,1
        `ifdef OC8051_TC01
                       .t0(t0_i),
                       .t1(t1_i),
        `endif
 
// t/c 2
        `ifdef OC8051_TC2
                       .t2(t2_i),
                       .t2ex(t2ex_i),
        `endif
 
// dptr
                       .dptr_hi(dptr_hi),
                       .dptr_lo(dptr_lo),
                       .wait_data(wait_data)
                       );
 
 
 
 
`ifdef OC8051_CACHE
 
 
  oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
  // cpu
        .adr_i(iadr_o),
        .dat_o(idat_i),
        .stb_i(istb_o),
        .ack_o(iack_i),
        .cyc_i(icyc_o),
  // pins
        .dat_i(wbi_dat_i),
        .stb_o(wbi_stb_o),
        .adr_o(wbi_adr_o),
        .ack_i(wbi_ack_i),
        .cyc_o(wbi_cyc_o));
 
  defparam oc8051_icache1.ADR_WIDTH = 6;  // cache address wihth
  defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
  defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
  defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
 
//
//    no cache
//
`else
 
  `ifdef OC8051_WB
 
    oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
    // cpu
        .adr_i(iadr_o),
        .dat_o(idat_i),
        .stb_i(istb_o),
        .ack_o(iack_i),
        .cyc_i(icyc_o),
    // external rom
        .dat_i(wbi_dat_i),
        .stb_o(wbi_stb_o),
        .adr_o(wbi_adr_o),
        .ack_i(wbi_ack_i),
        .cyc_o(wbi_cyc_o));
 
  `else
 
    assign wbi_adr_o = iadr_o    ;
    assign idat_i    = wbi_dat_i ;
    assign wbi_stb_o = 1'b1      ;
    assign iack_i    = wbi_ack_i ;
    assign wbi_cyc_o = 1'b1      ;
 
  `endif
 
`endif
 
 
 
endmodule

Line No.	Rev	Author	Line
1	72	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	54	simont	`// $Log: not supported by cvs2svn $`
47	148	simont	`// Revision 1.29 2003/05/07 12:36:03 simont`
48			`// chsnge comp.des to des1`
49			`//`
50	144	simont	`// Revision 1.28 2003/05/06 09:41:35 simont`
51			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
52			`//`
53	141	simont	`// Revision 1.27 2003/05/05 15:46:37 simont`
54			`// add aditional alu destination to solve critical path.`
55			`//`
56	139	simont	`// Revision 1.26 2003/04/29 11:24:31 simont`
57			`// fix bug in case execution of two data dependent instructions.`
58			`//`
59	134	simont	`// Revision 1.25 2003/04/25 17:15:51 simont`
60			`// change branch instruction execution (reduse needed clock periods).`
61			`//`
62	132	simont	`// Revision 1.24 2003/04/11 10:05:59 simont`
63			`// deifne OC8051_ROM added`
64			`//`
65	122	simont	`// Revision 1.23 2003/04/10 12:43:19 simont`
66			`// defines for pherypherals added`
67			`//`
68	120	simont	`// Revision 1.22 2003/04/09 16:24:04 simont`
69			`// change wr_sft to 2 bit wire.`
70			`//`
71	118	simont	`// Revision 1.21 2003/04/09 15:49:42 simont`
72			`// Register oc8051_sfr dato output, add signal wait_data.`
73			`//`
74	117	simont	`// Revision 1.20 2003/04/03 19:13:28 simont`
75			`// Include instruction cache.`
76			`//`
77	107	simont	`// Revision 1.19 2003/04/02 15:08:30 simont`
78			`// raname signals.`
79			`//`
80	102	simont	`// Revision 1.18 2003/01/13 14:14:41 simont`
81			`// replace some modules`
82			`//`
83	82	simont	`// Revision 1.17 2002/11/05 17:23:54 simont`
84			`// add module oc8051_sfr, 256 bytes internal ram`
85			`//`
86	76	simont	`// Revision 1.16 2002/10/28 14:55:00 simont`
87			`// fix bug in interface to external data ram`
88			`//`
89	72	simont	`// Revision 1.15 2002/10/23 16:53:39 simont`
90			`// fix bugs in instruction interface`
91			`//`
92	62	simont	`// Revision 1.14 2002/10/17 18:50:00 simont`
93			`// cahnge interface to instruction rom`
94			`//`
95	54	simont	`// Revision 1.13 2002/09/30 17:33:59 simont`
96			`// prepared header`
97	72	simont	`//`
98			`//`
99
100			`// synopsys translate_off`
101			`include "oc8051_timescale.v"
102			`// synopsys translate_on`
103
104	148	simont	`include "oc8051_defines.v"
105	72	simont
106	102	simont	`module oc8051_top (wb_rst_i, wb_clk_i,`
107			`//interface to instruction rom`
108	120	simont	`wbi_adr_o,`
109			`wbi_dat_i,`
110			`wbi_stb_o,`
111			`wbi_ack_i,`
112			`wbi_cyc_o,`
113			`wbi_err_i,`
114
115	102	simont	`//interface to data ram`
116	120	simont	`wbd_dat_i,`
117			`wbd_dat_o,`
118			`wbd_adr_o,`
119			`wbd_we_o,`
120	132	simont	`wbd_ack_i,`
121	120	simont	`wbd_stb_o,`
122			`wbd_cyc_o,`
123			`wbd_err_i,`
124
125	102	simont	`// interrupt interface`
126	120	simont	`int0_i,`
127			`int1_i,`
128
129
130	102	simont	`// port interface`
131	120	simont	`ifdef OC8051_PORTS
132			`ifdef OC8051_PORT0
133			`p0_i,`
134			`p0_o,`
135			`endif
136
137			`ifdef OC8051_PORT1
138			`p1_i,`
139			`p1_o,`
140			`endif
141
142			`ifdef OC8051_PORT2
143			`p2_i,`
144			`p2_o,`
145			`endif
146
147			`ifdef OC8051_PORT3
148			`p3_i,`
149			`p3_o,`
150			`endif
151			`endif
152
153	102	simont	`// serial interface`
154	120	simont	`ifdef OC8051_UART
155	102	simont	`rxd_i, txd_o,`
156	120	simont	`endif
157
158	102	simont	`// counter interface`
159	120	simont	`ifdef OC8051_TC01
160			`t0_i, t1_i,`
161			`endif
162	72	simont
163	120	simont	`ifdef OC8051_TC2
164	148	simont	`t2_i, t2ex_i,`
165	120	simont	`endif
166	148	simont
167			`// external access (active low)`
168			`ea_in`
169	120	simont	`);`
170	72	simont
171
172	120	simont
173	102	simont	`input wb_rst_i, // reset input`
174			`wb_clk_i, // clock input`
175			`int0_i, // interrupt 0`
176			`int1_i, // interrupt 1`
177			`ea_in, // external access`
178			`wbd_ack_i, // data acknowalge`
179			`wbi_ack_i, // instruction acknowlage`
180			`wbd_err_i, // data error`
181	120	simont	`wbi_err_i; // instruction error`
182	72	simont
183	120	simont	`input [7:0] wbd_dat_i; // ram data input`
184	102	simont	`input [31:0] wbi_dat_i; // rom data input`
185	72	simont
186	102	simont	`output wbd_we_o, // data write enable`
187			`wbd_stb_o, // data strobe`
188			`wbd_cyc_o, // data cycle`
189			`wbi_stb_o, // instruction strobe`
190			`wbi_cyc_o; // instruction cycle`
191	82	simont
192	120	simont	`output [7:0] wbd_dat_o; // data output`
193	102	simont
194			`output [15:0] wbd_adr_o, // data address`
195			`wbi_adr_o; // instruction address`
196
197	120	simont	`ifdef OC8051_PORTS
198	102	simont
199	120	simont	`ifdef OC8051_PORT0
200			`input [7:0] p0_i; // port 0 input`
201			`output [7:0] p0_o; // port 0 output`
202			`endif
203	72	simont
204	120	simont	`ifdef OC8051_PORT1
205			`input [7:0] p1_i; // port 1 input`
206			`output [7:0] p1_o; // port 1 output`
207			`endif
208	72	simont
209	120	simont	`ifdef OC8051_PORT2
210			`input [7:0] p2_i; // port 2 input`
211			`output [7:0] p2_o; // port 2 output`
212			`endif
213	72	simont
214	120	simont	`ifdef OC8051_PORT3
215			`input [7:0] p3_i; // port 3 input`
216			`output [7:0] p3_o; // port 3 output`
217			`endif
218	72	simont
219	120	simont	`endif
220	72	simont
221
222
223
224
225
226	120	simont	`ifdef OC8051_UART
227			`input rxd_i; // receive`
228			`output txd_o; // transnmit`
229			`endif
230	72	simont
231	120	simont	`ifdef OC8051_TC01
232			`input t0_i, // counter 0 input`
233			`t1_i; // counter 1 input`
234			`endif
235	72	simont
236	120	simont	`ifdef OC8051_TC2
237			`input t2_i, // counter 2 input`
238			`t2ex_i; //`
239			`endif
240	72	simont
241	148	simont	`wire [7:0] dptr_hi,`
242	120	simont	`dptr_lo,`
243			`ri,`
244			`data_out,`
245			`op1,`
246			`op2,`
247			`op3,`
248			`acc,`
249			`p0_out,`
250			`p1_out,`
251			`p2_out,`
252			`p3_out,`
253			`sp,`
254			`sp_w;`
255	72	simont
256	148	simont	`wire [31:0] idat_onchip;`
257
258	120	simont	`wire [15:0] pc;`
259	72	simont
260	120	simont	`assign wbd_cyc_o = wbd_stb_o;`
261	72	simont
262	120	simont	`wire src_sel3;`
263	141	simont	`wire [1:0] wr_sfr,`
264			`src_sel2;`
265	120	simont	`wire [2:0] ram_rd_sel, // ram read`
266			`ram_wr_sel, // ram write`
267			`src_sel1;`
268
269			`wire [7:0] ram_data,`
270			`ram_out, //data from ram`
271			`sfr_out,`
272			`wr_dat,`
273			`wr_addr, //ram write addres`
274			`rd_addr; //data ram read addres`
275			`wire sfr_bit;`
276
277			`wire [1:0] cy_sel, //carry select; from decoder to cy_selct1`
278			`bank_sel;`
279			`wire rom_addr_sel, //rom addres select; alu or pc`
280			`rmw,`
281			`ea_int;`
282
283			`wire reti,`
284			`intr,`
285			`int_ack,`
286			`istb;`
287			`wire [7:0] int_src;`
288
289			`wire mem_wait;`
290			`wire [2:0] mem_act;`
291			`wire [3:0] alu_op; //alu operation (from decoder)`
292			`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`
293
294			`wire [7:0] src1, //alu sources 1`
295			`src2, //alu sources 2`
296			`src3, //alu sources 3`
297	139	simont	`des_acc,`
298	120	simont	`des1, //alu destination 1`
299	132	simont	`des2; //alu destinations 2`
300	120	simont	`wire desCy, //carry out`
301			`desAc,`
302			`desOv, //overflow`
303			`alu_cy,`
304			`wr, //write to data ram`
305			`wr_o;`
306
307			`wire rd, //read program rom`
308			`pc_wr;`
309			`wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)`
310
311			`wire [7:0] op1_n, //from memory_interface to decoder`
312			`op2_n,`
313			`op3_n;`
314
315			`wire [1:0] comp_sel; //select source1 and source2 to compare`
316			`wire eq, //result (from comp1 to decoder)`
317			`srcAc,`
318			`cy,`
319			`rd_ind,`
320	132	simont	`wr_ind,`
321			`comp_wait;`
322	120	simont	`wire [2:0] op1_cur;`
323
324			`wire bit_addr, //bit addresable instruction`
325			`bit_data, //bit data from ram to ram_select`
326			`bit_out, //bit data from ram_select to alu and cy_select`
327			`bit_addr_o,`
328			`wait_data;`
329
330	72	simont	`//`
331	107	simont	`// cpu to cache/wb_interface`
332			`wire iack_i,`
333			`istb_o,`
334			`icyc_o;`
335			`wire [31:0] idat_i;`
336			`wire [15:0] iadr_o;`
337	72	simont
338
339			`//`
340			`// decoder`
341	120	simont	`oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),`
342			`.rst(wb_rst_i),`
343			`.op_in(op1_n),`
344			`.op1_c(op1_cur),`
345			`.ram_rd_sel_o(ram_rd_sel),`
346			`.ram_wr_sel_o(ram_wr_sel),`
347			`.bit_addr(bit_addr),`
348	72	simont
349	120	simont	`.src_sel1(src_sel1),`
350			`.src_sel2(src_sel2),`
351			`.src_sel3(src_sel3),`
352	72	simont
353	120	simont	`.alu_op_o(alu_op),`
354			`.psw_set(psw_set),`
355			`.cy_sel(cy_sel),`
356			`.wr_o(wr),`
357			`.pc_wr(pc_wr),`
358			`.pc_sel(pc_wr_sel),`
359			`.comp_sel(comp_sel),`
360			`.eq(eq),`
361			`.wr_sfr_o(wr_sfr),`
362			`.rd(rd),`
363			`.rmw(rmw),`
364			`.istb(istb),`
365			`.mem_act(mem_act),`
366			`.mem_wait(mem_wait),`
367			`.wait_data(wait_data));`
368
369
370	148	simont	`wire [7:0] sub_result;`
371	72	simont	`//`
372			`//alu`
373	148	simont	`oc8051_alu oc8051_alu1(.rst(wb_rst_i),`
374	139	simont	`.clk(wb_clk_i),`
375	120	simont	`.op_code(alu_op),`
376	132	simont	`.src1(src1),`
377	148	simont	`.src2(src2),`
378			`.src3(src3),`
379			`.srcCy(alu_cy),`
380	120	simont	`.srcAc(srcAc),`
381	139	simont	`.des_acc(des_acc),`
382	148	simont	`.sub_result(sub_result),`
383	132	simont	`.des1(des1),`
384			`.des2(des2),`
385	120	simont	`.desCy(desCy),`
386	148	simont	`.desAc(desAc),`
387			`.desOv(desOv),`
388	120	simont	`.bit_in(bit_out));`
389	72	simont
390			`//`
391			`//data ram`
392	134	simont	`oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),`
393	148	simont	`.rst(wb_rst_i),`
394			`.rd_addr(rd_addr),`
395	120	simont	`.rd_data(ram_data),`
396	148	simont	`.wr_addr(wr_addr),`
397			`.bit_addr(bit_addr_o),`
398			`.wr_data(wr_dat),`
399	120	simont	`.wr(wr_o && (!wr_addr[7] \|\| wr_ind)),`
400	148	simont	`.bit_data_in(desCy),`
401	120	simont	`.bit_data_out(bit_data));`
402	72	simont
403			`//`
404
405	148	simont	`oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),`
406			`.rst(wb_rst_i),`
407	120	simont	`.rd(rd),`
408	82	simont
409	120	simont	`.sel1(src_sel1),`
410			`.sel2(src_sel2),`
411			`.sel3(src_sel3),`
412	82	simont
413	120	simont	`.acc(acc),`
414			`.ram(ram_out),`
415			`.pc(pc),`
416			`.dptr({dptr_hi, dptr_lo}),`
417			`.op1(op1_n),`
418			`.op2(op2_n),`
419			`.op3(op3_n),`
420
421			`.src1(src1),`
422			`.src2(src2),`
423			`.src3(src3));`
424
425
426	72	simont	`//`
427			`//`
428	120	simont	`oc8051_comp oc8051_comp1(.sel(comp_sel),`
429	132	simont	`.eq(eq),`
430			`.b_in(bit_out),`
431			`.cy(cy),`
432			`.acc(acc),`
433	148	simont	`.des(sub_result)`
434	132	simont	`);`
435	72	simont
436
437			`//`
438			`//program rom`
439	122	simont	`ifdef OC8051_ROM
440			`oc8051_rom oc8051_rom1(.rst(wb_rst_i),`
441			`.clk(wb_clk_i),`
442			`.ea_int(ea_int),`
443	120	simont	`.addr(iadr_o),`
444	148	simont	`.data_o(idat_onchip)`
445			`);`
446	122	simont	`else
447			`assign ea_int = 1'b0;`
448	148	simont	`assign idat_onchip = 32'h0;`
449	122	simont	`endif
450	72	simont
451			`//`
452			`//`
453	120	simont	`oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),`
454			`.cy_in(cy),`
455			`.data_in(bit_out),`
456			`.data_out(alu_cy));`
457	72	simont	`//`
458			`//`
459	120	simont	`oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),`
460			`.rst(wb_rst_i),`
461			`.wr_addr(wr_addr),`
462	139	simont	`.data_in(wr_dat),`
463	134	simont	`.wr(wr_o),`
464	120	simont	`.wr_bit(bit_addr_o),`
465	139	simont	`.ri_out(ri),`
466			`.sel(op1_cur[0]),`
467	120	simont	`.bank(bank_sel));`
468	72	simont
469
470	107	simont
471			`assign icyc_o = istb_o;`
472	72	simont	`//`
473			`//`
474	120	simont	`oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),`
475			`.rst(wb_rst_i),`
476	107	simont	`// internal ram`
477	120	simont	`.wr_i(wr),`
478			`.wr_o(wr_o),`
479			`.wr_bit_i(bit_addr),`
480			`.wr_bit_o(bit_addr_o),`
481			`.wr_dat(wr_dat),`
482	139	simont	`.des_acc(des_acc),`
483	132	simont	`.des1(des1),`
484	120	simont	`.des2(des2),`
485	139	simont	`.rd_addr(rd_addr),`
486	120	simont	`.wr_addr(wr_addr),`
487			`.wr_ind(wr_ind),`
488	139	simont	`.bit_in(bit_data),`
489	120	simont	`.in_ram(ram_data),`
490	139	simont	`.sfr(sfr_out),`
491			`.sfr_bit(sfr_bit),`
492	134	simont	`.bit_out(bit_out),`
493	120	simont	`.iram_out(ram_out),`
494	72	simont
495	107	simont	`// external instrauction rom`
496	120	simont	`.iack_i(iack_i),`
497			`.iadr_o(iadr_o),`
498			`.idat_i(idat_i),`
499			`.istb_o(istb_o),`
500	82	simont

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