OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Blame information for rev 185

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 72 simont
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  8051 cores top level module                                 ////
4
////                                                              ////
5
////  This file is part of the 8051 cores project                 ////
6
////  http://www.opencores.org/cores/8051/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  8051 definitions.                                           ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////    nothing                                                   ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Simon Teran, simont@opencores.org                     ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 54 simont
// $Log: not supported by cvs2svn $
47 181 simont
// Revision 1.32  2003/06/20 13:36:37  simont
48
// ram modules added.
49
//
50 174 simont
// Revision 1.31  2003/06/17 14:17:22  simont
51
// BIST signals added.
52
//
53 172 simont
// Revision 1.30  2003/06/03 16:51:24  simont
54
// include "8051_defines" added.
55
//
56 148 simont
// Revision 1.29  2003/05/07 12:36:03  simont
57
// chsnge comp.des to des1
58
//
59 144 simont
// Revision 1.28  2003/05/06 09:41:35  simont
60
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
61
//
62 141 simont
// Revision 1.27  2003/05/05 15:46:37  simont
63
// add aditional alu destination to solve critical path.
64
//
65 139 simont
// Revision 1.26  2003/04/29 11:24:31  simont
66
// fix bug in case execution of two data dependent instructions.
67
//
68 134 simont
// Revision 1.25  2003/04/25 17:15:51  simont
69
// change branch instruction execution (reduse needed clock periods).
70
//
71 132 simont
// Revision 1.24  2003/04/11 10:05:59  simont
72
// deifne OC8051_ROM added
73
//
74 122 simont
// Revision 1.23  2003/04/10 12:43:19  simont
75
// defines for pherypherals added
76
//
77 120 simont
// Revision 1.22  2003/04/09 16:24:04  simont
78
// change wr_sft to 2 bit wire.
79
//
80 118 simont
// Revision 1.21  2003/04/09 15:49:42  simont
81
// Register oc8051_sfr dato output, add signal wait_data.
82
//
83 117 simont
// Revision 1.20  2003/04/03 19:13:28  simont
84
// Include instruction cache.
85
//
86 107 simont
// Revision 1.19  2003/04/02 15:08:30  simont
87
// raname signals.
88
//
89 102 simont
// Revision 1.18  2003/01/13 14:14:41  simont
90
// replace some modules
91
//
92 82 simont
// Revision 1.17  2002/11/05 17:23:54  simont
93
// add module oc8051_sfr, 256 bytes internal ram
94
//
95 76 simont
// Revision 1.16  2002/10/28 14:55:00  simont
96
// fix bug in interface to external data ram
97
//
98 72 simont
// Revision 1.15  2002/10/23 16:53:39  simont
99
// fix bugs in instruction interface
100
//
101 62 simont
// Revision 1.14  2002/10/17 18:50:00  simont
102
// cahnge interface to instruction rom
103
//
104 54 simont
// Revision 1.13  2002/09/30 17:33:59  simont
105
// prepared header
106 72 simont
//
107
//
108
 
109
// synopsys translate_off
110
`include "oc8051_timescale.v"
111
// synopsys translate_on
112
 
113 148 simont
`include "oc8051_defines.v"
114 72 simont
 
115 102 simont
module oc8051_top (wb_rst_i, wb_clk_i,
116
//interface to instruction rom
117 120 simont
                wbi_adr_o,
118
                wbi_dat_i,
119
                wbi_stb_o,
120
                wbi_ack_i,
121
                wbi_cyc_o,
122
                wbi_err_i,
123
 
124 102 simont
//interface to data ram
125 120 simont
                wbd_dat_i,
126
                wbd_dat_o,
127
                wbd_adr_o,
128
                wbd_we_o,
129 132 simont
                wbd_ack_i,
130 120 simont
                wbd_stb_o,
131
                wbd_cyc_o,
132
                wbd_err_i,
133
 
134 102 simont
// interrupt interface
135 120 simont
                int0_i,
136
                int1_i,
137
 
138
 
139 102 simont
// port interface
140 120 simont
  `ifdef OC8051_PORTS
141
        `ifdef OC8051_PORT0
142
                p0_i,
143
                p0_o,
144
        `endif
145
 
146
        `ifdef OC8051_PORT1
147
                p1_i,
148
                p1_o,
149
        `endif
150
 
151
        `ifdef OC8051_PORT2
152
                p2_i,
153
                p2_o,
154
        `endif
155
 
156
        `ifdef OC8051_PORT3
157
                p3_i,
158
                p3_o,
159
        `endif
160
  `endif
161
 
162 102 simont
// serial interface
163 120 simont
        `ifdef OC8051_UART
164 102 simont
                rxd_i, txd_o,
165 120 simont
        `endif
166
 
167 102 simont
// counter interface
168 120 simont
        `ifdef OC8051_TC01
169
                t0_i, t1_i,
170
        `endif
171 72 simont
 
172 120 simont
        `ifdef OC8051_TC2
173 148 simont
                t2_i, t2ex_i,
174 120 simont
        `endif
175 148 simont
 
176 172 simont
// BIST
177
`ifdef OC8051_BIST
178
         scanb_rst,
179
         scanb_clk,
180
         scanb_si,
181
         scanb_so,
182
         scanb_en,
183
`endif
184 148 simont
// external access (active low)
185
                ea_in
186 120 simont
                );
187 72 simont
 
188
 
189 120 simont
 
190 102 simont
input         wb_rst_i,         // reset input
191
              wb_clk_i,         // clock input
192
              int0_i,           // interrupt 0
193
              int1_i,           // interrupt 1
194
              ea_in,            // external access
195
              wbd_ack_i,        // data acknowalge
196
              wbi_ack_i,        // instruction acknowlage
197
              wbd_err_i,        // data error
198 120 simont
              wbi_err_i;        // instruction error
199 72 simont
 
200 120 simont
input [7:0]   wbd_dat_i; // ram data input
201 102 simont
input [31:0]  wbi_dat_i; // rom data input
202 72 simont
 
203 102 simont
output        wbd_we_o,         // data write enable
204
              wbd_stb_o,        // data strobe
205
              wbd_cyc_o,        // data cycle
206
              wbi_stb_o,        // instruction strobe
207
              wbi_cyc_o;        // instruction cycle
208 82 simont
 
209 120 simont
output [7:0]  wbd_dat_o; // data output
210 102 simont
 
211
output [15:0] wbd_adr_o, // data address
212
              wbi_adr_o;        // instruction address
213
 
214 120 simont
`ifdef OC8051_PORTS
215 102 simont
 
216 120 simont
`ifdef OC8051_PORT0
217
input  [7:0]  p0_i;              // port 0 input
218
output [7:0]  p0_o;              // port 0 output
219
`endif
220 72 simont
 
221 120 simont
`ifdef OC8051_PORT1
222
input  [7:0]  p1_i;              // port 1 input
223
output [7:0]  p1_o;              // port 1 output
224
`endif
225 72 simont
 
226 120 simont
`ifdef OC8051_PORT2
227
input  [7:0]  p2_i;              // port 2 input
228
output [7:0]  p2_o;              // port 2 output
229
`endif
230 72 simont
 
231 120 simont
`ifdef OC8051_PORT3
232
input  [7:0]  p3_i;              // port 3 input
233
output [7:0]  p3_o;              // port 3 output
234
`endif
235 72 simont
 
236 120 simont
`endif
237 72 simont
 
238
 
239
 
240
 
241
 
242
 
243 120 simont
`ifdef OC8051_UART
244
input         rxd_i;            // receive
245
output        txd_o;            // transnmit
246
`endif
247 72 simont
 
248 120 simont
`ifdef OC8051_TC01
249
input         t0_i,             // counter 0 input
250
              t1_i;             // counter 1 input
251
`endif
252 72 simont
 
253 120 simont
`ifdef OC8051_TC2
254
input         t2_i,             // counter 2 input
255
              t2ex_i;           //
256
`endif
257 72 simont
 
258 172 simont
`ifdef OC8051_BIST
259
input   scanb_rst;
260
input   scanb_clk;
261
input   scanb_si;
262
output  scanb_so;
263
input   scanb_en;
264 174 simont
wire    scanb_soi;
265 172 simont
`endif
266
 
267 148 simont
wire [7:0]  dptr_hi,
268 120 simont
            dptr_lo,
269
            ri,
270
            data_out,
271
            op1,
272
            op2,
273
            op3,
274
            acc,
275
            p0_out,
276
            p1_out,
277
            p2_out,
278
            p3_out,
279
            sp,
280
            sp_w;
281 72 simont
 
282 148 simont
wire [31:0] idat_onchip;
283
 
284 120 simont
wire [15:0] pc;
285 72 simont
 
286 120 simont
assign wbd_cyc_o = wbd_stb_o;
287 72 simont
 
288 120 simont
wire        src_sel3;
289 141 simont
wire [1:0]  wr_sfr,
290
            src_sel2;
291 120 simont
wire [2:0]  ram_rd_sel,  // ram read
292
            ram_wr_sel, // ram write
293
            src_sel1;
294
 
295
wire [7:0]  ram_data,
296
            ram_out,    //data from ram
297
            sfr_out,
298
            wr_dat,
299
            wr_addr,    //ram write addres
300
            rd_addr;    //data ram read addres
301
wire        sfr_bit;
302
 
303
wire [1:0]  cy_sel,      //carry select; from decoder to cy_selct1
304
            bank_sel;
305
wire        rom_addr_sel,       //rom addres select; alu or pc
306
            rmw,
307
            ea_int;
308
 
309
wire        reti,
310
            intr,
311
            int_ack,
312
            istb;
313
wire [7:0]  int_src;
314
 
315
wire        mem_wait;
316
wire [2:0]  mem_act;
317
wire [3:0]  alu_op;      //alu operation (from decoder)
318
wire [1:0]  psw_set;    //write to psw or not; from decoder to psw (through register)
319
 
320
wire [7:0]  src1,        //alu sources 1
321
            src2,       //alu sources 2
322
            src3,       //alu sources 3
323 139 simont
            des_acc,
324 120 simont
            des1,       //alu destination 1
325 132 simont
            des2;       //alu destinations 2
326 120 simont
wire        desCy,      //carry out
327
            desAc,
328
            desOv,      //overflow
329
            alu_cy,
330
            wr,         //write to data ram
331
            wr_o;
332
 
333
wire        rd,         //read program rom
334
            pc_wr;
335
wire [2:0]  pc_wr_sel;   //program counter write select (from decoder to pc)
336
 
337
wire [7:0]  op1_n, //from memory_interface to decoder
338
            op2_n,
339
            op3_n;
340
 
341
wire [1:0]  comp_sel;    //select source1 and source2 to compare
342
wire        eq,         //result (from comp1 to decoder)
343
            srcAc,
344
            cy,
345
            rd_ind,
346 132 simont
            wr_ind,
347
            comp_wait;
348 120 simont
wire [2:0]  op1_cur;
349
 
350
wire        bit_addr,   //bit addresable instruction
351
            bit_data,   //bit data from ram to ram_select
352
            bit_out,    //bit data from ram_select to alu and cy_select
353
            bit_addr_o,
354
            wait_data;
355
 
356 72 simont
//
357 107 simont
// cpu to cache/wb_interface
358
wire        iack_i,
359
            istb_o,
360
            icyc_o;
361
wire [31:0] idat_i;
362
wire [15:0] iadr_o;
363 72 simont
 
364
 
365
//
366
// decoder
367 120 simont
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
368
                               .rst(wb_rst_i),
369
                               .op_in(op1_n),
370
                               .op1_c(op1_cur),
371
                               .ram_rd_sel_o(ram_rd_sel),
372
                               .ram_wr_sel_o(ram_wr_sel),
373
                               .bit_addr(bit_addr),
374 72 simont
 
375 120 simont
                               .src_sel1(src_sel1),
376
                               .src_sel2(src_sel2),
377
                               .src_sel3(src_sel3),
378 72 simont
 
379 120 simont
                               .alu_op_o(alu_op),
380
                               .psw_set(psw_set),
381
                               .cy_sel(cy_sel),
382
                               .wr_o(wr),
383
                               .pc_wr(pc_wr),
384
                               .pc_sel(pc_wr_sel),
385
                               .comp_sel(comp_sel),
386
                               .eq(eq),
387
                               .wr_sfr_o(wr_sfr),
388
                               .rd(rd),
389
                               .rmw(rmw),
390
                               .istb(istb),
391
                               .mem_act(mem_act),
392
                               .mem_wait(mem_wait),
393
                               .wait_data(wait_data));
394
 
395
 
396 148 simont
wire [7:0] sub_result;
397 72 simont
//
398
//alu
399 148 simont
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
400 139 simont
                       .clk(wb_clk_i),
401 120 simont
                       .op_code(alu_op),
402 132 simont
                       .src1(src1),
403 148 simont
                       .src2(src2),
404
                       .src3(src3),
405
                       .srcCy(alu_cy),
406 120 simont
                       .srcAc(srcAc),
407 139 simont
                       .des_acc(des_acc),
408 148 simont
                       .sub_result(sub_result),
409 132 simont
                       .des1(des1),
410
                       .des2(des2),
411 120 simont
                       .desCy(desCy),
412 148 simont
                       .desAc(desAc),
413
                       .desOv(desOv),
414 120 simont
                       .bit_in(bit_out));
415 72 simont
 
416
//
417
//data ram
418 134 simont
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
419 148 simont
                               .rst(wb_rst_i),
420
                               .rd_addr(rd_addr),
421 120 simont
                               .rd_data(ram_data),
422 148 simont
                               .wr_addr(wr_addr),
423
                               .bit_addr(bit_addr_o),
424
                               .wr_data(wr_dat),
425 120 simont
                               .wr(wr_o && (!wr_addr[7] || wr_ind)),
426 148 simont
                               .bit_data_in(desCy),
427 172 simont
                               .bit_data_out(bit_data)
428
`ifdef OC8051_BIST
429
         ,
430
         .scanb_rst(scanb_rst),
431
         .scanb_clk(scanb_clk),
432 174 simont
         .scanb_si(scanb_soi),
433 172 simont
         .scanb_so(scanb_so),
434
         .scanb_en(scanb_en)
435
`endif
436
                               );
437 72 simont
 
438
//
439
 
440 148 simont
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
441
                                       .rst(wb_rst_i),
442 120 simont
                                       .rd(rd),
443 82 simont
 
444 120 simont
                                       .sel1(src_sel1),
445
                                       .sel2(src_sel2),
446
                                       .sel3(src_sel3),
447 82 simont
 
448 120 simont
                                       .acc(acc),
449
                                       .ram(ram_out),
450
                                       .pc(pc),
451
                                       .dptr({dptr_hi, dptr_lo}),
452
                                       .op1(op1_n),
453
                                       .op2(op2_n),
454
                                       .op3(op3_n),
455
 
456
                                       .src1(src1),
457
                                       .src2(src2),
458
                                       .src3(src3));
459
 
460
 
461 72 simont
//
462
//
463 120 simont
oc8051_comp oc8051_comp1(.sel(comp_sel),
464 132 simont
                         .eq(eq),
465
                         .b_in(bit_out),
466
                         .cy(cy),
467
                         .acc(acc),
468 148 simont
                         .des(sub_result)
469 132 simont
                         );
470 72 simont
 
471
 
472
//
473
//program rom
474 122 simont
`ifdef OC8051_ROM
475
  oc8051_rom oc8051_rom1(.rst(wb_rst_i),
476
                       .clk(wb_clk_i),
477
                       .ea_int(ea_int),
478 120 simont
                       .addr(iadr_o),
479 148 simont
                       .data_o(idat_onchip)
480
                       );
481 122 simont
`else
482
  assign ea_int = 1'b0;
483 148 simont
  assign idat_onchip = 32'h0;
484 181 simont
 
485
  `ifdef OC8051_SIMULATION
486
 
487
    initial
488
    begin
489
      $display("\t * ");
490
      $display("\t * Internal rom disabled!!!");
491
      $display("\t * ");
492
    end
493
 
494
  `endif
495
 
496 122 simont
`endif
497 72 simont
 
498
//
499
//
500 120 simont
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
501
                                   .cy_in(cy),
502
                                   .data_in(bit_out),
503
                                   .data_out(alu_cy));
504 72 simont
//
505
//
506 120 simont
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
507
                                    .rst(wb_rst_i),
508
                                    .wr_addr(wr_addr),
509 139 simont
                                    .data_in(wr_dat),
510 134 simont
                                    .wr(wr_o),
511 120 simont
                                    .wr_bit(bit_addr_o),
512 139 simont
                                    .ri_out(ri),
513
                                    .sel(op1_cur[0]),
514 120 simont
                                    .bank(bank_sel));
515 72 simont
 
516
 
517 107 simont
 
518
assign icyc_o = istb_o;
519 72 simont
//
520
//
521 120 simont
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
522
                       .rst(wb_rst_i),
523 107 simont
// internal ram
524 120 simont
                       .wr_i(wr),
525
                       .wr_o(wr_o),
526
                       .wr_bit_i(bit_addr),
527
                       .wr_bit_o(bit_addr_o),
528
                       .wr_dat(wr_dat),
529 139 simont
                       .des_acc(des_acc),
530 132 simont
                       .des1(des1),
531 120 simont
                       .des2(des2),
532 139 simont
                       .rd_addr(rd_addr),
533 120 simont
                       .wr_addr(wr_addr),
534
                       .wr_ind(wr_ind),
535 139 simont
                       .bit_in(bit_data),
536 120 simont
                       .in_ram(ram_data),
537 139 simont
                       .sfr(sfr_out),
538
                       .sfr_bit(sfr_bit),
539 134 simont
                       .bit_out(bit_out),
540 120 simont
                       .iram_out(ram_out),
541 72 simont
 
542 107 simont
// external instrauction rom
543 120 simont
                       .iack_i(iack_i),
544
                       .iadr_o(iadr_o),
545
                       .idat_i(idat_i),
546
                       .istb_o(istb_o),
547 82 simont
 
548 107 simont
// internal instruction rom
549 148 simont
                       .idat_onchip(idat_onchip),
550 82 simont
 
551 107 simont
// data memory
552 139 simont
                       .dadr_o(wbd_adr_o),
553 120 simont
                       .ddat_o(wbd_dat_o),
554 139 simont
                       .dwe_o(wbd_we_o),
555 120 simont
                       .dstb_o(wbd_stb_o),
556 139 simont
                       .ddat_i(wbd_dat_i),
557 120 simont
                       .dack_i(wbd_ack_i),
558 107 simont
 
559
// from decoder
560 139 simont
                       .rd_sel(ram_rd_sel),
561
                       .wr_sel(ram_wr_sel),
562 134 simont
                       .rn({bank_sel, op1_cur}),
563
                       .rd_ind(rd_ind),
564 120 simont
                       .rd(rd),
565 139 simont
                       .mem_act(mem_act),
566 120 simont
                       .mem_wait(mem_wait),
567 107 simont
 
568
// external access
569 139 simont
                       .ea(ea_in),
570 120 simont
                       .ea_int(ea_int),
571 107 simont
 
572
// instructions outputs to cpu
573 139 simont
                       .op1_out(op1_n),
574
                       .op2_out(op2_n),
575 120 simont
                       .op3_out(op3_n),
576 82 simont
 
577 107 simont
// interrupt interface
578 120 simont
                       .intr(intr),
579
                       .int_v(int_src),
580
                       .int_ack(int_ack),
581
                       .istb(istb),
582
                       .reti(reti),
583 107 simont
 
584 82 simont
//pc
585 120 simont
                       .pc_wr_sel(pc_wr_sel),
586 132 simont
                       .pc_wr(pc_wr & comp_wait),
587 120 simont
                       .pc(pc),
588 82 simont
 
589 107 simont
// sfr's
590 120 simont
                       .sp_w(sp_w),
591
                       .dptr({dptr_hi, dptr_lo}),
592
                       .ri(ri),
593 139 simont
                       .acc(acc),
594 120 simont
                       .sp(sp)
595
                       );
596 82 simont
 
597 107 simont
 
598 72 simont
//
599
//
600
 
601 120 simont
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
602
                       .clk(wb_clk_i),
603
                       .adr0(rd_addr[7:0]),
604
                       .adr1(wr_addr[7:0]),
605 139 simont
                       .dat0(sfr_out),
606
                       .dat1(wr_dat),
607
                       .dat2(des2),
608
                       .des_acc(des_acc),
609
                       .we(wr_o && !wr_ind),
610 120 simont
                       .bit_in(desCy),
611
                       .bit_out(sfr_bit),
612 134 simont
                       .wr_bit(bit_addr_o),
613
                       .ram_rd_sel(ram_rd_sel),
614 120 simont
                       .ram_wr_sel(ram_wr_sel),
615
                       .wr_sfr(wr_sfr),
616 132 simont
                       .comp_sel(comp_sel),
617
                       .comp_wait(comp_wait),
618 76 simont
// acc
619 120 simont
                       .acc(acc),
620 76 simont
// sp
621 120 simont
                       .sp(sp),
622
                       .sp_w(sp_w),
623 76 simont
// psw
624 120 simont
                       .bank_sel(bank_sel),
625
                       .desAc(desAc),
626
                       .desOv(desOv),
627
                       .psw_set(psw_set),
628
                       .srcAc(srcAc),
629
                       .cy(cy),
630 76 simont
// ports
631 172 simont
                       .rmw(rmw),
632 120 simont
 
633
  `ifdef OC8051_PORTS
634
        `ifdef OC8051_PORT0
635
                       .p0_out(p0_o),
636
                       .p0_in(p0_i),
637
        `endif
638
 
639
        `ifdef OC8051_PORT1
640
                       .p1_out(p1_o),
641
                       .p1_in(p1_i),
642
        `endif
643
 
644
        `ifdef OC8051_PORT2
645
                       .p2_out(p2_o),
646
                       .p2_in(p2_i),
647
        `endif
648
 
649
        `ifdef OC8051_PORT3
650
                       .p3_out(p3_o),
651
                       .p3_in(p3_i),
652
        `endif
653
  `endif
654
 
655 76 simont
// uart
656 120 simont
        `ifdef OC8051_UART
657
                       .rxd(rxd_i), .txd(txd_o),
658
        `endif
659
 
660 76 simont
// int
661 172 simont
                       .int_ack(int_ack),
662
                       .intr(intr),
663
                       .int0(int0_i),
664 120 simont
                       .int1(int1_i),
665 148 simont
                       .reti(reti),
666 120 simont
                       .int_src(int_src),
667
 
668
// t/c 0,1
669
        `ifdef OC8051_TC01
670
                       .t0(t0_i),
671
                       .t1(t1_i),
672
        `endif
673
 
674
// t/c 2
675
        `ifdef OC8051_TC2
676 172 simont
                       .t2(t2_i),
677 120 simont
                       .t2ex(t2ex_i),
678
        `endif
679
 
680 76 simont
// dptr
681 172 simont
                       .dptr_hi(dptr_hi),
682 120 simont
                       .dptr_lo(dptr_lo),
683
                       .wait_data(wait_data)
684
                       );
685 72 simont
 
686 82 simont
 
687 107 simont
 
688
 
689
`ifdef OC8051_CACHE
690
 
691
 
692 148 simont
  oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
693
  // cpu
694 107 simont
        .adr_i(iadr_o),
695
        .dat_o(idat_i),
696
        .stb_i(istb_o),
697
        .ack_o(iack_i),
698
        .cyc_i(icyc_o),
699 148 simont
  // pins
700 107 simont
        .dat_i(wbi_dat_i),
701
        .stb_o(wbi_stb_o),
702
        .adr_o(wbi_adr_o),
703
        .ack_i(wbi_ack_i),
704 174 simont
        .cyc_o(wbi_cyc_o)
705
`ifdef OC8051_BIST
706
         ,
707
         .scanb_rst(scanb_rst),
708
         .scanb_clk(scanb_clk),
709
         .scanb_si(scanb_si),
710
         .scanb_so(scanb_soi),
711
         .scanb_en(scanb_en)
712
`endif
713
        );
714 107 simont
 
715 148 simont
  defparam oc8051_icache1.ADR_WIDTH = 6;  // cache address wihth
716
  defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
717
  defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
718
  defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)
719 107 simont
 
720 174 simont
 
721
 
722 181 simont
  `ifdef OC8051_SIMULATION
723 174 simont
 
724 181 simont
    initial
725
    begin
726
      #1
727
      $display("\t * ");
728
      $display("\t * External rom interface: cache");
729
      $display("\t * ");
730
    end
731 174 simont
 
732 181 simont
  `endif
733 174 simont
 
734
 
735 181 simont
 
736 107 simont
//
737
//    no cache
738
//
739
`else
740
 
741 174 simont
  `ifdef OC8051_BIST
742
       assign scanb_soi=scanb_si;
743
  `endif
744
 
745 148 simont
  `ifdef OC8051_WB
746
 
747
    oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
748
    // cpu
749 107 simont
        .adr_i(iadr_o),
750
        .dat_o(idat_i),
751
        .stb_i(istb_o),
752
        .ack_o(iack_i),
753
        .cyc_i(icyc_o),
754 148 simont
    // external rom
755 107 simont
        .dat_i(wbi_dat_i),
756
        .stb_o(wbi_stb_o),
757
        .adr_o(wbi_adr_o),
758
        .ack_i(wbi_ack_i),
759
        .cyc_o(wbi_cyc_o));
760
 
761 181 simont
  `ifdef OC8051_SIMULATION
762 174 simont
 
763 181 simont
    initial
764
    begin
765
      #1
766
      $display("\t * ");
767
      $display("\t * External rom interface: WB interface");
768
      $display("\t * ");
769
    end
770 174 simont
 
771 181 simont
  `endif
772 174 simont
 
773 148 simont
  `else
774 107 simont
 
775 148 simont
    assign wbi_adr_o = iadr_o    ;
776
    assign idat_i    = wbi_dat_i ;
777
    assign wbi_stb_o = 1'b1      ;
778
    assign iack_i    = wbi_ack_i ;
779
    assign wbi_cyc_o = 1'b1      ;
780
 
781 181 simont
  `ifdef OC8051_SIMULATION
782 174 simont
 
783 181 simont
    initial
784
    begin
785
      #1
786
      $display("\t * ");
787
      $display("\t * External rom interface: Pipelined interface");
788
      $display("\t * ");
789
    end
790 174 simont
 
791 181 simont
  `endif
792 174 simont
 
793 181 simont
 
794 148 simont
  `endif
795
 
796 107 simont
`endif
797
 
798
 
799
 
800 72 simont
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.