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//////////////////////////////////////////////////////////////////////
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//// ////
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//// 8051 cores top level module ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// ////
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//// Description ////
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//// 8051 definitions. ////
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//// ////
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//// To Do: ////
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//// nothing ////
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//// ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.15 2002/10/23 16:53:39 simont
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// fix bugs in instruction interface
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//
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// Revision 1.14 2002/10/17 18:50:00 simont
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// cahnge interface to instruction rom
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//
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// Revision 1.13 2002/09/30 17:33:59 simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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module oc8051_top (rst, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, dat_i,
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icyc_o, dat_o, adr_o, we_o, ack_i, stb_o, cyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
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p1_out, p2_out, p3_out, rxd, txd, t0, t1);
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//
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// rst (in) reset - pin
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// clk (in) clock - pin
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// iadr_o (out) program rom addres (pin + internal)
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// int0 (in) external interrupt 0
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// int1 (in) external interrupt 1
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// dat_i (in) exteranal ram input
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// dat_o (out) exteranal ram output
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// adr_o (out) external address
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// we_o (out) write to external ram
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// stb_o
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// ack_i
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// idat_i (in) data from external program rom
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// istb_o (out) strobe to program rom
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// iack_i (in) acknowlage from external rom
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// icyc_o (out)
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// p0_in, p1_in, p2_in, p3_in (in) port inputs
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// p0_out, p1_out, p2_out, p3_out (out) port outputs
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// rxd (in) receive
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// txd (out) transmit
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// t0, t1 (in) t/c external inputs
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//
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//
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input rst, clk, int0, int1, ea, rxd, t0, t1, ack_i, iack_i;
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input [7:0] dat_i, p0_in, p1_in, p2_in, p3_in;
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input [31:0] idat_i;
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output we_o, txd, stb_o, cyc_o, istb_o, icyc_o;
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output [7:0] dat_o, p0_out, p1_out, p2_out, p3_out;
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//output [15:0] rom_addr, ext_addr;
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output [15:0] adr_o, iadr_o;
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wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, data_out;
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wire [7:0] op1, op2, op3;
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wire [7:0] acc, b_reg, p0_out, p1_out, p2_out, p3_out, uart, tc_out, int_out;
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wire [15:0] pc;
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//
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// data output is always from accumulator
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assign dat_o = acc;
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assign cyc_o = stb_o;
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assign icyc_o = istb_o;
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assign op1 = idat_i[31:24];
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assign op2 = idat_i[23:16];
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assign op3 = idat_i[15:8];
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//
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// ram_rd_sel ram read (internal)
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// ram_wr_sel ram write (internal)
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// src_sel1, src_sel2 from decoder to register
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// imm_sel immediate select
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wire [1:0] ram_rd_sel, src_sel1, src_sel2;
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wire [2:0] ram_wr_sel, ram_wr_sel_r, imm_sel;
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//
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// wr_addr ram write addres
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// ram_out data from ram
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// sp stack pointer output
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// rd_addr data ram read addres
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// rd_addr_r data ram read addres registerd
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wire [7:0] wr_addr, ram_data, ram_out, sp, sp_r, rd_addr, rd_addr_r, ports_in;
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//
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// src_sel1_r, src_sel2_r src select, registred
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// cy_sel carry select; from decoder to cy_selct1
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// rom_addr_sel rom addres select; alu or pc
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// ext_adddr_sel external addres select; data pointer or Ri
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// write_p output from decoder; write to external ram, go to register;
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wire [1:0] src_sel1_r, src_sel2_r, cy_sel, cy_sel_r;
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wire src_sel3, src_sel3_r, rom_addr_sel, ext_addr_sel, rmw, ea_int, wr_xaddr;
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//
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// int_uart interrupt from uart
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// tf0 interrupt from t/c 0
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// tf1 interrupt from t/c 1
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// tr0 timer 0 run
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// tr1 timer 1 run
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wire int_uart, tf0, tf1, tr0, tr1, reti, intr, ack, istb;
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wire [7:0] int_src;
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//
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//alu_op alu operation (from decoder)
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//alu_op_r alu operation (registerd)
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//psw_set write to psw or not; from decoder to psw (through register)
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wire [3:0] alu_op, alu_op_r; wire [1:0] psw_set, psw_set_r;
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//
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// immediate1_r from imediate_sel1 to alu_src1_sel1
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// immediate2_r from imediate_sel1 to alu_src2_sel1
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// src1. src2, src2 alu sources
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// des2, des2 alu destinations
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// des1_r destination 1 registerd (to comp1)
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// psw output from psw
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// desCy carry out
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// desAc
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// desOv overflow
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// wr, wr_r write to data ram
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wire [7:0] src1, src2, src3, des1, des2, des1_r, psw, psw_r;
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wire desCy, desAc, desOv, alu_cy, wr, wr_r;
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wire [7:0] immediate1_r, immediate2_r;
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//
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// rd read program rom
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// pc_wr_sel program counter write select (from decoder to pc)
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wire rd, pc_wr;
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wire [1:0] pc_wr_sel;
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//
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// op1_n from op_select to decoder
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// op2_n, output of op_select, to immediate_sel1, pc1, comp1
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// op3_n, output of op_select, to immediate_sel1, ram_wr_sel1
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// op2_dr, output of op_select, to ram_rd_sel1, ram_wr_sel1
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wire [7:0] op1_n, op2_n, op2_dr, op3_n, pc_hi_r;
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wire [7:0] op2_dr_r, ri_r, op3_nr;
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wire [2:0] op1_r;
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//
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// comp_sel select source1 and source2 to compare
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// eq result (from comp1 to decoder)
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// wad2, wad2_r write to accumulator from destination 2
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wire [1:0] comp_sel;
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wire eq, wad2, wad2_r, nop;
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//
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// bit_addr bit addresable instruction
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// bit_data bit data from ram to ram_select
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// bit_out bit data from ram_select to alu and cy_select
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wire bit_addr, bit_data, bit_out, bit_addr_r;
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//
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// p parity from accumulator to psw
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wire p, pc_wait;
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wire b_bit, acc_bit, psw_bit, int_bit, port_bit, uart_bit;
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//
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//registers
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oc8051_reg8 oc8051_reg8_pc_hi(.clk(clk), .rst(rst), .din(pc[15:8]), .dout(pc_hi_r));
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//oc8051_reg1 oc8051_reg1_write(.clk(clk), .rst(rst), .din(write_p), .dout(we_o));
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oc8051_reg2 oc8051_reg2_src_sel1(.clk(clk), .rst(rst), .din(src_sel1), .dout(src_sel1_r));
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oc8051_reg2 oc8051_reg2_src_sel2(.clk(clk), .rst(rst), .din(src_sel2), .dout(src_sel2_r));
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oc8051_reg1 oc8051_reg1_sre_sel3(.clk(clk), .rst(rst), .din(src_sel3), .dout(src_sel3_r));
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oc8051_reg1 oc8051_reg1_wr (.clk(clk), .rst(rst), .din(wr), .dout(wr_r));
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//oc8051_reg8 oc8051_reg8_wr_addr (.clk(clk), .rst(rst), .din(wr_addr1), .dout(wr_addr_r));
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oc8051_reg3 oc8051_reg3_wr_sel(.clk(clk), .rst(rst), .din(ram_wr_sel), .dout(ram_wr_sel_r));
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oc8051_reg3 oc8051_reg3_op1(.clk(clk), .rst(rst), .din(op1_n[2:0]), .dout(op1_r));
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oc8051_reg8 oc8051_reg8_op2(.clk(clk), .rst(rst), .din(op2_dr), .dout(op2_dr_r));
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oc8051_reg8 oc8051_reg8_ri(.clk(clk), .rst(rst), .din(ri), .dout(ri_r));
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oc8051_reg8 oc8051_reg8_op3(.clk(clk), .rst(rst), .din(op3_n), .dout(op3_nr));
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//oc8051_reg5 oc8051_reg5_rn(.clk(clk), .rst(rst), .din({psw[4:3], op1_n[2:0]}), .dout(rn_r));
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oc8051_reg4 oc8051_reg4_alu_op(.clk(clk), .rst(rst), .din(alu_op), .dout(alu_op_r));
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oc8051_reg1 oc8051_reg1_bit_addr(.clk(clk), .rst(rst), .din(bit_addr), .dout(bit_addr_r));
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oc8051_reg1 oc8051_reg1_wad2(.clk(clk), .rst(rst), .din(wad2), .dout(wad2_r));
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//oc8051_reg8 oc8051_reg8_des1(.clk(clk), .rst(rst), .din(des1), .dout(des1_r));
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oc8051_reg2 oc8051_reg2_cy(.clk(clk), .rst(rst), .din(cy_sel), .dout(cy_sel_r));
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oc8051_reg2 oc8051_psw_reg (.clk(clk), .rst(rst), .din(psw_set), .dout(psw_set_r));
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//oc8051_reg8 oc8051_op2_dr_reg (.clk(clk), .rst(rst), .din(op2_dr), .dout(op2_dr_r));
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oc8051_reg8 oc8051_reg8_rd_ram (.clk(clk), .rst(rst), .din(rd_addr), .dout(rd_addr_r));
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//
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//program counter
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oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
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.pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
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.rd((pc_wait && !(istb_o && !iack_i))), .intr(intr));
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//
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// decoder
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oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n),
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.ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
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.src_sel1(src_sel1), .wr_xaddr(wr_xaddr), .src_sel2(src_sel2),
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.src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
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.imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
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.pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
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.rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
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.wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw),
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.stb_o(stb_o), .ack_i(ack_i), .istb(istb), .ea(ea && ea_int),
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.iack(iack_i), .pc_wait(pc_wait), .nop(nop));
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//
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262 |
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// ram read and ram write select
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263 |
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oc8051_ram_rd_sel oc8051_ram_rd_sel1 (.sel(ram_rd_sel), .sp(sp), .ri(ri),
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.rn({psw[4:3], op1_n[2:0]}), .imm(op2_dr), .addr_out(rd_addr));
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oc8051_ram_wr_sel oc8051_ram_wr_sel1 (.sel(ram_wr_sel_r), .sp(sp_r),
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.rn({psw_r[4:3], op1_r}), .imm(op2_dr_r), .ri(ri_r), .imm2(op3_nr), .addr_out(wr_addr));
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269 |
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270 |
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//
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//alu
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oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op_r), .src1(src1), .src2(src2), .src3(src3),
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.srcCy(alu_cy), .srcAc(psw_r[6]), .des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
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.desAc(desAc), .desOv(desOv), .bit_in(bit_out));
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276 |
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//
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278 |
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//
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279 |
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oc8051_immediate_sel oc8051_immediate_sel1(.clk(clk), .rst(rst), .sel(imm_sel), .op1(op1_n), .op2(op2_n),
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.op3(op3_n), .pch(pc_hi_r), .pcl(pc[7:0]), .out1(immediate1_r), .out2(immediate2_r));
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281 |
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282 |
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//
|
283 |
|
|
//data ram
|
284 |
|
|
oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
|
285 |
|
|
.wr_addr(wr_addr), .bit_addr(bit_addr), .wr_data(des1), .wr(wr_r),
|
286 |
|
|
.bit_data_in(desCy), .bit_data_out(bit_data));
|
287 |
|
|
|
288 |
|
|
//
|
289 |
|
|
//
|
290 |
|
|
oc8051_acc oc8051_acc1(.clk(clk), .rst(rst), .bit_in(desCy), .data_in(des1),
|
291 |
|
|
.data2_in(des2), .wr(wr_r), .wr_bit(bit_addr_r), .wad2(wad2_r),
|
292 |
|
|
.wr_addr(wr_addr), .rd_addr(rd_addr[2:0]), .data_out(acc), .bit_out(acc_bit), .p(p),
|
293 |
|
|
.stb_o(stb_o), .we_o(we_o), .ack_i(ack_i), .xdata(dat_i));
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
//
|
297 |
|
|
//
|
298 |
|
|
oc8051_b_register oc8051_b_register (.clk(clk), .rst(rst), .bit_in(desCy), .bit_out(b_bit), .data_in(des1),
|
299 |
|
|
.wr(wr_r), .wr_bit(bit_addr_r), .wr_addr(wr_addr), .rd_addr(rd_addr[2:0]), .data_out(b_reg));
|
300 |
|
|
|
301 |
|
|
//
|
302 |
|
|
//
|
303 |
|
|
oc8051_alu_src1_sel oc8051_alu_src1_sel1(.sel(src_sel1_r), .immediate(immediate1_r),
|
304 |
|
|
.acc(acc), .ram(ram_out), .ext(dat_i), .des(src1));
|
305 |
|
|
oc8051_alu_src2_sel oc8051_alu_src2_sel1(.sel(src_sel2_r), .immediate(immediate2_r),
|
306 |
|
|
.acc(acc), .ram(ram_out), .des(src2));
|
307 |
|
|
oc8051_alu_src3_sel oc8051_alu_src3_sel1(.sel(src_sel3_r), .pc(pc_hi_r),
|
308 |
|
|
.dptr(dptr_hi), .des(src3));
|
309 |
|
|
|
310 |
|
|
//
|
311 |
|
|
//
|
312 |
|
|
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(psw_r[7]), .acc(acc), .des(des1_r));
|
313 |
|
|
|
314 |
|
|
//
|
315 |
|
|
//stack pointer
|
316 |
|
|
oc8051_sp oc8051_sp1(.clk(clk), .rst(rst), .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
|
317 |
|
|
.wr_addr(wr_addr), .wr(wr_r), .wr_bit(bit_addr_r), .data_in(des1),
|
318 |
|
|
.data_out(sp), .data_out_r (sp_r));
|
319 |
|
|
|
320 |
|
|
//
|
321 |
|
|
//program rom
|
322 |
|
|
oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(iadr_o),
|
323 |
|
|
.data1(op1_i), .data2(op2_i), .data3(op3_i));
|
324 |
|
|
|
325 |
|
|
//
|
326 |
|
|
//data pointer
|
327 |
|
|
oc8051_dptr oc8051_dptr1(.clk(clk), .rst(rst), .addr(wr_addr), .data_in(des1),
|
328 |
|
|
.data2_in(des2), .wr(wr_r), .wr_bit(bit_addr_r), .wd2(ram_wr_sel_r),
|
329 |
|
|
.data_hi(dptr_hi), .data_lo(dptr_lo));
|
330 |
|
|
|
331 |
|
|
//
|
332 |
|
|
//
|
333 |
|
|
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel_r), .cy_in(psw_r[7]), .data_in(bit_out),
|
334 |
|
|
.data_out(alu_cy));
|
335 |
|
|
|
336 |
|
|
//
|
337 |
|
|
//program status word
|
338 |
|
|
oc8051_psw oc8051_psw1 (.clk(clk), .rst(rst), .wr_addr(wr_addr), .rd_addr(rd_addr[2:0]), .data_in(des1), .wr(wr_r),
|
339 |
|
|
.wr_bit(bit_addr_r), .data_out(psw), .data_out_r(psw_r), .bit_out(psw_bit), .p(p), .cy_in(desCy),
|
340 |
|
|
.ac_in(desAc), .ov_in(desOv), .set(psw_set_r));
|
341 |
|
|
|
342 |
|
|
//
|
343 |
|
|
//
|
344 |
54 |
simont |
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .addr(wr_addr),
|
345 |
|
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .data_out(ri),
|
346 |
72 |
simont |
.sel(op1_n[0]), .bank(psw[4:3]));
|
347 |
|
|
|
348 |
|
|
//
|
349 |
|
|
//
|
350 |
54 |
simont |
oc8051_rom_addr_sel oc8051_rom_addr_sel1(.clk(clk), .rst(rst), .iack_i(iack_i),
|
351 |
|
|
.ea(ea && ea_int), .sel(rom_addr_sel), .des1(des1), .des2(des2),
|
352 |
72 |
simont |
.pc(pc), .out_addr(iadr_o));
|
353 |
|
|
|
354 |
|
|
//
|
355 |
|
|
//
|
356 |
|
|
oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
|
357 |
|
|
.dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o),
|
358 |
|
|
.wr(wr_xaddr), .stb(stb_o));
|
359 |
|
|
|
360 |
|
|
//
|
361 |
|
|
//
|
362 |
|
|
oc8051_ram_sel oc8051_ram_sel1(.addr(rd_addr_r), .bit_in(bit_data), .in_ram(ram_data),
|
363 |
|
|
.psw(psw_r), .acc(acc), .dptr_hi(dptr_hi), .ports_in(ports_in), .sp(sp_r),
|
364 |
|
|
.b_reg(b_reg), .uart(uart), .int(int_out), .tc(tc_out), .b_bit(b_bit),
|
365 |
|
|
.acc_bit(acc_bit), .psw_bit(psw_bit), .int_bit(int_bit), .port_bit(port_bit),
|
366 |
|
|
.uart_bit(uart_bit), .bit_out(bit_out), .out_data(ram_out));
|
367 |
|
|
|
368 |
|
|
//
|
369 |
|
|
//
|
370 |
|
|
oc8051_ports oc8051_ports1(.clk(clk), .rst(rst), .bit_in(desCy), .data_in(des1), .wr(wr_r),
|
371 |
|
|
.wr_bit(bit_addr_r), .wr_addr(wr_addr), .rd_addr(rd_addr), .rmw(rmw),
|
372 |
|
|
.data_out(ports_in), .bit_out(port_bit), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out),
|
373 |
|
|
.p3_out(p3_out), .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in));
|
374 |
|
|
|
375 |
|
|
//
|
376 |
|
|
//
|
377 |
|
|
oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
|
378 |
|
|
.op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
|
379 |
|
|
.op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
|
380 |
62 |
simont |
.intr(intr), .int_v(int_src), .rd(rd), .ack(ack), .istb(istb),
|
381 |
72 |
simont |
.istb_o(istb_o), .iack_i(iack_i), .nop(nop));
|
382 |
|
|
|
383 |
|
|
//
|
384 |
|
|
// serial interface
|
385 |
|
|
oc8051_uart oc8051_uatr1 (.clk(clk), .rst(rst), .bit_in(desCy), .rd_addr(rd_addr),
|
386 |
|
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .wr_addr(wr_addr),
|
387 |
|
|
.data_out(uart), .bit_out(uart_bit), .rxd(rxd), .txd(txd), .intr(int_uart), .t1_ow(tf1));
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
oc0851_int oc8051_int1(.clk(clk), .rst(rst), .wr_addr(wr_addr), .rd_addr(rd_addr), .bit_in(desCy), .ack(ack),
|
391 |
|
|
.intr(intr), .data_in(des1), .data_out(int_out), .bit_out(int_bit), .wr(wr_r), .wr_bit(bit_addr_r), .tf0(tf0), .tf1(tf1),
|
392 |
|
|
.ie0(int0), .ie1(int1), .reti(reti), .int_vec(int_src), .tr0(tr0), .tr1(tr1), .uart(int_uart));
|
393 |
|
|
|
394 |
|
|
oc8051_tc oc8051_tc1(.clk(clk), .rst(rst), .wr_addr(wr_addr), .rd_addr(rd_addr),
|
395 |
|
|
.data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .ie0(int0), .ie1(int1), .tr0(tr0),
|
396 |
|
|
.tr1(tr1), .t0(t0), .t1(t1), .data_out(tc_out), .tf0(tf0), .tf1(tf1));
|
397 |
|
|
|
398 |
|
|
endmodule
|