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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Blame information for rev 76

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1 72 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 cores top level module                                 ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  8051 definitions.                                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46 54 simont
// $Log: not supported by cvs2svn $
47 76 simont
// Revision 1.16  2002/10/28 14:55:00  simont
48
// fix bug in interface to external data ram
49
//
50 72 simont
// Revision 1.15  2002/10/23 16:53:39  simont
51
// fix bugs in instruction interface
52
//
53 62 simont
// Revision 1.14  2002/10/17 18:50:00  simont
54
// cahnge interface to instruction rom
55
//
56 54 simont
// Revision 1.13  2002/09/30 17:33:59  simont
57
// prepared header
58 72 simont
//
59
//
60
 
61
// synopsys translate_off
62
`include "oc8051_timescale.v"
63
// synopsys translate_on
64
 
65
 
66
module oc8051_top (rst, clk, int0, int1, ea, iadr_o, idat_i,istb_o, iack_i, dat_i,
67
                icyc_o, dat_o, adr_o, we_o, ack_i, stb_o, cyc_o, p0_in, p1_in, p2_in, p3_in, p0_out,
68
                p1_out, p2_out, p3_out, rxd, txd, t0, t1);
69
//
70
// rst           (in)  reset - pin
71
// clk           (in)  clock - pin
72
// iadr_o        (out) program rom addres (pin + internal)
73
// int0          (in)  external interrupt 0
74
// int1          (in)  external interrupt 1
75
// dat_i         (in)  exteranal ram input
76
// dat_o         (out) exteranal ram output
77
// adr_o         (out) external address
78
// we_o          (out) write to external ram
79
// stb_o
80
// ack_i
81 54 simont
// idat_i        (in)  data from external program rom
82
// istb_o        (out) strobe to program rom
83
// iack_i        (in)  acknowlage from external rom
84
// icyc_o        (out)
85 72 simont
// p0_in, p1_in, p2_in, p3_in           (in)  port inputs
86
// p0_out, p1_out, p2_out, p3_out       (out) port outputs
87
// rxd           (in) receive
88
// txd           (out) transmit
89
// t0, t1        (in)  t/c external inputs
90
//
91
//
92
 
93
 
94
 
95
input rst, clk, int0, int1, ea, rxd, t0, t1, ack_i, iack_i;
96
input [7:0] dat_i, p0_in, p1_in, p2_in, p3_in;
97 54 simont
input [31:0] idat_i;
98 72 simont
 
99
output we_o, txd, stb_o, cyc_o, istb_o, icyc_o;
100
output [7:0] dat_o, p0_out, p1_out, p2_out, p3_out;
101
//output [15:0] rom_addr, ext_addr;
102
output [15:0] adr_o, iadr_o;
103
 
104 76 simont
wire [7:0] op1_i, op2_i, op3_i, dptr_hi, dptr_lo, ri, data_out, sp;
105 54 simont
wire [7:0] op1, op2, op3;
106 76 simont
wire [7:0] acc, p0_out, p1_out, p2_out, p3_out;
107 72 simont
 
108
wire [15:0] pc;
109
 
110
//
111
// data output is always from accumulator
112
assign dat_o = acc;
113
 
114
assign cyc_o = stb_o;
115 54 simont
assign icyc_o = istb_o;
116
 
117 72 simont
 
118 54 simont
assign op1 = idat_i[31:24];
119
assign op2 = idat_i[23:16];
120
assign op3 = idat_i[15:8];
121
 
122 72 simont
//
123
// ram_rd_sel    ram read (internal)
124
// ram_wr_sel    ram write (internal)
125
// src_sel1, src_sel2    from decoder to register
126
// imm_sel       immediate select
127
wire [1:0] ram_rd_sel, src_sel1, src_sel2;
128 76 simont
wire [2:0] ram_wr_sel, imm_sel;
129 72 simont
 
130
//
131
// wr_addr       ram write addres
132
// ram_out       data from ram
133
// sp            stack pointer output
134
// rd_addr       data ram read addres
135
// rd_addr_r     data ram read addres registerd
136 76 simont
wire [7:0] wr_addr, ram_data, ram_out, rd_addr, rd_addr_r, sfr_out;
137
wire sfr_bit;
138 72 simont
 
139
 
140
//
141
// src_sel1_r, src_sel2_r       src select, registred
142
// cy_sel       carry select; from decoder to cy_selct1
143
// rom_addr_sel rom addres select; alu or pc
144
// ext_adddr_sel        external addres select; data pointer or Ri
145
// write_p      output from decoder; write to external ram, go to register;
146 76 simont
wire [1:0] src_sel1_r, src_sel2_r, cy_sel, cy_sel_r, bank_sel;
147 72 simont
wire src_sel3, src_sel3_r, rom_addr_sel, ext_addr_sel, rmw, ea_int, wr_xaddr;
148
 
149
//
150
// int_uart     interrupt from uart
151
// tf0          interrupt from t/c 0
152
// tf1          interrupt from t/c 1
153
// tr0          timer 0 run
154
// tr1          timer 1 run
155 76 simont
wire reti, intr, int_ack, istb;
156 72 simont
wire [7:0] int_src;
157
 
158
//
159
//alu_op        alu operation (from decoder)
160
//alu_op_r      alu operation (registerd)
161
//psw_set       write to psw or not; from decoder to psw (through register)
162
wire [3:0] alu_op, alu_op_r; wire [1:0] psw_set, psw_set_r;
163
 
164
//
165
// immediate1_r         from imediate_sel1 to alu_src1_sel1
166
// immediate2_r         from imediate_sel1 to alu_src2_sel1
167
// src1. src2, src2     alu sources
168
// des2, des2           alu destinations
169
// des1_r               destination 1 registerd (to comp1)
170
// desCy                carry out
171
// desAc
172
// desOv                overflow
173
// wr, wr_r             write to data ram
174 76 simont
wire [7:0] src1, src2, src3, des1, des2, des1_r;
175 72 simont
wire desCy, desAc, desOv, alu_cy, wr, wr_r;
176
wire [7:0] immediate1_r, immediate2_r;
177
 
178
 
179
//
180
// rd           read program rom
181
// pc_wr_sel    program counter write select (from decoder to pc)
182
wire rd, pc_wr;
183
wire [1:0] pc_wr_sel;
184
 
185
//
186
// op1_n                from op_select to decoder
187
// op2_n,         output of op_select, to immediate_sel1, pc1, comp1
188
// op3_n,         output of op_select, to immediate_sel1, ram_wr_sel1
189
// op2_dr,      output of op_select, to ram_rd_sel1, ram_wr_sel1
190
wire [7:0] op1_n, op2_n, op2_dr, op3_n, pc_hi_r;
191 76 simont
//wire [2:0] op1_r;
192 72 simont
 
193
//
194
// comp_sel     select source1 and source2 to compare
195
// eq           result (from comp1 to decoder)
196
// wad2, wad2_r write to accumulator from destination 2
197
wire [1:0] comp_sel;
198 76 simont
wire eq, wad2, wad2_r, nop, srcAc, cy, rd_ind, wr_ind;
199 72 simont
 
200
 
201
//
202
// bit_addr     bit addresable instruction
203
// bit_data     bit data from ram to ram_select
204
// bit_out      bit data from ram_select to alu and cy_select
205
wire bit_addr, bit_data, bit_out, bit_addr_r;
206
 
207
//
208 76 simont
wire pc_wait;
209 72 simont
 
210
 
211
//
212
//registers
213
oc8051_reg8 oc8051_reg8_pc_hi(.clk(clk), .rst(rst), .din(pc[15:8]), .dout(pc_hi_r));
214
 
215
oc8051_reg2 oc8051_reg2_src_sel1(.clk(clk), .rst(rst), .din(src_sel1), .dout(src_sel1_r));
216
oc8051_reg2 oc8051_reg2_src_sel2(.clk(clk), .rst(rst), .din(src_sel2), .dout(src_sel2_r));
217
oc8051_reg1 oc8051_reg1_sre_sel3(.clk(clk), .rst(rst), .din(src_sel3), .dout(src_sel3_r));
218
 
219
oc8051_reg1 oc8051_reg1_wr (.clk(clk), .rst(rst), .din(wr), .dout(wr_r));
220
 
221
oc8051_reg4 oc8051_reg4_alu_op(.clk(clk), .rst(rst), .din(alu_op), .dout(alu_op_r));
222
 
223
oc8051_reg1 oc8051_reg1_bit_addr(.clk(clk), .rst(rst), .din(bit_addr), .dout(bit_addr_r));
224
 
225
oc8051_reg1 oc8051_reg1_wad2(.clk(clk), .rst(rst), .din(wad2), .dout(wad2_r));
226
oc8051_reg2 oc8051_reg2_cy(.clk(clk), .rst(rst), .din(cy_sel), .dout(cy_sel_r));
227
oc8051_reg2 oc8051_psw_reg (.clk(clk), .rst(rst), .din(psw_set), .dout(psw_set_r));
228
oc8051_reg8 oc8051_reg8_rd_ram (.clk(clk), .rst(rst), .din(rd_addr), .dout(rd_addr_r));
229
 
230 76 simont
 
231
 
232
 
233 72 simont
//
234
//program counter
235
oc8051_pc oc8051_pc1(.rst(rst), .clk(clk), .pc_out(pc), .alu({des2,des1}),
236
       .pc_wr_sel(pc_wr_sel), .op1(op1_n), .op2(op2_n), .op3(op3_n), .wr(pc_wr),
237
       .rd((pc_wait && !(istb_o && !iack_i))), .intr(intr));
238
 
239
//
240
// decoder
241 76 simont
oc8051_decoder oc8051_decoder1(.clk(clk), .rst(rst), .op_in(op1_n),
242
     .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel), .bit_addr(bit_addr),
243
     .src_sel1(src_sel1), .wr_xaddr(wr_xaddr), .src_sel2(src_sel2),
244 62 simont
     .src_sel3(src_sel3), .alu_op(alu_op), .psw_set(psw_set),
245 76 simont
     .imm_sel(imm_sel), .cy_sel(cy_sel), .wr(wr), .pc_wr(pc_wr),
246
     .pc_sel(pc_wr_sel), .comp_sel(comp_sel), .eq(eq),
247 72 simont
     .rom_addr_sel(rom_addr_sel), .ext_addr_sel(ext_addr_sel),
248 76 simont
     .wad2(wad2), .rd(rd), .we_o(we_o), .reti(reti), .rmw(rmw),
249 62 simont
     .stb_o(stb_o), .ack_i(ack_i), .istb(istb), .ea(ea && ea_int),
250 72 simont
     .iack(iack_i), .pc_wait(pc_wait), .nop(nop));
251
 
252
 
253
 
254
//
255 76 simont
// internal ram address select
256
oc8051_ram_adr_sel oc8051_ram_rd_sel1 (.rst(rst), .clk(clk), .rd_sel(ram_rd_sel),
257
            .wr_sel(ram_wr_sel), .sp(sp), .ri(ri), .rn({bank_sel, op1_n[2:0]}), .imm(op2_dr),
258
            .imm2(op3_n), .rd_addr(rd_addr), .wr_addr(wr_addr), .rd_ind(rd_ind), .wr_ind(wr_ind));
259 72 simont
 
260
 
261
 
262
//
263
//alu
264
oc8051_alu oc8051_alu1(.rst(rst), .clk(clk), .op_code(alu_op_r), .src1(src1), .src2(src2), .src3(src3),
265 76 simont
         .srcCy(alu_cy), .srcAc(srcAc), .des1(des1), .des2(des2), .des1_r(des1_r), .desCy(desCy),
266 72 simont
         .desAc(desAc), .desOv(desOv), .bit_in(bit_out));
267
 
268
 
269
//
270
//
271
oc8051_immediate_sel oc8051_immediate_sel1(.clk(clk), .rst(rst), .sel(imm_sel), .op1(op1_n), .op2(op2_n),
272
          .op3(op3_n), .pch(pc_hi_r), .pcl(pc[7:0]), .out1(immediate1_r), .out2(immediate2_r));
273
 
274
//
275
//data ram
276
oc8051_ram_top oc8051_ram_top1(.clk(clk), .rst(rst), .rd_addr(rd_addr), .rd_data(ram_data),
277 76 simont
          .wr_addr(wr_addr), .bit_addr(bit_addr), .wr_data(des1), .wr(wr_r && (!wr_addr[7] || wr_ind)),
278 72 simont
          .bit_data_in(desCy), .bit_data_out(bit_data));
279
 
280
//
281
//
282
oc8051_alu_src1_sel oc8051_alu_src1_sel1(.sel(src_sel1_r), .immediate(immediate1_r),
283
                .acc(acc), .ram(ram_out), .ext(dat_i), .des(src1));
284
oc8051_alu_src2_sel oc8051_alu_src2_sel1(.sel(src_sel2_r), .immediate(immediate2_r),
285
                .acc(acc), .ram(ram_out), .des(src2));
286
oc8051_alu_src3_sel oc8051_alu_src3_sel1(.sel(src_sel3_r), .pc(pc_hi_r),
287
                .dptr(dptr_hi), .des(src3));
288
 
289
//
290
//
291 76 simont
oc8051_comp oc8051_comp1(.sel(comp_sel), .eq(eq), .b_in(bit_out), .cy(cy), .acc(acc), .des(des1_r));
292 72 simont
 
293
 
294
//
295
//program rom
296 76 simont
oc8051_rom oc8051_rom1(.rst(rst), .clk(clk), .ea_int(ea_int), .addr(iadr_o),
297 72 simont
                .data1(op1_i), .data2(op2_i), .data3(op3_i));
298
 
299
//
300
//
301 76 simont
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel_r), .cy_in(cy), .data_in(bit_out),
302 72 simont
                 .data_out(alu_cy));
303
//
304
//
305 76 simont
oc8051_indi_addr oc8051_indi_addr1 (.clk(clk), .rst(rst), .addr(wr_addr),
306
      .data_in(des1), .wr(wr_r), .wr_bit(bit_addr_r), .data_out(ri),
307
      .sel(op1_n[0]), .bank(bank_sel));
308 72 simont
 
309
//
310
//
311 54 simont
oc8051_rom_addr_sel oc8051_rom_addr_sel1(.clk(clk), .rst(rst), .iack_i(iack_i),
312 76 simont
               .ea(ea && ea_int), .sel(rom_addr_sel), .des1(des1), .des2(des2),
313 72 simont
               .pc(pc), .out_addr(iadr_o));
314
 
315
//
316
//
317
oc8051_ext_addr_sel oc8051_ext_addr_sel1(.clk(clk), .rst(rst), .sel(ext_addr_sel),
318
                 .dptr_hi(dptr_hi), .dptr_lo(dptr_lo), .ri(ri), .addr_out(adr_o),
319
                 .wr(wr_xaddr), .stb(stb_o));
320
//
321
//
322 76 simont
oc8051_ram_sel oc8051_ram_sel1(.addr(rd_addr_r), .bit_in(bit_data), .in_ram(ram_data), .rd_ind(rd_ind),
323
                .sfr(sfr_out), .sfr_bit(sfr_bit), .bit_out(bit_out), .out_data(ram_out));
324 72 simont
 
325
//
326
//
327
oc8051_op_select oc8051_op_select1(.clk(clk), .rst(rst), .ea(ea), .ea_int(ea_int), .op1_i(op1_i),
328
                .op2_i(op2_i), .op3_i(op3_i), .op1_x(op1), .op2_x(op2), .op3_x(op3),
329
                .op1_out(op1_n), .op2_out(op2_n), .op2_direct(op2_dr), .op3_out(op3_n),
330 76 simont
                .intr(intr), .int_v(int_src), .rd(rd), .ack(int_ack), .istb(istb),
331 72 simont
    .istb_o(istb_o), .iack_i(iack_i), .nop(nop));
332
 
333
 
334 76 simont
oc8051_sfr oc8051_sfr1(.rst(rst), .clk(clk), .adr0(rd_addr), .adr1(wr_addr), .dat0(sfr_out),
335
       .dat1(des1), .dat2(des2), .we(wr_r && !wr_ind), .bit_in(desCy), .bit_out(sfr_bit), .wr_bit(bit_addr_r),
336
       .ram_rd_sel(ram_rd_sel), .ram_wr_sel(ram_wr_sel),
337
// acc
338
       .wad2(wad2_r), .acc(acc), .rd_x(stb_o && !we_o && ack_i), .xdata(dat_i),
339
// sp
340
       .sp(sp),
341
// psw
342
       .bank_sel(bank_sel), .desAc(desAc), .desOv(desOv), .psw_set(psw_set_r),
343
       .srcAc(srcAc), .cy(cy),
344
// ports
345
       .rmw(rmw), .p0_out(p0_out), .p1_out(p1_out), .p2_out(p2_out), .p3_out(p3_out),
346
       .p0_in(p0_in), .p1_in(p1_in), .p2_in(p2_in), .p3_in(p3_in),
347
// uart
348
       .rxd(rxd), .txd(txd),
349
// int
350
       .int_ack(int_ack), .intr(intr), .int0(int0), .int1(int1), .reti(reti), .int_src(int_src),
351
// t/c
352
       .t0(t0), .t1(t1),
353
// dptr
354
       .dptr_hi(dptr_hi), .dptr_lo(dptr_lo));
355 72 simont
 
356
endmodule

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