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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores serial interface                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   uart for 8051 core                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.10  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.9  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk,
             bit_in, data_in,
             rd_addr, wr_addr,
             bit_out, data_out,
             wr, wr_bit,
             rxd, txd,
             intr,
             brate2, t1_ow, pres_ow,
             rclk, tclk);
 
input        rst,
             clk,
             bit_in,
             wr,
             rxd,
             wr_bit,
             t1_ow,
             brate2,
             pres_ow,
             rclk,
             tclk;
input [7:0]  rd_addr,
             data_in,
             wr_addr;
 
output       txd,
             intr,
             bit_out;
output [7:0] data_out;
 
reg /*txd, */bit_out;
reg [7:0] data_out;
 
reg t1_ow_buf;
//reg tr_start, trans, trans_buf, t1_ow_buf;
//reg [5:0] smod_cnt_r, smod_cnt_t;
//reg receive, receive_buf, rxd_buf, r_int;
//
reg [7:0] /*sbuf_rxd, sbuf_txd, */scon, pcon;
//reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
//reg [3:0] tr_count, re_count, re_count_buff;
 
 
reg        txd,
           trans,
           receive,
           tx_done,
           rx_done,
           rxd_r,
           shift_tr,
           shift_re;
reg [1:0]  rx_sam;
reg [3:0]  tr_count,
           re_count;
reg [7:0]  sbuf_rxd;
reg [11:0] sbuf_rxd_tmp;
reg [12:0] sbuf_txd;
 
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
wire ren, tb8, rb8, ri;
assign ren = scon[4];
assign tb8 = scon[3];
assign rb8 = scon[2];
assign ri  = scon[0];
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if (tx_done)
    scon[1] <= #1 1'b1;
  else if (!rx_done) begin
    if (scon[7:6]==2'b00) begin
      scon[0] <= #1 1'b1;
    end else if ((sbuf_rxd_tmp[11]) | !(scon[5])) begin
      scon[0] <= #1 1'b1;
      scon[2] <= #1 sbuf_rxd_tmp[11];
    end else
      scon[2] <= #1 sbuf_rxd_tmp[11];
  end
end
 
//
//power control register
//
wire smod;
assign smod = pcon[7];
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
 
//
//serial port buffer (transmit)
//
 
wire wr_sbuf;
assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd      <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans    <= #1 1'b0;
    sbuf_txd <= #1 11'h00;
    tx_done  <= #1 1'b0;
//
// start transmiting
//
  end else if (wr_sbuf) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        sbuf_txd <= #1 {3'b001, data_in};
      end
      2'b01: begin // mode 1
        sbuf_txd <= #1 {2'b01, data_in, 1'b0};
      end
      default: begin  // mode 2 and mode 3
        sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};
      end
    endcase
    trans    <= #1 1'b1;
    tr_count <= #1 4'd0;
    tx_done  <= #1 1'b0;
//
// transmiting
//
  end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0
  begin
    if (~|sbuf_txd[10:1]) begin
      trans   <= #1 1'b0;
      tx_done <= #1 1'b1;
    end else begin
      {sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
      tx_done         <= #1 1'b0;
    end
  end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3
    tr_count <= #1 tr_count + 4'd1;
    if (~|tr_count) begin
      if (~|sbuf_txd[10:0]) begin
        trans   <= #1 1'b0;
        tx_done <= #1 1'b1;
        txd <= #1 1'b1;
      end else begin
        {sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};
        tx_done         <= #1 1'b0;
      end
    end
  end else if (!trans) begin
    txd     <= #1 1'b1;
    tx_done <= #1 1'b0;
  end
end
 
//
//
reg sc_clk_tr, smod_clk_tr;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)
begin
  if (scon[7:6]==8'b10) begin //mode 2
    sc_clk_tr = 1'b1;
  end else if (tclk) begin //
    sc_clk_tr = brate2;
  end else begin //
    sc_clk_tr = !t1_ow_buf & t1_ow;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    smod_clk_tr <= #1 1'b0;
    shift_tr    <= #1 1'b0;
  end else if (sc_clk_tr) begin
    if (smod) begin
      shift_tr <= #1 1'b1;
    end else begin
      shift_tr    <= #1  smod_clk_tr;
      smod_clk_tr <= #1 !smod_clk_tr;
    end
  end else begin
    shift_tr <= #1 1'b0;
  end
end
 
/*
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 6'h0;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 6'h0;
//
// transmiting/
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (smod_cnt_t == 6'd12) begin
          if (tr_count==4'd8)
          begin
                  trans <= #1 1'b0;
                  txd <= #1 1'b1;
                end else begin
            txd <= #1 sbuf_txd[tr_count];
                  tr_count <= #1 tr_count + 4'b1;
                end
          smod_cnt_t <= #1 6'h0;
              end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
                if (((pcon[7]) &  (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
                begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
                    4'd9: trans <= #1 1'b0;
                    4'b1111: txd <= #1 1'b0; //start bit
                    default: txd <= #1 sbuf_txd[tr_count];
                  endcase
            tr_count <= #1 tr_count + 4'b1;
                  smod_cnt_t <= #1 6'h0;
                end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
              end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
            case (tr_count)
            4'd8: begin
                    txd <= #1 scon[3];
                  end
            4'd9: begin
                    txd <= #1 1'b1; //stop bit
                  end
            4'd10: begin
                    trans <= #1 1'b0;
                  end
 
                  default: begin
                    txd <= #1 sbuf_txd[tr_count];
                  end
                endcase
          tr_count <= #1 tr_count+1'b1;
                smod_cnt_t <= #1 6'h00;
              end else begin
          smod_cnt_t <= #1 smod_cnt_t + 6'h01;
              end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
      if (((pcon[7]) &  (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 6'h00;
          end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
*/
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    re_count     <= #1 4'd0;
    receive      <= #1 1'b0;
    sbuf_rxd     <= #1 8'h00;
    sbuf_rxd_tmp <= #1 12'd0;
    rx_done      <= #1 1'b1;
    rxd_r        <= #1 1'b1;
    rx_sam       <= #1 2'b00;
  end else if (!rx_done) begin
    receive <= #1 1'b0;
    rx_done <= #1 1'b1;
//    if (scon[7:6]==2'b00) begin
      sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];
//    end else begin
//      sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
//    end
  end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0
    {sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};
  end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3
    re_count <= #1 re_count + 4'd1;
    case (re_count)
      4'h7: rx_sam[0] <= #1 rxd;
      4'h8: rx_sam[1] <= #1 rxd;
      4'h9: begin
        {sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};
      end
    endcase
//
//start receiving
//
  end else if (scon[7:6]==2'b00) begin //start mode 0
    rx_done <= #1 1'b1;
    if (ren && !ri && !receive) begin
      receive      <= #1 1'b1;
      sbuf_rxd_tmp <= #1 10'h0ff;
    end
  end else if (ren & shift_re) begin
    rxd_r <= #1 rxd;
    rx_done <= #1 1'b1;
    re_count <= #1 4'h0;
    receive <= #1 (rxd_r & !rxd);
    sbuf_rxd_tmp <= #1 10'h1ff;
  end else
    rx_done <= #1 1'b1;
end
 
//
//
reg sc_clk_re, smod_clk_re;
always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)
begin
  if (scon[7:6]==8'b10) begin //mode 2
    sc_clk_re = 1'b1;
  end else if (rclk) begin //
    sc_clk_re = brate2;
  end else begin //
    sc_clk_re = !t1_ow_buf & t1_ow;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    smod_clk_re <= #1 1'b0;
    shift_re    <= #1 1'b0;
  end else if (sc_clk_re) begin
    if (smod) begin
      shift_re <= #1 1'b1;
    end else begin
      shift_re    <= #1  smod_clk_re;
      smod_clk_re <= #1 !smod_clk_re;
    end
  end else begin
    shift_re <= #1 1'b0;
  end
end
 
 
/*
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 6'h00;
    r_int <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (smod_cnt_r==6'd12) begin
          if (re_count==4'd8) begin
                  receive <= #1 1'b0;
                  r_int <= #1 1'b1;
                  sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              end else begin
            sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
                  r_int <= #1 1'b0;
                end
          re_count <= #1 re_count + 4'd1;
          smod_cnt_r <= #1 6'h00;
        end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if (((pcon[7]) &  (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
                begin
            r_int <= #1 1'b0;
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 6'h00;
            sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
            if ((re_count==4'd0) && (rxd))
              receive <= #1 1'b0;
 
                end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
              end else begin
              r_int <= #1 1'b1;
            if (re_count == 4'd10)
          begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
            receive <= #1 1'b0;
              r_int <= #1 1'b1;
          end else r_int <= #1 1'b0;
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
          r_int <= #1 1'b0;
            re_count <= #1 re_count + 4'd1;
          smod_cnt_r <= #1 6'h00;
          sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
          re_count <= #1 re_count + 4'd1;
              end else begin
          smod_cnt_r <= #1 smod_cnt_r + 6'h1;
                if (re_count==4'd11) begin
                  sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
                  r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
                  receive <= #1 1'b0;
                end else
                  r_int <= #1 1'b0;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if (((pcon[7]) &  (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
                begin
            sbuf_rxd_tmp[re_count] <= #1 rxd;
                  r_int <= #1 1'b0;
                re_count <= #1 re_count + 4'd1;
                  smod_cnt_r <= #1 6'h00;
                end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
              end else begin
          if (re_count==4'd11) begin
            sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
            receive <= #1 1'b0;
                  r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
                end else begin
            r_int <= #1 1'b0;
          end
              end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) && !(scon[0]) && !(r_int)) begin
          receive <= #1 1'b1;
          smod_cnt_r <= #1 6'h6;
        end
      end
      2'b10: begin
        if ((scon[4]) && !(rxd)) begin
          receive <= #1 1'b1;
          if (pcon[7])
            smod_cnt_r <= #1 6'd15;
          else smod_cnt_r <= #1 6'd31;
        end
      end
      default: begin
        if ((scon[4]) && (!rxd)) begin
          if (pcon[7])
            smod_cnt_r <= #1 6'd7;
          else smod_cnt_r <= #1 6'd15;
          receive <= #1 1'b1;
        end
      end
    endcase
 
    sbuf_rxd_tmp <= #1 11'd0;
    re_count <= #1 4'd0;
    r_int <= #1 1'b0;
  end
end
*/
 
//
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
//    trans_buf <= #1 1'b0;
//    receive_buf <= #1 1'b0;
    t1_ow_buf <= #1 1'b0;
//    rxd_buf <= #1 1'b0;
  end else begin
//    trans_buf <= #1 trans;
//    receive_buf <= #1 receive;
    t1_ow_buf <= #1 t1_ow;
//    rxd_buf <= #1 rxd;
  end
end
 
 
always  @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
end
 
/*
always @(posedge clk or posedge rst)
  if (rst)
    re_count_buff <= #1 4'h4;
  else re_count_buff <= #1 re_count;
*/
 
endmodule
 

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores serial interface ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// uart for 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	115	simont	`// Revision 1.10 2003/01/13 14:14:41 simont`
48			`// replace some modules`
49			`//`
50	82	simont	`// Revision 1.9 2002/09/30 17:33:59 simont`
51			`// prepared header`
52			`//`
53			`//`
54
55			`// synopsys translate_off`
56			`include "oc8051_timescale.v"
57			`// synopsys translate_on`
58
59			`include "oc8051_defines.v"
60
61	115	simont	`module oc8051_uart (rst, clk,`
62			`bit_in, data_in,`
63			`rd_addr, wr_addr,`
64			`bit_out, data_out,`
65			`wr, wr_bit,`
66			`rxd, txd,`
67			`intr,`
68			`brate2, t1_ow, pres_ow,`
69			`rclk, tclk);`
70	82	simont
71	115	simont	`input rst,`
72			`clk,`
73			`bit_in,`
74			`wr,`
75			`rxd,`
76			`wr_bit,`
77			`t1_ow,`
78			`brate2,`
79			`pres_ow,`
80			`rclk,`
81			`tclk;`
82			`input [7:0] rd_addr,`
83			`data_in,`
84			`wr_addr;`
85	82	simont
86	115	simont	`output txd,`
87			`intr,`
88			`bit_out;`
89	82	simont	`output [7:0] data_out;`
90
91	115	simont	`reg /txd, /bit_out;`
92	82	simont	`reg [7:0] data_out;`
93
94	115	simont	`reg t1_ow_buf;`
95			`//reg tr_start, trans, trans_buf, t1_ow_buf;`
96			`//reg [5:0] smod_cnt_r, smod_cnt_t;`
97			`//reg receive, receive_buf, rxd_buf, r_int;`
98	82	simont	`//`
99	115	simont	`reg [7:0] /sbuf_rxd, sbuf_txd, /scon, pcon;`
100			`//reg [10:0] sbuf_rxd_tmp;`
101	82	simont	`//`
102			`//tr_count trancive counter`
103			`//re_count receive counter`
104	115	simont	`//reg [3:0] tr_count, re_count, re_count_buff;`
105	82	simont
106
107	115	simont	`reg txd,`
108			`trans,`
109			`receive,`
110			`tx_done,`
111			`rx_done,`
112			`rxd_r,`
113			`shift_tr,`
114			`shift_re;`
115			`reg [1:0] rx_sam;`
116			`reg [3:0] tr_count,`
117			`re_count;`
118			`reg [7:0] sbuf_rxd;`
119			`reg [11:0] sbuf_rxd_tmp;`
120			`reg [12:0] sbuf_txd;`
121
122
123	82	simont	`assign intr = scon[1] \| scon [0];`
124
125			`//`
126			`//serial port control register`
127			`//`
128	115	simont	`wire ren, tb8, rb8, ri;`
129			`assign ren = scon[4];`
130			`assign tb8 = scon[3];`
131			`assign rb8 = scon[2];`
132			`assign ri = scon[0];`
133
134	82	simont	`always @(posedge clk or posedge rst)`
135			`begin`
136			`if (rst)`
137			scon <= #1 `OC8051_RST_SCON;
138			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
139			`scon <= #1 data_in;`
140			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
141			`scon[wr_addr[2:0]] <= #1 bit_in;`
142	115	simont	`else if (tx_done)`
143	82	simont	`scon[1] <= #1 1'b1;`
144	115	simont	`else if (!rx_done) begin`
145			`if (scon[7:6]==2'b00) begin`
146			`scon[0] <= #1 1'b1;`
147			`end else if ((sbuf_rxd_tmp[11]) \| !(scon[5])) begin`
148			`scon[0] <= #1 1'b1;`
149			`scon[2] <= #1 sbuf_rxd_tmp[11];`
150			`end else`
151			`scon[2] <= #1 sbuf_rxd_tmp[11];`
152			`end`
153			`end`
154
155			`//`
156			`//power control register`
157			`//`
158			`wire smod;`
159			`assign smod = pcon[7];`
160			`always @(posedge clk or posedge rst)`
161			`begin`
162			`if (rst)`
163			`begin`
164			pcon <= #1 `OC8051_RST_PCON;
165			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
166			`pcon <= #1 data_in;`
167			`end`
168
169
170			`//`
171			`//serial port buffer (transmit)`
172			`//`
173
174			`wire wr_sbuf;`
175			assign wr_sbuf = (wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit);
176
177			`always @(posedge clk or posedge rst)`
178			`begin`
179			`if (rst) begin`
180			`txd <= #1 1'b1;`
181			`tr_count <= #1 4'd0;`
182			`trans <= #1 1'b0;`
183			`sbuf_txd <= #1 11'h00;`
184			`tx_done <= #1 1'b0;`
185			`//`
186			`// start transmiting`
187			`//`
188			`end else if (wr_sbuf) begin`
189	82	simont	`case (scon[7:6])`
190	115	simont	`2'b00: begin // mode 0`
191			`sbuf_txd <= #1 {3'b001, data_in};`
192	82	simont	`end`
193	115	simont	`2'b01: begin // mode 1`
194			`sbuf_txd <= #1 {2'b01, data_in, 1'b0};`
195			`end`
196			`default: begin // mode 2 and mode 3`
197			`sbuf_txd <= #1 {1'b1, tb8, data_in, 1'b0};`
198			`end`
199	82	simont	`endcase`
200	115	simont	`trans <= #1 1'b1;`
201			`tr_count <= #1 4'd0;`
202			`tx_done <= #1 1'b0;`
203			`//`
204			`// transmiting`
205			`//`
206			`end else if (trans & (scon[7:6] == 2'b00) & pres_ow) // mode 0`
207			`begin`
208			`if (~\|sbuf_txd[10:1]) begin`
209			`trans <= #1 1'b0;`
210			`tx_done <= #1 1'b1;`
211			`end else begin`
212			`{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};`
213			`tx_done <= #1 1'b0;`
214			`end`
215			`end else if (trans & (scon[7:6] != 2'b00) & shift_tr) begin // mode 1, 2, 3`
216			`tr_count <= #1 tr_count + 4'd1;`
217			`if (~\|tr_count) begin`
218			`if (~\|sbuf_txd[10:0]) begin`
219			`trans <= #1 1'b0;`
220			`tx_done <= #1 1'b1;`
221			`txd <= #1 1'b1;`
222			`end else begin`
223			`{sbuf_txd, txd} <= #1 {1'b0, sbuf_txd};`
224			`tx_done <= #1 1'b0;`
225			`end`
226			`end`
227			`end else if (!trans) begin`
228			`txd <= #1 1'b1;`
229			`tx_done <= #1 1'b0;`
230	82	simont	`end`
231			`end`
232
233			`//`
234			`//`
235	115	simont	`reg sc_clk_tr, smod_clk_tr;`
236			`always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or tclk)`
237			`begin`
238			`if (scon[7:6]==8'b10) begin //mode 2`
239			`sc_clk_tr = 1'b1;`
240			`end else if (tclk) begin //`
241			`sc_clk_tr = brate2;`
242			`end else begin //`
243			`sc_clk_tr = !t1_ow_buf & t1_ow;`
244			`end`
245			`end`
246
247	82	simont	`always @(posedge clk or posedge rst)`
248			`begin`
249			`if (rst) begin`
250	115	simont	`smod_clk_tr <= #1 1'b0;`
251			`shift_tr <= #1 1'b0;`
252			`end else if (sc_clk_tr) begin`
253			`if (smod) begin`
254			`shift_tr <= #1 1'b1;`
255			`end else begin`
256			`shift_tr <= #1 smod_clk_tr;`
257			`smod_clk_tr <= #1 !smod_clk_tr;`
258			`end`
259			`end else begin`
260			`shift_tr <= #1 1'b0;`
261			`end`
262	82	simont	`end`
263
264	115	simont	`/*`
265	82	simont	`//`
266			`// transmit`
267			`//`
268			`always @(posedge clk or posedge rst)`
269			`begin`
270			`if (rst) begin`
271			`txd <= #1 1'b1;`
272			`tr_count <= #1 4'd0;`
273			`trans <= #1 1'b0;`
274			`smod_cnt_t <= #1 6'h0;`
275			`//`
276			`// start transmiting`
277			`//`
278			`end else if (tr_start) begin`
279			`case (scon[7:6])`
280			`2'b00: begin // mode 0`
281			`txd <= #1 sbuf_txd[0];`
282			`tr_count <= #1 4'd1;`
283			`end`
284			`2'b10: begin`
285			`txd <= #1 1'b0;`
286			`tr_count <= #1 4'd0;`
287			`end`
288			`default: begin // mode 1 and mode 3`
289			`tr_count <= #1 4'b1111;`
290			`end`
291			`endcase`
292			`trans <= #1 1'b1;`
293			`smod_cnt_t <= #1 6'h0;`
294			`//`
295			`// transmiting/`
296			`//`
297			`end else if (trans)`
298			`begin`
299			`case (scon[7:6])`
300			`2'b00: begin //mode 0`
301			`if (smod_cnt_t == 6'd12) begin`
302			`if (tr_count==4'd8)`
303			`begin`
304			`trans <= #1 1'b0;`
305			`txd <= #1 1'b1;`
306			`end else begin`
307			`txd <= #1 sbuf_txd[tr_count];`
308			`tr_count <= #1 tr_count + 4'b1;`
309			`end`
310			`smod_cnt_t <= #1 6'h0;`
311			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
312			`end`
313			`2'b01: begin // mode 1`
314			`if ((t1_ow) & !(t1_ow_buf))`
315			`begin`
316			`if (((pcon[7]) & (smod_cnt_t == 6'd15))\| (!(pcon[7]) & (smod_cnt_t==6'd31)))`
317			`begin`
318			`case (tr_count)`
319			`4'd8: txd <= #1 1'b1; // stop bit`
320			`4'd9: trans <= #1 1'b0;`
321			`4'b1111: txd <= #1 1'b0; //start bit`
322			`default: txd <= #1 sbuf_txd[tr_count];`
323			`endcase`
324			`tr_count <= #1 tr_count + 4'b1;`
325			`smod_cnt_t <= #1 6'h0;`
326			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
327			`end`
328			`end`
329			`2'b10: begin // mode 2`
330			`//`
331			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
332			`//`
333			`if (((pcon[7]) & (smod_cnt_t==6'd31)) \| (!(pcon[7]) & (smod_cnt_t==6'd63))) begin`
334			`case (tr_count)`
335			`4'd8: begin`
336			`txd <= #1 scon[3];`
337			`end`
338			`4'd9: begin`
339			`txd <= #1 1'b1; //stop bit`
340			`end`
341			`4'd10: begin`
342			`trans <= #1 1'b0;`
343			`end`
344
345			`default: begin`
346			`txd <= #1 sbuf_txd[tr_count];`
347			`end`
348			`endcase`
349			`tr_count <= #1 tr_count+1'b1;`
350			`smod_cnt_t <= #1 6'h00;`
351			`end else begin`
352			`smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
353			`end`
354			`end`
355			`default: begin // mode 3`
356			`if ((t1_ow) & !(t1_ow_buf))`
357			`begin`
358			`if (((pcon[7]) & (smod_cnt_t == 6'd15))\| (!(pcon[7]) & (smod_cnt_t==6'd31)))`
359			`begin`
360			`case (tr_count)`
361			`4'd8: begin`
362			`txd <= #1 scon[3];`
363			`end`
364			`4'd9: begin`
365			`txd <= #1 1'b1; //stop bit`
366			`end`
367			`4'd10: begin`
368			`trans <= #1 1'b0;`
369			`end`
370			`4'b1111: txd <= #1 1'b0; //start bit`
371			`default: begin`
372			`txd <= #1 sbuf_txd[tr_count];`
373			`end`
374			`endcase`
375			`tr_count <= #1 tr_count+1'b1;`
376			`smod_cnt_t <= #1 6'h00;`
377			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
378			`end`
379			`end`
380			`endcase`
381			`end else`
382			`txd <= #1 1'b1;`
383			`end`
384	115	simont	`*/`
385	82	simont
386			`//`
387	115	simont	`//serial port buffer (receive)`
388	82	simont	`//`
389			`always @(posedge clk or posedge rst)`
390			`begin`
391	115	simont	`if (rst) begin`
392			`re_count <= #1 4'd0;`
393			`receive <= #1 1'b0;`
394			`sbuf_rxd <= #1 8'h00;`
395			`sbuf_rxd_tmp <= #1 12'd0;`
396			`rx_done <= #1 1'b1;`
397			`rxd_r <= #1 1'b1;`
398			`rx_sam <= #1 2'b00;`
399			`end else if (!rx_done) begin`
400			`receive <= #1 1'b0;`
401			`rx_done <= #1 1'b1;`
402			`// if (scon[7:6]==2'b00) begin`
403			`sbuf_rxd <= #1 sbuf_rxd_tmp[10:3];`
404			`// end else begin`
405			`// sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
406			`// end`
407			`end else if (receive & (scon[7:6]==2'b00) & pres_ow) begin //mode 0`
408			`{sbuf_rxd_tmp, rx_done} <= #1 {rxd, sbuf_rxd_tmp};`
409			`end else if (receive & (scon[7:6]!=2'b00) & shift_re) begin //mode 1, 2, 3`
410			`re_count <= #1 re_count + 4'd1;`
411			`case (re_count)`
412			`4'h7: rx_sam[0] <= #1 rxd;`
413			`4'h8: rx_sam[1] <= #1 rxd;`
414			`4'h9: begin`
415			`{sbuf_rxd_tmp, rx_done} <= #1 {(rxd==rx_sam[0] ? rxd : rx_sam[1]), sbuf_rxd_tmp};`
416			`end`
417			`endcase`
418			`//`
419			`//start receiving`
420			`//`
421			`end else if (scon[7:6]==2'b00) begin //start mode 0`
422			`rx_done <= #1 1'b1;`
423			`if (ren && !ri && !receive) begin`
424			`receive <= #1 1'b1;`
425			`sbuf_rxd_tmp <= #1 10'h0ff;`
426			`end`
427			`end else if (ren & shift_re) begin`
428			`rxd_r <= #1 rxd;`
429			`rx_done <= #1 1'b1;`
430			`re_count <= #1 4'h0;`
431			`receive <= #1 (rxd_r & !rxd);`
432			`sbuf_rxd_tmp <= #1 10'h1ff;`
433			`end else`
434			`rx_done <= #1 1'b1;`
435	82	simont	`end`
436
437			`//`
438			`//`
439	115	simont	`reg sc_clk_re, smod_clk_re;`
440			`always @(brate2 or t1_ow or t1_ow_buf or scon[7:6] or rclk)`
441			`begin`
442			`if (scon[7:6]==8'b10) begin //mode 2`
443			`sc_clk_re = 1'b1;`
444			`end else if (rclk) begin //`
445			`sc_clk_re = brate2;`
446			`end else begin //`
447			`sc_clk_re = !t1_ow_buf & t1_ow;`
448			`end`
449			`end`
450
451	82	simont	`always @(posedge clk or posedge rst)`
452			`begin`
453			`if (rst) begin`
454	115	simont	`smod_clk_re <= #1 1'b0;`
455			`shift_re <= #1 1'b0;`
456			`end else if (sc_clk_re) begin`
457			`if (smod) begin`
458			`shift_re <= #1 1'b1;`
459			`end else begin`
460			`shift_re <= #1 smod_clk_re;`
461			`smod_clk_re <= #1 !smod_clk_re;`
462			`end`
463			`end else begin`
464			`shift_re <= #1 1'b0;`
465			`end`
466			`end`
467
468
469			`/*`
470			`always @(posedge clk or posedge rst)`
471			`begin`
472			`if (rst) begin`
473	82	simont	`re_count <= #1 4'd0;`
474			`receive <= #1 1'b0;`
475			`sbuf_rxd <= #1 8'h00;`
476			`sbuf_rxd_tmp <= #1 11'd0;`
477			`smod_cnt_r <= #1 6'h00;`
478			`r_int <= #1 1'b0;`
479			`end else if (receive) begin`
480			`case (scon[7:6])`
481			`2'b00: begin // mode 0`
482			`if (smod_cnt_r==6'd12) begin`
483			`if (re_count==4'd8) begin`
484			`receive <= #1 1'b0;`
485			`r_int <= #1 1'b1;`
486			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
487			`end else begin`
488			`sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;`
489			`r_int <= #1 1'b0;`
490			`end`
491			`re_count <= #1 re_count + 4'd1;`
492			`smod_cnt_r <= #1 6'h00;`
493			`end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;`
494			`end`
495			`2'b01: begin // mode 1`
496			`if ((t1_ow) & !(t1_ow_buf))`
497			`begin`
498			`if (((pcon[7]) & (smod_cnt_r == 6'd15))\| (!(pcon[7]) & (smod_cnt_r==6'd31)))`
499			`begin`
500			`r_int <= #1 1'b0;`

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