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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 17

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// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
                   rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;
reg receive, receive_buf, rxd_buf, r_int;
//
// mode 2 counter
reg [2:0] mode2_count;
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
reg [3:0] tr_count, re_count;
 
//
// sam_cnt      sample counter
reg [2:0] sam_cnt, sample;
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if ((trans_buf) & !(trans))
    scon[1] <= #1 1'b1;
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
    case (scon[7:6])
      2'b00: scon[0] <= #1 1'b1;
      default: begin
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
        scon[2] <= #1 sbuf_rxd_tmp[9];
      end
    endcase
  end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= #1 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
  end else tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 1'b0;
    mode2_count <= #1 3'b000;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 1'b0;
    mode2_count <= #1 3'b000;
//
// transmiting
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (tr_count==4'd8)
        begin
          trans <= #1 1'b0;
          txd <= #1 1'b1;
        end else begin
          txd <= #1 sbuf_txd[tr_count];
          tr_count <= #1 tr_count + 4'b1;
        end
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
              4'd9: trans <= #1 1'b0;
              4'b1111: txd <= #1 1'b0; //start bit
              default: txd <= #1 sbuf_txd[tr_count];
            endcase
            tr_count <= #1 tr_count + 4'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (mode2_count==3'b011)) | (!(pcon[7]) & (mode2_count==3'b101))) begin
          case (tr_count)
            4'd8: begin
              txd <= #1 scon[3];
            end
            4'd9: begin
              txd <= #1 1'b1; //stop bit
              trans <= #1 1'b0;
            end
            default: begin
              txd <= #1 sbuf_txd[tr_count];
            end
          endcase
          tr_count <= #1 tr_count+1'b1;
          mode2_count <= #1 3'd0;
        end else begin
          mode2_count <= #1 mode2_count + 3'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_t))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 1'b0;
          end else smod_cnt_t <= #1 1'b1;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 1'b0;
    r_int <= #1 1'b0;
    re_start <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (re_count==4'd8) begin
          receive <= #1 1'b0;
          r_int <= #1 1'b1;
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
        end else begin
          sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
          r_int <= #1 1'b0;
        end
        re_count <= #1 re_count + 4'd1;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
            r_int <= #1 1'b0;
 
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          if (sam_cnt==3'b011) begin
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
            if (re_count == 4'd9)
            begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 1'b1;
            end else r_int <= #1 1'b0;
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt +1'b1;
            r_int <= #1 1'b0;
          end
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (sam_cnt==3'b100)) | (!(pcon[7]) & (sam_cnt==3'b110))) begin
          if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
              receive <= #1 1'b0;
          end else begin
            sam_cnt <= #1 3'b001;
            sample[0] <= #1 rxd;
            r_int <= #1 1'b0;
          end
    re_count <= #1 re_count + 4'd1;
        end else begin
          r_int <= #1 1'b0;
 
          if (sam_cnt==3'b011) begin
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          end else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
          end
    sam_cnt <= #1 sam_cnt + 1'b1;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if ((pcon[7]) | (smod_cnt_r))
          begin
            sam_cnt <= #1 3'b000;
 
            if (re_count==4'd11) begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
              receive <= #1 1'b0;
              r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
            end else begin
              sam_cnt <= #1 3'b000;
              r_int <= #1 1'b0;
            end
 
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 1'b0;
          end else smod_cnt_r <= #1 1'b1;
        end else begin
          r_int <= #1 1'b0;
          if (sam_cnt==3'b011)
            if ((sample[0] ^ sample[1]) | (sample[0] ^ sample[2]))
              sbuf_rxd_tmp[re_count] <= #1 sample[0];
            else
              sbuf_rxd_tmp[re_count] <= #1 sample[1];
          else begin
            sample[sam_cnt[1:0]] <= #1 rxd;
            sam_cnt <= #1 sam_cnt + 1'b1;
          end
        end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) & !(scon[0]) & !(r_int)) begin
          receive <= #1 1'b1;
        end
      end
      2'b10: begin
        if ((rxd_buf) & !(rxd)) begin
          receive <= #1 1'b1;
        end
      end
      default: begin
        if ((rxd_buf) & !(rxd)) begin
          re_start <= #1 1'b1;
        end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin
          re_start <= #1 1'b0;
          receive <= 1'b1;
        end
      end
    endcase
 
    sample <= #1 3'b000;
    sam_cnt <= #1 3'b000;
    re_count <= #1 4'd0;
    sbuf_rxd_tmp <= #1 11'd0;
    r_int <= #1 1'b0;
  end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    trans_buf <= #1 1'b0;
    receive_buf <= #1 1'b0;
    t1_ow_buf <= #1 1'b0;
    rxd_buf <= #1 1'b0;
  end else begin
    trans_buf <= #1 trans;
    receive_buf <= #1 receive;
    t1_ow_buf <= #1 t1_ow;
    rxd_buf <= #1 rxd;
  end
end
 
always  @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
end
 
endmodule

Line No.	Rev	Author	Line
1	8	markom	`// synopsys translate_off`
2			`include "oc8051_timescale.v"
3			`// synopsys translate_on`
4
5			`include "oc8051_defines.v"
6
7	2	simont	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
8	4	markom	`rxd, txd, intr, t1_ow);`
9	2	simont
10			`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
11			`input [7:0] rd_addr, data_in, wr_addr;`
12
13	4	markom	`output txd, intr, bit_out;`
14	2	simont	`output [7:0] data_out;`
15
16			`reg txd, bit_out;`
17			`reg [7:0] data_out;`
18
19			`reg tr_start, trans, trans_buf, t1_ow_buf, smod_cnt_t, smod_cnt_r, re_start;`
20			`reg receive, receive_buf, rxd_buf, r_int;`
21			`//`
22			`// mode 2 counter`
23			`reg [2:0] mode2_count;`
24			`reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;`
25			`reg [10:0] sbuf_rxd_tmp;`
26			`//`
27			`//tr_count trancive counter`
28			`//re_count receive counter`
29			`reg [3:0] tr_count, re_count;`
30
31			`//`
32			`// sam_cnt sample counter`
33			`reg [2:0] sam_cnt, sample;`
34
35	4	markom	`assign intr = scon[1] \| scon [0];`
36	2	simont
37			`//`
38			`//serial port control register`
39			`//`
40			`always @(posedge clk or posedge rst)`
41			`begin`
42			`if (rst)`
43			scon <= #1 `OC8051_RST_SCON;
44			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
45			`scon <= #1 data_in;`
46			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
47			`scon[wr_addr[2:0]] <= #1 bit_in;`
48			`else if ((trans_buf) & !(trans))`
49			`scon[1] <= #1 1'b1;`
50			`else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin`
51			`case (scon[7:6])`
52			`2'b00: scon[0] <= #1 1'b1;`
53			`default: begin`
54			`if ((sbuf_rxd_tmp[9]) \| !(scon[5])) scon[0] <= #1 1'b1;`
55			`scon[2] <= #1 sbuf_rxd_tmp[9];`
56			`end`
57			`endcase`
58			`end`
59
60			`end`
61
62			`//`
63			`//serial port buffer (transmit)`
64			`//`
65			`always @(posedge clk or posedge rst)`
66			`begin`
67			`if (rst) begin`
68			sbuf_txd <= #1 `OC8051_RST_SBUF;
69	4	markom	`tr_start <= #1 1'b0;`
70	2	simont	end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
71			`sbuf_txd <= #1 data_in;`
72			`tr_start <= #1 1'b1;`
73	5	markom	`end else tr_start <= #1 1'b0;`
74	2	simont	`end`
75
76			`//`
77			`// transmit`
78			`//`
79			`always @(posedge clk or posedge rst)`
80			`begin`
81			`if (rst) begin`
82			`txd <= #1 1'b1;`
83			`tr_count <= #1 4'd0;`
84			`trans <= #1 1'b0;`
85			`smod_cnt_t <= #1 1'b0;`
86	17	simont	`mode2_count <= #1 3'b000;`
87	2	simont	`//`
88			`// start transmiting`
89			`//`
90			`end else if (tr_start) begin`
91			`case (scon[7:6])`
92			`2'b00: begin // mode 0`
93			`txd <= #1 sbuf_txd[0];`
94			`tr_count <= #1 4'd1;`
95			`end`
96			`2'b10: begin`
97			`txd <= #1 1'b0;`
98			`tr_count <= #1 4'd0;`
99			`end`
100			`default: begin // mode 1 and mode 3`
101			`tr_count <= #1 4'b1111;`
102			`end`
103			`endcase`
104			`trans <= #1 1'b1;`
105			`smod_cnt_t <= #1 1'b0;`
106			`mode2_count <= #1 3'b000;`
107			`//`
108			`// transmiting`
109			`//`
110			`end else if (trans)`
111			`begin`
112			`case (scon[7:6])`
113			`2'b00: begin //mode 0`
114	4	markom	`if (tr_count==4'd8)`
115	2	simont	`begin`
116			`trans <= #1 1'b0;`
117			`txd <= #1 1'b1;`
118			`end else begin`
119			`txd <= #1 sbuf_txd[tr_count];`
120	4	markom	`tr_count <= #1 tr_count + 4'b1;`
121	2	simont	`end`
122			`end`
123			`2'b01: begin // mode 1`
124			`if ((t1_ow) & !(t1_ow_buf))`
125			`begin`
126			`if ((pcon[7]) \| (smod_cnt_t))`
127			`begin`
128			`case (tr_count)`
129			`4'd8: txd <= #1 1'b1; // stop bit`
130			`4'd9: trans <= #1 1'b0;`
131			`4'b1111: txd <= #1 1'b0; //start bit`
132			`default: txd <= #1 sbuf_txd[tr_count];`
133			`endcase`
134	4	markom	`tr_count <= #1 tr_count + 4'b1;`
135	2	simont	`smod_cnt_t <= #1 1'b0;`
136			`end else smod_cnt_t <= #1 1'b1;`
137			`end`
138			`end`
139			`2'b10: begin // mode 2`
140			`//`
141			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
142			`//`
143			`if (((pcon[7]) & (mode2_count==3'b011)) \| (!(pcon[7]) & (mode2_count==3'b101))) begin`
144			`case (tr_count)`
145			`4'd8: begin`
146			`txd <= #1 scon[3];`
147			`end`
148			`4'd9: begin`
149			`txd <= #1 1'b1; //stop bit`
150			`trans <= #1 1'b0;`
151			`end`
152			`default: begin`
153			`txd <= #1 sbuf_txd[tr_count];`
154			`end`
155			`endcase`
156			`tr_count <= #1 tr_count+1'b1;`
157	4	markom	`mode2_count <= #1 3'd0;`
158	2	simont	`end else begin`
159	4	markom	`mode2_count <= #1 mode2_count + 3'b1;`
160	2	simont	`end`
161			`end`
162			`default: begin // mode 3`
163			`if ((t1_ow) & !(t1_ow_buf))`
164			`begin`
165			`if ((pcon[7]) \| (smod_cnt_t))`
166			`begin`
167			`case (tr_count)`
168			`4'd8: begin`
169			`txd <= #1 scon[3];`
170			`end`
171			`4'd9: begin`
172			`txd <= #1 1'b1; //stop bit`
173			`end`
174			`4'd10: begin`
175			`trans <= #1 1'b0;`
176			`end`
177			`4'b1111: txd <= #1 1'b0; //start bit`
178			`default: begin`
179			`txd <= #1 sbuf_txd[tr_count];`
180			`end`
181			`endcase`
182			`tr_count <= #1 tr_count+1'b1;`
183			`smod_cnt_t <= #1 1'b0;`
184			`end else smod_cnt_t <= #1 1'b1;`
185			`end`
186			`end`
187			`endcase`
188			`end else`
189			`txd <= #1 1'b1;`
190			`end`
191
192			`//`
193			`//power control register`
194			`//`
195			`always @(posedge clk or posedge rst)`
196			`begin`
197			`if (rst)`
198			`begin`
199			pcon <= #1 `OC8051_RST_PCON;
200			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
201			`pcon <= #1 data_in;`
202			`end`
203
204			`//`
205	4	markom	`//serial port buffer (receive)`
206	2	simont	`//`
207			`always @(posedge clk or posedge rst)`
208			`begin`
209			`if (rst) begin`
210			`sample <= #1 3'b000;`
211			`sam_cnt <= #1 3'b000;`
212			`re_count <= #1 4'd0;`
213			`receive <= #1 1'b0;`
214			`sbuf_rxd <= #1 8'h00;`
215			`sbuf_rxd_tmp <= #1 11'd0;`
216			`smod_cnt_r <= #1 1'b0;`
217			`r_int <= #1 1'b0;`
218			`re_start <= #1 1'b0;`
219			`end else if (receive) begin`
220			`case (scon[7:6])`
221			`2'b00: begin // mode 0`
222			`if (re_count==4'd8) begin`
223			`receive <= #1 1'b0;`
224			`r_int <= #1 1'b1;`
225			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
226			`end else begin`
227	5	markom	`sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;`
228	2	simont	`r_int <= #1 1'b0;`
229			`end`
230	5	markom	`re_count <= #1 re_count + 4'd1;`
231	2	simont	`end`
232			`2'b01: begin // mode 1`
233			`if ((t1_ow) & !(t1_ow_buf))`
234			`begin`
235			`if ((pcon[7]) \| (smod_cnt_r))`
236			`begin`
237			`sam_cnt <= #1 3'b000;`
238			`r_int <= #1 1'b0;`
239
240	5	markom	`re_count <= #1 re_count + 4'd1;`
241	2	simont	`smod_cnt_r <= #1 1'b0;`
242			`end else smod_cnt_r <= #1 1'b1;`
243			`end else begin`
244			`if (sam_cnt==3'b011) begin`
245	10	markom	`if ((sample[0] ^ sample[1]) \| (sample[0] ^ sample[2]))`
246	2	simont	`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
247			`else`
248			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
249	5	markom	`if (re_count == 4'd9)`
250	2	simont	`begin`
251			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
252			`receive <= #1 1'b0;`
253			`r_int <= #1 1'b1;`
254			`end else r_int <= #1 1'b0;`
255			`end else begin`
256			`sample[sam_cnt[1:0]] <= #1 rxd;`
257			`sam_cnt <= #1 sam_cnt +1'b1;`
258			`r_int <= #1 1'b0;`
259			`end`
260			`end`
261			`end`
262			`2'b10: begin // mode 2`
263			`if (((pcon[7]) & (sam_cnt==3'b100)) \| (!(pcon[7]) & (sam_cnt==3'b110))) begin`
264			`if (re_count==4'd11) begin`
265			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
266			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
267			`receive <= #1 1'b0;`
268			`end else begin`
269			`sam_cnt <= #1 3'b001;`
270			`sample[0] <= #1 rxd;`
271			`r_int <= #1 1'b0;`
272			`end`
273	5	markom	`re_count <= #1 re_count + 4'd1;`
274	2	simont	`end else begin`
275			`r_int <= #1 1'b0;`
276
277			`if (sam_cnt==3'b011) begin`
278	10	markom	`if ((sample[0] ^ sample[1]) \| (sample[0] ^ sample[2]))`
279	2	simont	`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
280			`else`
281			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
282			`end else begin`
283			`sample[sam_cnt[1:0]] <= #1 rxd;`
284			`end`
285			`sam_cnt <= #1 sam_cnt + 1'b1;`
286			`end`
287			`end`
288			`default: begin // mode 3`
289			`if ((t1_ow) & !(t1_ow_buf))`
290			`begin`
291			`if ((pcon[7]) \| (smod_cnt_r))`
292			`begin`
293			`sam_cnt <= #1 3'b000;`
294
295			`if (re_count==4'd11) begin`
296			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
297			`receive <= #1 1'b0;`
298			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
299			`end else begin`
300			`sam_cnt <= #1 3'b000;`
301			`r_int <= #1 1'b0;`
302			`end`
303
304	5	markom	`re_count <= #1 re_count + 4'd1;`
305	2	simont	`smod_cnt_r <= #1 1'b0;`
306			`end else smod_cnt_r <= #1 1'b1;`
307			`end else begin`
308			`r_int <= #1 1'b0;`
309			`if (sam_cnt==3'b011)`
310	10	markom	`if ((sample[0] ^ sample[1]) \| (sample[0] ^ sample[2]))`
311	2	simont	`sbuf_rxd_tmp[re_count] <= #1 sample[0];`
312			`else`
313			`sbuf_rxd_tmp[re_count] <= #1 sample[1];`
314			`else begin`
315			`sample[sam_cnt[1:0]] <= #1 rxd;`
316	10	markom	`sam_cnt <= #1 sam_cnt + 1'b1;`
317	2	simont	`end`
318			`end`
319			`end`
320			`endcase`
321			`end else begin`
322			`case (scon[7:6])`
323			`2'b00: begin`
324			`if ((scon[4]) & !(scon[0]) & !(r_int)) begin`
325			`receive <= #1 1'b1;`
326			`end`
327			`end`
328			`2'b10: begin`
329			`if ((rxd_buf) & !(rxd)) begin`
330			`receive <= #1 1'b1;`
331			`end`
332			`end`
333			`default: begin`
334			`if ((rxd_buf) & !(rxd)) begin`
335			`re_start <= #1 1'b1;`
336			`end else if ((re_start) & (t1_ow) & !(t1_ow_buf)) begin`
337			`re_start <= #1 1'b0;`
338			`receive <= 1'b1;`
339			`end`
340			`end`
341			`endcase`
342
343			`sample <= #1 3'b000;`
344			`sam_cnt <= #1 3'b000;`
345			`re_count <= #1 4'd0;`
346			`sbuf_rxd_tmp <= #1 11'd0;`
347			`r_int <= #1 1'b0;`
348			`end`
349			`end`
350
351			`//`
352			`//`
353			`//`
354	4	markom	`always @(posedge clk or posedge rst)`
355	2	simont	`begin`
356	4	markom	`if (rst) data_out <= #1 8'h0;`
357			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) \|
358	2	simont	(wr_addr==`OC8051_SFR_SCON))) begin
359			`data_out <= #1 data_in;`
360			`end else begin`
361			`case (rd_addr)`
362			`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
363			`OC8051_SFR_PCON: data_out <= #1 pcon;
364			`default: data_out <= #1 scon;`
365			`endcase`
366			`end`
367			`end`
368
369
370	4	markom	`always @(posedge clk or posedge rst)`
371	2	simont	`begin`
372	4	markom	`if (rst) begin`
373			`trans_buf <= #1 1'b0;`
374			`receive_buf <= #1 1'b0;`
375			`t1_ow_buf <= #1 1'b0;`
376			`rxd_buf <= #1 1'b0;`
377			`end else begin`
378			`trans_buf <= #1 trans;`
379			`receive_buf <= #1 receive;`
380			`t1_ow_buf <= #1 t1_ow;`
381			`rxd_buf <= #1 rxd;`
382			`end`
383	2	simont	`end`
384
385	4	markom	`always @(posedge clk or posedge rst)`
386	2	simont	`begin`
387	4	markom	`if (rst) bit_out <= #1 1'b0;`
388			else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
389	2	simont	`bit_out <= #1 bit_in;`
390			`end else`
391			`bit_out <= #1 scon[rd_addr[2:0]];`
392			`end`
393
394			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 17