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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 30

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// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,
                   rxd, txd, intr, t1_ow);
 
input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;
input [7:0] rd_addr, data_in, wr_addr;
 
output txd, intr, bit_out;
output [7:0] data_out;
 
reg txd, bit_out;
reg [7:0] data_out;
 
reg tr_start, trans, trans_buf, t1_ow_buf;
reg [5:0] smod_cnt_r, smod_cnt_t;
reg receive, receive_buf, rxd_buf, r_int;
//
reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;
reg [10:0] sbuf_rxd_tmp;
//
//tr_count      trancive counter
//re_count      receive counter
reg [3:0] tr_count, re_count, re_count_buff;
 
 
assign intr = scon[1] | scon [0];
 
//
//serial port control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
    scon <= #1 `OC8051_RST_SCON;
  else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
    scon <= #1 data_in;
  else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
    scon[wr_addr[2:0]] <= #1 bit_in;
  else if ((trans_buf) & !(trans))
    scon[1] <= #1 1'b1;
  else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin
    case (scon[7:6])
      2'b00: scon[0] <= #1 1'b1;
      default: begin
        if ((sbuf_rxd_tmp[9]) | !(scon[5])) scon[0] <= #1 1'b1;
        scon[2] <= #1 sbuf_rxd_tmp[9];
      end
    endcase
  end
 
end
 
//
//serial port buffer (transmit)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    sbuf_txd <= #1 `OC8051_RST_SBUF;
    tr_start <= #1 1'b0;
  end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
    sbuf_txd <= #1 data_in;
    tr_start <= #1 1'b1;
  end else tr_start <= #1 1'b0;
end
 
//
// transmit
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    txd <= #1 1'b1;
    tr_count <= #1 4'd0;
    trans <= #1 1'b0;
    smod_cnt_t <= #1 6'h0;
//
// start transmiting
//
  end else if (tr_start) begin
    case (scon[7:6])
      2'b00: begin  // mode 0
        txd <= #1 sbuf_txd[0];
        tr_count <= #1 4'd1;
      end
      2'b10: begin
        txd <= #1 1'b0;
        tr_count <= #1 4'd0;
      end
      default: begin  // mode 1 and mode 3
        tr_count <= #1 4'b1111;
      end
    endcase
    trans <= #1 1'b1;
    smod_cnt_t <= #1 6'h0;
//
// transmiting/
//
  end else if (trans)
  begin
    case (scon[7:6])
      2'b00: begin //mode 0
        if (tr_count==4'd8)
        begin
          trans <= #1 1'b0;
          txd <= #1 1'b1;
        end else begin
          txd <= #1 sbuf_txd[tr_count];
          tr_count <= #1 tr_count + 4'b1;
        end
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
                if (((pcon[7]) &  (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
                begin
            case (tr_count)
              4'd8: txd <= #1 1'b1;  // stop bit
                    4'd9: trans <= #1 1'b0;
                    4'b1111: txd <= #1 1'b0; //start bit
                    default: txd <= #1 sbuf_txd[tr_count];
                  endcase
            tr_count <= #1 tr_count + 4'b1;
                  smod_cnt_t <= #1 6'h0;
                end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
              end
      end
      2'b10: begin // mode 2
//
// if smod (pcon[7]) is 1 count to 4 else count to 6
//
        if (((pcon[7]) & (smod_cnt_t==6'd31)) | (!(pcon[7]) & (smod_cnt_t==6'd63))) begin
            case (tr_count)
            4'd8: begin
                    txd <= #1 scon[3];
                  end
            4'd9: begin
                    txd <= #1 1'b1; //stop bit
                  end
            4'd10: begin
                    trans <= #1 1'b0;
                  end
 
                  default: begin
                    txd <= #1 sbuf_txd[tr_count];
                  end
                endcase
          tr_count <= #1 tr_count+1'b1;
                smod_cnt_t <= #1 6'h00;
              end else begin
          smod_cnt_t <= #1 smod_cnt_t + 6'h01;
              end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
      if (((pcon[7]) &  (smod_cnt_t == 6'd15))| (!(pcon[7]) & (smod_cnt_t==6'd31)))
          begin
            case (tr_count)
              4'd8: begin
                txd <= #1 scon[3];
              end
              4'd9: begin
                txd <= #1 1'b1; //stop bit
              end
              4'd10: begin
          trans <= #1 1'b0;
        end
              4'b1111: txd <= #1 1'b0; //start bit
              default: begin
                txd <= #1 sbuf_txd[tr_count];
              end
            endcase
            tr_count <= #1 tr_count+1'b1;
            smod_cnt_t <= #1 6'h00;
          end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;
        end
      end
    endcase
  end else
    txd <= #1 1'b1;
end
 
//
//power control register
//
always @(posedge clk or posedge rst)
begin
  if (rst)
  begin
    pcon <= #1 `OC8051_RST_PCON;
  end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
    pcon <= #1 data_in;
end
 
//
//serial port buffer (receive)
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    re_count <= #1 4'd0;
    receive <= #1 1'b0;
    sbuf_rxd <= #1 8'h00;
    sbuf_rxd_tmp <= #1 11'd0;
    smod_cnt_r <= #1 6'h00;
    r_int <= #1 1'b0;
  end else if (receive) begin
    case (scon[7:6])
      2'b00: begin // mode 0
        if (re_count==4'd8) begin
          receive <= #1 1'b0;
          r_int <= #1 1'b1;
          sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
        end else begin
          sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;
          r_int <= #1 1'b0;
        end
        re_count <= #1 re_count + 4'd1;
      end
      2'b01: begin // mode 1
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if (((pcon[7]) &  (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
                begin
            r_int <= #1 1'b0;
            re_count <= #1 re_count + 4'd1;
            smod_cnt_r <= #1 6'h00;
            sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
            if ((re_count==4'd0) && (rxd))
              receive <= #1 1'b0;
 
                end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
              end else begin
              r_int <= #1 1'b1;
            if (re_count == 4'd10)
          begin
              sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
            receive <= #1 1'b0;
              r_int <= #1 1'b1;
          end else r_int <= #1 1'b0;
        end
      end
      2'b10: begin // mode 2
        if (((pcon[7]) & (smod_cnt_r==6'd31)) | (!(pcon[7]) & (smod_cnt_r==6'd63))) begin
          r_int <= #1 1'b0;
            re_count <= #1 re_count + 4'd1;
          smod_cnt_r <= #1 6'h00;
          sbuf_rxd_tmp[re_count_buff] <= #1 rxd;
          re_count <= #1 re_count + 4'd1;
              end else begin
          smod_cnt_r <= #1 smod_cnt_r + 6'h1;
                if (re_count==4'd11) begin
                  sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
                  r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
                  receive <= #1 1'b0;
                end else
                  r_int <= #1 1'b0;
        end
      end
      default: begin // mode 3
        if ((t1_ow) & !(t1_ow_buf))
        begin
          if (((pcon[7]) &  (smod_cnt_r == 6'd15))| (!(pcon[7]) & (smod_cnt_r==6'd31)))
                begin
            sbuf_rxd_tmp[re_count] <= #1 rxd;
                  r_int <= #1 1'b0;
                re_count <= #1 re_count + 4'd1;
                  smod_cnt_r <= #1 6'h00;
                end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;
              end else begin
          if (re_count==4'd11) begin
            sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];
            receive <= #1 1'b0;
                  r_int <= #1 sbuf_rxd_tmp[0] | !scon[5];
                end else begin
            r_int <= #1 1'b0;
          end
              end
      end
    endcase
  end else begin
    case (scon[7:6])
      2'b00: begin
        if ((scon[4]) && !(scon[0]) && !(r_int)) begin
          receive <= #1 1'b1;
        end
      end
      2'b10: begin
        if ((scon[4]) && !(rxd)) begin
          receive <= #1 1'b1;
          if (pcon[7])
            smod_cnt_r <= #1 6'd15;
          else smod_cnt_r <= #1 6'd31;
        end
      end
      default: begin
        if ((scon[4]) && (!rxd)) begin
          if (pcon[7])
            smod_cnt_r <= #1 6'd7;
          else smod_cnt_r <= #1 6'd15;
          receive <= #1 1'b1;
        end
      end
    endcase
 
    sbuf_rxd_tmp <= #1 11'd0;
    re_count <= #1 4'd0;
    r_int <= #1 1'b0;
  end
end
 
//
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) data_out <= #1 8'h0;
  else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) |
     (wr_addr==`OC8051_SFR_SCON))) begin
    data_out <= #1 data_in;
  end else begin
    case (rd_addr)
      `OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
      `OC8051_SFR_PCON: data_out <= #1 pcon;
      default: data_out <= #1 scon;
    endcase
  end
end
 
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    trans_buf <= #1 1'b0;
    receive_buf <= #1 1'b0;
    t1_ow_buf <= #1 1'b0;
    rxd_buf <= #1 1'b0;
  end else begin
    trans_buf <= #1 trans;
    receive_buf <= #1 receive;
    t1_ow_buf <= #1 t1_ow;
    rxd_buf <= #1 rxd;
  end
end
 
always  @(posedge clk or posedge rst)
begin
  if (rst) bit_out <= #1 1'b0;
  else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
    bit_out <= #1 bit_in;
  end else
    bit_out <= #1 scon[rd_addr[2:0]];
end
 
always @(posedge clk or posedge rst)
  if (rst)
    re_count_buff <= #1 4'h4;
  else re_count_buff <= #1 re_count;
 
endmodule
 

Line No.	Rev	Author	Line
1	8	markom	`// synopsys translate_off`
2			`include "oc8051_timescale.v"
3			`// synopsys translate_on`
4
5			`include "oc8051_defines.v"
6
7	2	simont	`module oc8051_uart (rst, clk, bit_in, rd_addr, data_in, bit_out, wr, wr_bit, wr_addr, data_out,`
8	4	markom	`rxd, txd, intr, t1_ow);`
9	2	simont
10			`input rst, clk, bit_in, wr, rxd, wr_bit, t1_ow;`
11			`input [7:0] rd_addr, data_in, wr_addr;`
12
13	4	markom	`output txd, intr, bit_out;`
14	2	simont	`output [7:0] data_out;`
15
16			`reg txd, bit_out;`
17			`reg [7:0] data_out;`
18
19	30	simont	`reg tr_start, trans, trans_buf, t1_ow_buf;`
20			`reg [5:0] smod_cnt_r, smod_cnt_t;`
21	2	simont	`reg receive, receive_buf, rxd_buf, r_int;`
22			`//`
23			`reg [7:0] sbuf_rxd, sbuf_txd, scon, pcon;`
24			`reg [10:0] sbuf_rxd_tmp;`
25			`//`
26			`//tr_count trancive counter`
27			`//re_count receive counter`
28	30	simont	`reg [3:0] tr_count, re_count, re_count_buff;`
29	2	simont
30
31	4	markom	`assign intr = scon[1] \| scon [0];`
32	2	simont
33			`//`
34			`//serial port control register`
35			`//`
36			`always @(posedge clk or posedge rst)`
37			`begin`
38			`if (rst)`
39			scon <= #1 `OC8051_RST_SCON;
40			else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_SCON))
41			`scon <= #1 data_in;`
42			else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_SCON))
43			`scon[wr_addr[2:0]] <= #1 bit_in;`
44			`else if ((trans_buf) & !(trans))`
45			`scon[1] <= #1 1'b1;`
46			`else if ((receive_buf) & !(receive) & !(sbuf_rxd_tmp[0])) begin`
47			`case (scon[7:6])`
48			`2'b00: scon[0] <= #1 1'b1;`
49			`default: begin`
50			`if ((sbuf_rxd_tmp[9]) \| !(scon[5])) scon[0] <= #1 1'b1;`
51			`scon[2] <= #1 sbuf_rxd_tmp[9];`
52			`end`
53			`endcase`
54			`end`
55
56			`end`
57
58			`//`
59			`//serial port buffer (transmit)`
60			`//`
61			`always @(posedge clk or posedge rst)`
62			`begin`
63			`if (rst) begin`
64			sbuf_txd <= #1 `OC8051_RST_SBUF;
65	4	markom	`tr_start <= #1 1'b0;`
66	2	simont	end else if ((wr_addr==`OC8051_SFR_SBUF) & (wr) & !(wr_bit)) begin
67			`sbuf_txd <= #1 data_in;`
68			`tr_start <= #1 1'b1;`
69	5	markom	`end else tr_start <= #1 1'b0;`
70	2	simont	`end`
71
72			`//`
73			`// transmit`
74			`//`
75			`always @(posedge clk or posedge rst)`
76			`begin`
77			`if (rst) begin`
78			`txd <= #1 1'b1;`
79			`tr_count <= #1 4'd0;`
80			`trans <= #1 1'b0;`
81	30	simont	`smod_cnt_t <= #1 6'h0;`
82	2	simont	`//`
83			`// start transmiting`
84			`//`
85			`end else if (tr_start) begin`
86			`case (scon[7:6])`
87			`2'b00: begin // mode 0`
88			`txd <= #1 sbuf_txd[0];`
89			`tr_count <= #1 4'd1;`
90			`end`
91			`2'b10: begin`
92			`txd <= #1 1'b0;`
93			`tr_count <= #1 4'd0;`
94			`end`
95			`default: begin // mode 1 and mode 3`
96			`tr_count <= #1 4'b1111;`
97			`end`
98			`endcase`
99			`trans <= #1 1'b1;`
100	30	simont	`smod_cnt_t <= #1 6'h0;`
101	2	simont	`//`
102	30	simont	`// transmiting/`
103	2	simont	`//`
104			`end else if (trans)`
105			`begin`
106			`case (scon[7:6])`
107			`2'b00: begin //mode 0`
108	4	markom	`if (tr_count==4'd8)`
109	2	simont	`begin`
110			`trans <= #1 1'b0;`
111			`txd <= #1 1'b1;`
112			`end else begin`
113			`txd <= #1 sbuf_txd[tr_count];`
114	4	markom	`tr_count <= #1 tr_count + 4'b1;`
115	2	simont	`end`
116			`end`
117			`2'b01: begin // mode 1`
118			`if ((t1_ow) & !(t1_ow_buf))`
119	30	simont	`begin`
120			`if (((pcon[7]) & (smod_cnt_t == 6'd15))\| (!(pcon[7]) & (smod_cnt_t==6'd31)))`
121			`begin`
122	2	simont	`case (tr_count)`
123			`4'd8: txd <= #1 1'b1; // stop bit`
124	30	simont	`4'd9: trans <= #1 1'b0;`
125			`4'b1111: txd <= #1 1'b0; //start bit`
126			`default: txd <= #1 sbuf_txd[tr_count];`
127			`endcase`
128	4	markom	`tr_count <= #1 tr_count + 4'b1;`
129	30	simont	`smod_cnt_t <= #1 6'h0;`
130			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
131			`end`
132	2	simont	`end`
133			`2'b10: begin // mode 2`
134			`//`
135			`// if smod (pcon[7]) is 1 count to 4 else count to 6`
136			`//`
137	30	simont	`if (((pcon[7]) & (smod_cnt_t==6'd31)) \| (!(pcon[7]) & (smod_cnt_t==6'd63))) begin`
138			`case (tr_count)`
139	2	simont	`4'd8: begin`
140	30	simont	`txd <= #1 scon[3];`
141			`end`
142	2	simont	`4'd9: begin`
143	30	simont	`txd <= #1 1'b1; //stop bit`
144			`end`
145			`4'd10: begin`
146			`trans <= #1 1'b0;`
147			`end`
148
149			`default: begin`
150			`txd <= #1 sbuf_txd[tr_count];`
151			`end`
152			`endcase`
153	2	simont	`tr_count <= #1 tr_count+1'b1;`
154	30	simont	`smod_cnt_t <= #1 6'h00;`
155			`end else begin`
156			`smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
157			`end`
158	2	simont	`end`
159			`default: begin // mode 3`
160			`if ((t1_ow) & !(t1_ow_buf))`
161			`begin`
162	30	simont	`if (((pcon[7]) & (smod_cnt_t == 6'd15))\| (!(pcon[7]) & (smod_cnt_t==6'd31)))`
163	2	simont	`begin`
164			`case (tr_count)`
165			`4'd8: begin`
166			`txd <= #1 scon[3];`
167			`end`
168			`4'd9: begin`
169			`txd <= #1 1'b1; //stop bit`
170			`end`
171			`4'd10: begin`
172			`trans <= #1 1'b0;`
173			`end`
174			`4'b1111: txd <= #1 1'b0; //start bit`
175			`default: begin`
176			`txd <= #1 sbuf_txd[tr_count];`
177			`end`
178			`endcase`
179			`tr_count <= #1 tr_count+1'b1;`
180	30	simont	`smod_cnt_t <= #1 6'h00;`
181			`end else smod_cnt_t <= #1 smod_cnt_t + 6'h01;`
182	2	simont	`end`
183			`end`
184			`endcase`
185			`end else`
186			`txd <= #1 1'b1;`
187			`end`
188
189			`//`
190			`//power control register`
191			`//`
192			`always @(posedge clk or posedge rst)`
193			`begin`
194			`if (rst)`
195			`begin`
196			pcon <= #1 `OC8051_RST_PCON;
197			end else if ((wr_addr==`OC8051_SFR_PCON) & (wr) & !(wr_bit))
198			`pcon <= #1 data_in;`
199			`end`
200
201			`//`
202	4	markom	`//serial port buffer (receive)`
203	2	simont	`//`
204			`always @(posedge clk or posedge rst)`
205			`begin`
206			`if (rst) begin`
207			`re_count <= #1 4'd0;`
208			`receive <= #1 1'b0;`
209			`sbuf_rxd <= #1 8'h00;`
210			`sbuf_rxd_tmp <= #1 11'd0;`
211	30	simont	`smod_cnt_r <= #1 6'h00;`
212	2	simont	`r_int <= #1 1'b0;`
213			`end else if (receive) begin`
214			`case (scon[7:6])`
215			`2'b00: begin // mode 0`
216			`if (re_count==4'd8) begin`
217			`receive <= #1 1'b0;`
218			`r_int <= #1 1'b1;`
219			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
220			`end else begin`
221	5	markom	`sbuf_rxd_tmp[re_count + 4'd1] <= #1 rxd;`
222	2	simont	`r_int <= #1 1'b0;`
223			`end`
224	5	markom	`re_count <= #1 re_count + 4'd1;`
225	2	simont	`end`
226			`2'b01: begin // mode 1`
227			`if ((t1_ow) & !(t1_ow_buf))`
228	30	simont	`begin`
229			`if (((pcon[7]) & (smod_cnt_r == 6'd15))\| (!(pcon[7]) & (smod_cnt_r==6'd31)))`
230			`begin`
231	2	simont	`r_int <= #1 1'b0;`
232	30	simont	`re_count <= #1 re_count + 4'd1;`
233			`smod_cnt_r <= #1 6'h00;`
234			`sbuf_rxd_tmp[re_count_buff] <= #1 rxd;`
235			`if ((re_count==4'd0) && (rxd))`
236			`receive <= #1 1'b0;`
237	2	simont
238	30	simont	`end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;`
239			`end else begin`
240			`r_int <= #1 1'b1;`
241			`if (re_count == 4'd10)`
242			`begin`
243			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
244			`receive <= #1 1'b0;`
245			`r_int <= #1 1'b1;`
246			`end else r_int <= #1 1'b0;`
247			`end`
248	2	simont	`end`
249			`2'b10: begin // mode 2`
250	30	simont	`if (((pcon[7]) & (smod_cnt_r==6'd31)) \| (!(pcon[7]) & (smod_cnt_r==6'd63))) begin`
251			`r_int <= #1 1'b0;`
252			`re_count <= #1 re_count + 4'd1;`
253			`smod_cnt_r <= #1 6'h00;`
254			`sbuf_rxd_tmp[re_count_buff] <= #1 rxd;`
255			`re_count <= #1 re_count + 4'd1;`
256			`end else begin`
257			`smod_cnt_r <= #1 smod_cnt_r + 6'h1;`
258			`if (re_count==4'd11) begin`
259			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
260			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
261			`receive <= #1 1'b0;`
262			`end else`
263			`r_int <= #1 1'b0;`
264			`end`
265	2	simont	`end`
266			`default: begin // mode 3`
267			`if ((t1_ow) & !(t1_ow_buf))`
268	30	simont	`begin`
269			`if (((pcon[7]) & (smod_cnt_r == 6'd15))\| (!(pcon[7]) & (smod_cnt_r==6'd31)))`
270			`begin`
271			`sbuf_rxd_tmp[re_count] <= #1 rxd;`
272			`r_int <= #1 1'b0;`
273			`re_count <= #1 re_count + 4'd1;`
274			`smod_cnt_r <= #1 6'h00;`
275			`end else smod_cnt_r <= #1 smod_cnt_r + 6'h01;`
276			`end else begin`
277			`if (re_count==4'd11) begin`
278			`sbuf_rxd <= #1 sbuf_rxd_tmp[8:1];`
279			`receive <= #1 1'b0;`
280			`r_int <= #1 sbuf_rxd_tmp[0] \| !scon[5];`
281			`end else begin`
282			`r_int <= #1 1'b0;`
283			`end`
284			`end`
285	2	simont	`end`
286			`endcase`
287			`end else begin`
288			`case (scon[7:6])`
289			`2'b00: begin`
290	30	simont	`if ((scon[4]) && !(scon[0]) && !(r_int)) begin`
291	2	simont	`receive <= #1 1'b1;`
292			`end`
293			`end`
294			`2'b10: begin`
295	30	simont	`if ((scon[4]) && !(rxd)) begin`
296	2	simont	`receive <= #1 1'b1;`
297	30	simont	`if (pcon[7])`
298			`smod_cnt_r <= #1 6'd15;`
299			`else smod_cnt_r <= #1 6'd31;`
300	2	simont	`end`
301			`end`
302			`default: begin`
303	30	simont	`if ((scon[4]) && (!rxd)) begin`
304			`if (pcon[7])`
305			`smod_cnt_r <= #1 6'd7;`
306			`else smod_cnt_r <= #1 6'd15;`
307			`receive <= #1 1'b1;`
308	2	simont	`end`
309			`end`
310			`endcase`
311
312	30	simont	`sbuf_rxd_tmp <= #1 11'd0;`
313	2	simont	`re_count <= #1 4'd0;`
314			`r_int <= #1 1'b0;`
315			`end`
316			`end`
317
318			`//`
319			`//`
320			`//`
321	4	markom	`always @(posedge clk or posedge rst)`
322	2	simont	`begin`
323	4	markom	`if (rst) data_out <= #1 8'h0;`
324			else if (wr & !wr_bit & (wr_addr==rd_addr) & ((wr_addr==`OC8051_SFR_PCON) \|
325	2	simont	(wr_addr==`OC8051_SFR_SCON))) begin
326			`data_out <= #1 data_in;`
327			`end else begin`
328			`case (rd_addr)`
329			`OC8051_SFR_SBUF: data_out <= #1 sbuf_rxd;
330			`OC8051_SFR_PCON: data_out <= #1 pcon;
331			`default: data_out <= #1 scon;`
332			`endcase`
333			`end`
334			`end`
335
336
337	4	markom	`always @(posedge clk or posedge rst)`
338	2	simont	`begin`
339	4	markom	`if (rst) begin`
340			`trans_buf <= #1 1'b0;`
341			`receive_buf <= #1 1'b0;`
342			`t1_ow_buf <= #1 1'b0;`
343			`rxd_buf <= #1 1'b0;`
344			`end else begin`
345			`trans_buf <= #1 trans;`
346			`receive_buf <= #1 receive;`
347			`t1_ow_buf <= #1 t1_ow;`
348			`rxd_buf <= #1 rxd;`
349			`end`
350	2	simont	`end`
351
352	4	markom	`always @(posedge clk or posedge rst)`
353	2	simont	`begin`
354	4	markom	`if (rst) bit_out <= #1 1'b0;`
355			else if (wr & wr_bit & (rd_addr==wr_addr) & (wr_addr[7:3]==`OC8051_SFR_B_SCON)) begin
356	2	simont	`bit_out <= #1 bit_in;`
357			`end else`
358			`bit_out <= #1 scon[rd_addr[2:0]];`
359			`end`
360
361	30	simont	`always @(posedge clk or posedge rst)`
362			`if (rst)`
363			`re_count_buff <= #1 4'h4;`
364			`else re_count_buff <= #1 re_count;`
365
366	2	simont	`endmodule`
367	30	simont

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_uart.v] - Blame information for rev 30