1 |
2 |
simont |
|
2 |
14 |
simont |
///
|
3 |
|
|
/// created by oc8051 rom maker
|
4 |
|
|
/// author: Simon Teran (simont@opencores.org)
|
5 |
|
|
///
|
6 |
19 |
simont |
/// source file: C:\simont\monasm1.hex
|
7 |
41 |
simont |
/// date: 8/21/2002
|
8 |
|
|
/// time: 4:20:40 PM
|
9 |
14 |
simont |
///
|
10 |
2 |
simont |
|
11 |
|
|
module ROM32X1(O, A0, A1, A2, A3, A4); // synthesis syn_black_box syn_resources="luts=2"
|
12 |
|
|
output O;
|
13 |
|
|
input A0;
|
14 |
|
|
input A1;
|
15 |
|
|
input A2;
|
16 |
|
|
input A3;
|
17 |
|
|
input A4;
|
18 |
|
|
endmodule
|
19 |
|
|
|
20 |
|
|
//rom for 8051 processor
|
21 |
|
|
|
22 |
14 |
simont |
module oc8051_rom (rst, clk, addr, ea_int, data1, data2, data3);
|
23 |
2 |
simont |
|
24 |
19 |
simont |
parameter INT_ROM_WID= 10;
|
25 |
14 |
simont |
|
26 |
|
|
input rst, clk;
|
27 |
2 |
simont |
input [15:0] addr;
|
28 |
14 |
simont |
output ea_int;
|
29 |
2 |
simont |
output [7:0] data1, data2, data3;
|
30 |
19 |
simont |
reg ea_int;
|
31 |
14 |
simont |
reg [4:0] addr01;
|
32 |
2 |
simont |
reg [7:0] data1, data2, data3;
|
33 |
|
|
|
34 |
14 |
simont |
wire ea;
|
35 |
2 |
simont |
wire [15:0] addr_rst;
|
36 |
19 |
simont |
wire [7:0] int_data0, int_data1, int_data2, int_data3, int_data4, int_data5, int_data6, int_data7, int_data8, int_data9, int_data10, int_data11, int_data12, int_data13, int_data14, int_data15, int_data16, int_data17, int_data18, int_data19, int_data20, int_data21, int_data22, int_data23, int_data24, int_data25, int_data26, int_data27, int_data28, int_data29, int_data30, int_data31;
|
37 |
2 |
simont |
|
38 |
14 |
simont |
assign ea = | addr[15:INT_ROM_WID];
|
39 |
|
|
|
40 |
2 |
simont |
assign addr_rst = rst ? 16'h0000 : addr;
|
41 |
|
|
|
42 |
|
|
rom0 rom_0 (.a(addr01), .o(int_data0));
|
43 |
|
|
rom1 rom_1 (.a(addr01), .o(int_data1));
|
44 |
19 |
simont |
rom2 rom_2 (.a(addr_rst[9:5]), .o(int_data2));
|
45 |
|
|
rom3 rom_3 (.a(addr_rst[9:5]), .o(int_data3));
|
46 |
|
|
rom4 rom_4 (.a(addr_rst[9:5]), .o(int_data4));
|
47 |
|
|
rom5 rom_5 (.a(addr_rst[9:5]), .o(int_data5));
|
48 |
|
|
rom6 rom_6 (.a(addr_rst[9:5]), .o(int_data6));
|
49 |
|
|
rom7 rom_7 (.a(addr_rst[9:5]), .o(int_data7));
|
50 |
|
|
rom8 rom_8 (.a(addr_rst[9:5]), .o(int_data8));
|
51 |
|
|
rom9 rom_9 (.a(addr_rst[9:5]), .o(int_data9));
|
52 |
|
|
rom10 rom_10 (.a(addr_rst[9:5]), .o(int_data10));
|
53 |
|
|
rom11 rom_11 (.a(addr_rst[9:5]), .o(int_data11));
|
54 |
|
|
rom12 rom_12 (.a(addr_rst[9:5]), .o(int_data12));
|
55 |
|
|
rom13 rom_13 (.a(addr_rst[9:5]), .o(int_data13));
|
56 |
|
|
rom14 rom_14 (.a(addr_rst[9:5]), .o(int_data14));
|
57 |
|
|
rom15 rom_15 (.a(addr_rst[9:5]), .o(int_data15));
|
58 |
|
|
rom16 rom_16 (.a(addr_rst[9:5]), .o(int_data16));
|
59 |
|
|
rom17 rom_17 (.a(addr_rst[9:5]), .o(int_data17));
|
60 |
|
|
rom18 rom_18 (.a(addr_rst[9:5]), .o(int_data18));
|
61 |
|
|
rom19 rom_19 (.a(addr_rst[9:5]), .o(int_data19));
|
62 |
|
|
rom20 rom_20 (.a(addr_rst[9:5]), .o(int_data20));
|
63 |
|
|
rom21 rom_21 (.a(addr_rst[9:5]), .o(int_data21));
|
64 |
|
|
rom22 rom_22 (.a(addr_rst[9:5]), .o(int_data22));
|
65 |
|
|
rom23 rom_23 (.a(addr_rst[9:5]), .o(int_data23));
|
66 |
|
|
rom24 rom_24 (.a(addr_rst[9:5]), .o(int_data24));
|
67 |
|
|
rom25 rom_25 (.a(addr_rst[9:5]), .o(int_data25));
|
68 |
|
|
rom26 rom_26 (.a(addr_rst[9:5]), .o(int_data26));
|
69 |
|
|
rom27 rom_27 (.a(addr_rst[9:5]), .o(int_data27));
|
70 |
|
|
rom28 rom_28 (.a(addr_rst[9:5]), .o(int_data28));
|
71 |
|
|
rom29 rom_29 (.a(addr_rst[9:5]), .o(int_data29));
|
72 |
|
|
rom30 rom_30 (.a(addr_rst[9:5]), .o(int_data30));
|
73 |
|
|
rom31 rom_31 (.a(addr_rst[9:5]), .o(int_data31));
|
74 |
2 |
simont |
|
75 |
|
|
always @(addr_rst)
|
76 |
|
|
begin
|
77 |
|
|
if (addr_rst[1])
|
78 |
19 |
simont |
addr01= addr_rst[9:5]+ 5'h1;
|
79 |
2 |
simont |
else
|
80 |
19 |
simont |
addr01= addr_rst[9:5];
|
81 |
2 |
simont |
end
|
82 |
|
|
|
83 |
|
|
//
|
84 |
|
|
// always read tree bits in row
|
85 |
|
|
always @(posedge clk)
|
86 |
|
|
begin
|
87 |
19 |
simont |
case(addr[4:0])
|
88 |
|
|
5'd0: begin
|
89 |
2 |
simont |
data1 <= #1 int_data0;
|
90 |
|
|
data2 <= #1 int_data1;
|
91 |
|
|
data3 <= #1 int_data2;
|
92 |
|
|
end
|
93 |
19 |
simont |
5'd1: begin
|
94 |
2 |
simont |
data1 <= #1 int_data1;
|
95 |
|
|
data2 <= #1 int_data2;
|
96 |
|
|
data3 <= #1 int_data3;
|
97 |
|
|
end
|
98 |
19 |
simont |
5'd2: begin
|
99 |
2 |
simont |
data1 <= #1 int_data2;
|
100 |
|
|
data2 <= #1 int_data3;
|
101 |
19 |
simont |
data3 <= #1 int_data4;
|
102 |
|
|
end
|
103 |
|
|
5'd3: begin
|
104 |
|
|
data1 <= #1 int_data3;
|
105 |
|
|
data2 <= #1 int_data4;
|
106 |
|
|
data3 <= #1 int_data5;
|
107 |
|
|
end
|
108 |
|
|
5'd4: begin
|
109 |
|
|
data1 <= #1 int_data4;
|
110 |
|
|
data2 <= #1 int_data5;
|
111 |
|
|
data3 <= #1 int_data6;
|
112 |
|
|
end
|
113 |
|
|
5'd5: begin
|
114 |
|
|
data1 <= #1 int_data5;
|
115 |
|
|
data2 <= #1 int_data6;
|
116 |
|
|
data3 <= #1 int_data7;
|
117 |
|
|
end
|
118 |
|
|
5'd6: begin
|
119 |
|
|
data1 <= #1 int_data6;
|
120 |
|
|
data2 <= #1 int_data7;
|
121 |
|
|
data3 <= #1 int_data8;
|
122 |
|
|
end
|
123 |
|
|
5'd7: begin
|
124 |
|
|
data1 <= #1 int_data7;
|
125 |
|
|
data2 <= #1 int_data8;
|
126 |
|
|
data3 <= #1 int_data9;
|
127 |
|
|
end
|
128 |
|
|
5'd8: begin
|
129 |
|
|
data1 <= #1 int_data8;
|
130 |
|
|
data2 <= #1 int_data9;
|
131 |
|
|
data3 <= #1 int_data10;
|
132 |
|
|
end
|
133 |
|
|
5'd9: begin
|
134 |
|
|
data1 <= #1 int_data9;
|
135 |
|
|
data2 <= #1 int_data10;
|
136 |
|
|
data3 <= #1 int_data11;
|
137 |
|
|
end
|
138 |
|
|
5'd10: begin
|
139 |
|
|
data1 <= #1 int_data10;
|
140 |
|
|
data2 <= #1 int_data11;
|
141 |
|
|
data3 <= #1 int_data12;
|
142 |
|
|
end
|
143 |
|
|
5'd11: begin
|
144 |
|
|
data1 <= #1 int_data11;
|
145 |
|
|
data2 <= #1 int_data12;
|
146 |
|
|
data3 <= #1 int_data13;
|
147 |
|
|
end
|
148 |
|
|
5'd12: begin
|
149 |
|
|
data1 <= #1 int_data12;
|
150 |
|
|
data2 <= #1 int_data13;
|
151 |
|
|
data3 <= #1 int_data14;
|
152 |
|
|
end
|
153 |
|
|
5'd13: begin
|
154 |
|
|
data1 <= #1 int_data13;
|
155 |
|
|
data2 <= #1 int_data14;
|
156 |
|
|
data3 <= #1 int_data15;
|
157 |
|
|
end
|
158 |
|
|
5'd14: begin
|
159 |
|
|
data1 <= #1 int_data14;
|
160 |
|
|
data2 <= #1 int_data15;
|
161 |
|
|
data3 <= #1 int_data16;
|
162 |
|
|
end
|
163 |
|
|
5'd15: begin
|
164 |
|
|
data1 <= #1 int_data15;
|
165 |
|
|
data2 <= #1 int_data16;
|
166 |
|
|
data3 <= #1 int_data17;
|
167 |
|
|
end
|
168 |
|
|
5'd16: begin
|
169 |
|
|
data1 <= #1 int_data16;
|
170 |
|
|
data2 <= #1 int_data17;
|
171 |
|
|
data3 <= #1 int_data18;
|
172 |
|
|
end
|
173 |
|
|
5'd17: begin
|
174 |
|
|
data1 <= #1 int_data17;
|
175 |
|
|
data2 <= #1 int_data18;
|
176 |
|
|
data3 <= #1 int_data19;
|
177 |
|
|
end
|
178 |
|
|
5'd18: begin
|
179 |
|
|
data1 <= #1 int_data18;
|
180 |
|
|
data2 <= #1 int_data19;
|
181 |
|
|
data3 <= #1 int_data20;
|
182 |
|
|
end
|
183 |
|
|
5'd19: begin
|
184 |
|
|
data1 <= #1 int_data19;
|
185 |
|
|
data2 <= #1 int_data20;
|
186 |
|
|
data3 <= #1 int_data21;
|
187 |
|
|
end
|
188 |
|
|
5'd20: begin
|
189 |
|
|
data1 <= #1 int_data20;
|
190 |
|
|
data2 <= #1 int_data21;
|
191 |
|
|
data3 <= #1 int_data22;
|
192 |
|
|
end
|
193 |
|
|
5'd21: begin
|
194 |
|
|
data1 <= #1 int_data21;
|
195 |
|
|
data2 <= #1 int_data22;
|
196 |
|
|
data3 <= #1 int_data23;
|
197 |
|
|
end
|
198 |
|
|
5'd22: begin
|
199 |
|
|
data1 <= #1 int_data22;
|
200 |
|
|
data2 <= #1 int_data23;
|
201 |
|
|
data3 <= #1 int_data24;
|
202 |
|
|
end
|
203 |
|
|
5'd23: begin
|
204 |
|
|
data1 <= #1 int_data23;
|
205 |
|
|
data2 <= #1 int_data24;
|
206 |
|
|
data3 <= #1 int_data25;
|
207 |
|
|
end
|
208 |
|
|
5'd24: begin
|
209 |
|
|
data1 <= #1 int_data24;
|
210 |
|
|
data2 <= #1 int_data25;
|
211 |
|
|
data3 <= #1 int_data26;
|
212 |
|
|
end
|
213 |
|
|
5'd25: begin
|
214 |
|
|
data1 <= #1 int_data25;
|
215 |
|
|
data2 <= #1 int_data26;
|
216 |
|
|
data3 <= #1 int_data27;
|
217 |
|
|
end
|
218 |
|
|
5'd26: begin
|
219 |
|
|
data1 <= #1 int_data26;
|
220 |
|
|
data2 <= #1 int_data27;
|
221 |
|
|
data3 <= #1 int_data28;
|
222 |
|
|
end
|
223 |
|
|
5'd27: begin
|
224 |
|
|
data1 <= #1 int_data27;
|
225 |
|
|
data2 <= #1 int_data28;
|
226 |
|
|
data3 <= #1 int_data29;
|
227 |
|
|
end
|
228 |
|
|
5'd28: begin
|
229 |
|
|
data1 <= #1 int_data28;
|
230 |
|
|
data2 <= #1 int_data29;
|
231 |
|
|
data3 <= #1 int_data30;
|
232 |
|
|
end
|
233 |
|
|
5'd29: begin
|
234 |
|
|
data1 <= #1 int_data29;
|
235 |
|
|
data2 <= #1 int_data30;
|
236 |
|
|
data3 <= #1 int_data31;
|
237 |
|
|
end
|
238 |
|
|
5'd30: begin
|
239 |
|
|
data1 <= #1 int_data30;
|
240 |
|
|
data2 <= #1 int_data31;
|
241 |
2 |
simont |
data3 <= #1 int_data0;
|
242 |
|
|
end
|
243 |
19 |
simont |
5'd31: begin
|
244 |
|
|
data1 <= #1 int_data31;
|
245 |
2 |
simont |
data2 <= #1 int_data0;
|
246 |
|
|
data3 <= #1 int_data1;
|
247 |
|
|
end
|
248 |
|
|
default: begin
|
249 |
|
|
data1 <= #1 8'h00;
|
250 |
|
|
data2 <= #1 8'h00;
|
251 |
|
|
data3 <= #1 8'h00;
|
252 |
|
|
end
|
253 |
|
|
endcase
|
254 |
|
|
end
|
255 |
|
|
|
256 |
19 |
simont |
always @(posedge clk or posedge rst)
|
257 |
|
|
if (rst)
|
258 |
|
|
ea_int <= #1 1'b1;
|
259 |
|
|
else ea_int <= #1 !ea;
|
260 |
|
|
|
261 |
2 |
simont |
endmodule
|
262 |
|
|
|
263 |
|
|
|
264 |
|
|
//rom0
|
265 |
|
|
module rom0 (o,a);
|
266 |
|
|
input [4:0] a;
|
267 |
|
|
output [7:0] o;
|
268 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00092dd0" */;
|
269 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00143111" */;
|
270 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000008d8" */;
|
271 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00178438" */;
|
272 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000203c4" */;
|
273 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000880c0" */;
|
274 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008a0c0" */;
|
275 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00032bc0" */;
|
276 |
2 |
simont |
endmodule
|
277 |
|
|
|
278 |
|
|
//rom1
|
279 |
|
|
module rom1 (o,a);
|
280 |
|
|
input [4:0] a;
|
281 |
|
|
output [7:0] o;
|
282 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00160931" */;
|
283 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e0294" */;
|
284 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00193938" */;
|
285 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00180010" */;
|
286 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00032148" */;
|
287 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f1564" */;
|
288 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f1d60" */;
|
289 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000021f0" */;
|
290 |
2 |
simont |
endmodule
|
291 |
|
|
|
292 |
|
|
//rom2
|
293 |
|
|
module rom2 (o,a);
|
294 |
|
|
input [4:0] a;
|
295 |
|
|
output [7:0] o;
|
296 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0015a771" */;
|
297 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0017b405" */;
|
298 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c2601" */;
|
299 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00040170" */;
|
300 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002ff1" */;
|
301 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f0e4d" */;
|
302 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f2ec8" */;
|
303 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00008d35" */;
|
304 |
2 |
simont |
endmodule
|
305 |
|
|
|
306 |
|
|
//rom3
|
307 |
|
|
module rom3 (o,a);
|
308 |
|
|
input [4:0] a;
|
309 |
|
|
output [7:0] o;
|
310 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00070d2c" */;
|
311 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00012083" */;
|
312 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00070f30" */;
|
313 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00150014" */;
|
314 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00128d75" */;
|
315 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0017af31" */;
|
316 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00078f70" */;
|
317 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000224" */;
|
318 |
2 |
simont |
endmodule
|
319 |
|
|
|
320 |
19 |
simont |
//rom4
|
321 |
|
|
module rom4 (o,a);
|
322 |
|
|
input [4:0] a;
|
323 |
|
|
output [7:0] o;
|
324 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c12f0" */;
|
325 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00031218" */;
|
326 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f10c0" */;
|
327 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d1020" */;
|
328 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010bf2c" */;
|
329 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00179048" */;
|
330 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00071d44" */;
|
331 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00003f60" */;
|
332 |
19 |
simont |
endmodule
|
333 |
|
|
|
334 |
|
|
//rom5
|
335 |
|
|
module rom5 (o,a);
|
336 |
|
|
input [4:0] a;
|
337 |
|
|
output [7:0] o;
|
338 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001402a8" */;
|
339 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008309e" */;
|
340 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00100224" */;
|
341 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00081c08" */;
|
342 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00101274" */;
|
343 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00141278" */;
|
344 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004126e" */;
|
345 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000052e8" */;
|
346 |
19 |
simont |
endmodule
|
347 |
|
|
|
348 |
|
|
//rom6
|
349 |
|
|
module rom6 (o,a);
|
350 |
|
|
input [4:0] a;
|
351 |
|
|
output [7:0] o;
|
352 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001a7348" */;
|
353 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00043c5e" */;
|
354 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00042090" */;
|
355 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f6b10" */;
|
356 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0012624a" */;
|
357 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c6582" */;
|
358 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c7084" */;
|
359 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003dbfc" */;
|
360 |
19 |
simont |
endmodule
|
361 |
|
|
|
362 |
|
|
//rom7
|
363 |
|
|
module rom7 (o,a);
|
364 |
|
|
input [4:0] a;
|
365 |
|
|
output [7:0] o;
|
366 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000007de" */;
|
367 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000041e8" */;
|
368 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d3662" */;
|
369 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008001c" */;
|
370 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00039ef6" */;
|
371 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001fee62" */;
|
372 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fae62" */;
|
373 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000039f4" */;
|
374 |
19 |
simont |
endmodule
|
375 |
|
|
|
376 |
|
|
//rom8
|
377 |
|
|
module rom8 (o,a);
|
378 |
|
|
input [4:0] a;
|
379 |
|
|
output [7:0] o;
|
380 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0012e844" */;
|
381 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00022100" */;
|
382 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00180014" */;
|
383 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00190972" */;
|
384 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000b616" */;
|
385 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001fd99c" */;
|
386 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001b469c" */;
|
387 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002f02" */;
|
388 |
19 |
simont |
endmodule
|
389 |
|
|
|
390 |
|
|
//rom9
|
391 |
|
|
module rom9 (o,a);
|
392 |
|
|
input [4:0] a;
|
393 |
|
|
output [7:0] o;
|
394 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001a6068" */;
|
395 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00124138" */;
|
396 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e2048" */;
|
397 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00120000" */;
|
398 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00052c86" */;
|
399 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001f6808" */;
|
400 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e7826" */;
|
401 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002924" */;
|
402 |
19 |
simont |
endmodule
|
403 |
|
|
|
404 |
|
|
//rom10
|
405 |
|
|
module rom10 (o,a);
|
406 |
|
|
input [4:0] a;
|
407 |
|
|
output [7:0] o;
|
408 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c6b8a" */;
|
409 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e4d10" */;
|
410 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e1caa" */;
|
411 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00162300" */;
|
412 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000b9fa" */;
|
413 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e5fda" */;
|
414 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001e5dca" */;
|
415 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000be68" */;
|
416 |
19 |
simont |
endmodule
|
417 |
|
|
|
418 |
|
|
//rom11
|
419 |
|
|
module rom11 (o,a);
|
420 |
|
|
input [4:0] a;
|
421 |
|
|
output [7:0] o;
|
422 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c3f3e" */;
|
423 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00041601" */;
|
424 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00052830" */;
|
425 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0015002e" */;
|
426 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000a899" */;
|
427 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001ca8d1" */;
|
428 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001cbcd0" */;
|
429 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0001168e" */;
|
430 |
19 |
simont |
endmodule
|
431 |
|
|
|
432 |
|
|
//rom12
|
433 |
|
|
module rom12 (o,a);
|
434 |
|
|
input [4:0] a;
|
435 |
|
|
output [7:0] o;
|
436 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00020014" */;
|
437 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002824c" */;
|
438 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001b1500" */;
|
439 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080310" */;
|
440 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0011bd18" */;
|
441 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001dc32a" */;
|
442 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00196920" */;
|
443 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027e14" */;
|
444 |
19 |
simont |
endmodule
|
445 |
|
|
|
446 |
|
|
//rom13
|
447 |
|
|
module rom13 (o,a);
|
448 |
|
|
input [4:0] a;
|
449 |
|
|
output [7:0] o;
|
450 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010050a" */;
|
451 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0010520c" */;
|
452 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00150422" */;
|
453 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00151cbc" */;
|
454 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000082" */;
|
455 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001d409a" */;
|
456 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0015409a" */;
|
457 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000024c" */;
|
458 |
19 |
simont |
endmodule
|
459 |
|
|
|
460 |
|
|
//rom14
|
461 |
|
|
module rom14 (o,a);
|
462 |
|
|
input [4:0] a;
|
463 |
|
|
output [7:0] o;
|
464 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004224a" */;
|
465 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c1b0e" */;
|
466 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0050" */;
|
467 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c3a32" */;
|
468 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001103d8" */;
|
469 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001dbff0" */;
|
470 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=001c1e70" */;
|
471 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000b86e" */;
|
472 |
19 |
simont |
endmodule
|
473 |
|
|
|
474 |
|
|
//rom15
|
475 |
|
|
module rom15 (o,a);
|
476 |
|
|
input [4:0] a;
|
477 |
|
|
output [7:0] o;
|
478 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00082ffa" */;
|
479 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0014242a" */;
|
480 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0946" */;
|
481 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0014048e" */;
|
482 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000adc82" */;
|
483 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000ec9c6" */;
|
484 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000cd9e4" */;
|
485 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00006166" */;
|
486 |
19 |
simont |
endmodule
|
487 |
|
|
|
488 |
|
|
//rom16
|
489 |
|
|
module rom16 (o,a);
|
490 |
|
|
input [4:0] a;
|
491 |
|
|
output [7:0] o;
|
492 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e8002" */;
|
493 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0005a410" */;
|
494 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c1622" */;
|
495 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00092200" */;
|
496 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002cbf2" */;
|
497 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000ee75e" */;
|
498 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c4fce" */;
|
499 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00012d60" */;
|
500 |
19 |
simont |
endmodule
|
501 |
|
|
|
502 |
|
|
//rom17
|
503 |
|
|
module rom17 (o,a);
|
504 |
|
|
input [4:0] a;
|
505 |
|
|
output [7:0] o;
|
506 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000545a" */;
|
507 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000a746c" */;
|
508 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00010122" */;
|
509 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000022" */;
|
510 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00034150" */;
|
511 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b4010" */;
|
512 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00095524" */;
|
513 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000034c2" */;
|
514 |
19 |
simont |
endmodule
|
515 |
|
|
|
516 |
|
|
//rom18
|
517 |
|
|
module rom18 (o,a);
|
518 |
|
|
input [4:0] a;
|
519 |
|
|
output [7:0] o;
|
520 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e698a" */;
|
521 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00026342" */;
|
522 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c5d0e" */;
|
523 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00052942" */;
|
524 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002fcce" */;
|
525 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000bea7a" */;
|
526 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000968e8" */;
|
527 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00009cca" */;
|
528 |
19 |
simont |
endmodule
|
529 |
|
|
|
530 |
|
|
//rom19
|
531 |
|
|
module rom19 (o,a);
|
532 |
|
|
input [4:0] a;
|
533 |
|
|
output [7:0] o;
|
534 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0001ae6a" */;
|
535 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0031" */;
|
536 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00020e22" */;
|
537 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000484a8" */;
|
538 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b1ffb" */;
|
539 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b9ef7" */;
|
540 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00088a86" */;
|
541 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000108" */;
|
542 |
19 |
simont |
endmodule
|
543 |
|
|
|
544 |
|
|
//rom20
|
545 |
|
|
module rom20 (o,a);
|
546 |
|
|
input [4:0] a;
|
547 |
|
|
output [7:0] o;
|
548 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00060870" */;
|
549 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001158" */;
|
550 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00022024" */;
|
551 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00042816" */;
|
552 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002eeec" */;
|
553 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0006b4fc" */;
|
554 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004e630" */;
|
555 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00004a12" */;
|
556 |
19 |
simont |
endmodule
|
557 |
|
|
|
558 |
|
|
//rom21
|
559 |
|
|
module rom21 (o,a);
|
560 |
|
|
input [4:0] a;
|
561 |
|
|
output [7:0] o;
|
562 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00095118" */;
|
563 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00027910" */;
|
564 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f250c" */;
|
565 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d0900" */;
|
566 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000242bc" */;
|
567 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00064548" */;
|
568 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004506a" */;
|
569 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000114b0" */;
|
570 |
19 |
simont |
endmodule
|
571 |
|
|
|
572 |
|
|
//rom22
|
573 |
|
|
module rom22 (o,a);
|
574 |
|
|
input [4:0] a;
|
575 |
|
|
output [7:0] o;
|
576 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002091a" */;
|
577 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000a2190" */;
|
578 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00071002" */;
|
579 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c8e18" */;
|
580 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003d34a" */;
|
581 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007ea46" */;
|
582 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00054246" */;
|
583 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00009908" */;
|
584 |
19 |
simont |
endmodule
|
585 |
|
|
|
586 |
|
|
//rom23
|
587 |
|
|
module rom23 (o,a);
|
588 |
|
|
input [4:0] a;
|
589 |
|
|
output [7:0] o;
|
590 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000cb8cc" */;
|
591 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080d84" */;
|
592 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d25e8" */;
|
593 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b81a8" */;
|
594 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000223ee" */;
|
595 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fb7fc" */;
|
596 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000db572" */;
|
597 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000d02" */;
|
598 |
19 |
simont |
endmodule
|
599 |
|
|
|
600 |
|
|
//rom24
|
601 |
|
|
module rom24 (o,a);
|
602 |
|
|
input [4:0] a;
|
603 |
|
|
output [7:0] o;
|
604 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fe720" */;
|
605 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c0830" */;
|
606 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0004812c" */;
|
607 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00020a2a" */;
|
608 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003066c" */;
|
609 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f8f28" */;
|
610 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000c9368" */;
|
611 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000069e0" */;
|
612 |
19 |
simont |
endmodule
|
613 |
|
|
|
614 |
|
|
//rom25
|
615 |
|
|
module rom25 (o,a);
|
616 |
|
|
input [4:0] a;
|
617 |
|
|
output [7:0] o;
|
618 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00063490" */;
|
619 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00002820" */;
|
620 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00007498" */;
|
621 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080042" */;
|
622 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00082332" */;
|
623 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e5136" */;
|
624 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00065316" */;
|
625 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001d10" */;
|
626 |
19 |
simont |
endmodule
|
627 |
|
|
|
628 |
|
|
//rom26
|
629 |
|
|
module rom26 (o,a);
|
630 |
|
|
input [4:0] a;
|
631 |
|
|
output [7:0] o;
|
632 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00011a54" */;
|
633 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00033a0c" */;
|
634 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00040740" */;
|
635 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00058834" */;
|
636 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000869ba" */;
|
637 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000eca2e" */;
|
638 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00065f20" */;
|
639 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00019690" */;
|
640 |
19 |
simont |
endmodule
|
641 |
|
|
|
642 |
|
|
//rom27
|
643 |
|
|
module rom27 (o,a);
|
644 |
|
|
input [4:0] a;
|
645 |
|
|
output [7:0] o;
|
646 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000b040a" */;
|
647 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00030091" */;
|
648 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0008d40e" */;
|
649 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00004008" */;
|
650 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00099577" */;
|
651 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fc77b" */;
|
652 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0003c74a" */;
|
653 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001548" */;
|
654 |
19 |
simont |
endmodule
|
655 |
|
|
|
656 |
|
|
//rom28
|
657 |
|
|
module rom28 (o,a);
|
658 |
|
|
input [4:0] a;
|
659 |
|
|
output [7:0] o;
|
660 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000da040" */;
|
661 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00053290" */;
|
662 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0002bb40" */;
|
663 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000880a" */;
|
664 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00080ca8" */;
|
665 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000fac4e" */;
|
666 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00078ddc" */;
|
667 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0000057a" */;
|
668 |
19 |
simont |
endmodule
|
669 |
|
|
|
670 |
|
|
//rom29
|
671 |
|
|
module rom29 (o,a);
|
672 |
|
|
input [4:0] a;
|
673 |
|
|
output [7:0] o;
|
674 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00078b24" */;
|
675 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000de308" */;
|
676 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f880c" */;
|
677 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000d8414" */;
|
678 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00083156" */;
|
679 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000f8040" */;
|
680 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00079240" */;
|
681 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000043da" */;
|
682 |
19 |
simont |
endmodule
|
683 |
|
|
|
684 |
|
|
//rom30
|
685 |
|
|
module rom30 (o,a);
|
686 |
|
|
input [4:0] a;
|
687 |
|
|
output [7:0] o;
|
688 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00042152" */;
|
689 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00030f00" */;
|
690 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007c756" */;
|
691 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00050120" */;
|
692 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00000b1e" */;
|
693 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007dd5a" */;
|
694 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=0007d53a" */;
|
695 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001728" */;
|
696 |
19 |
simont |
endmodule
|
697 |
|
|
|
698 |
|
|
//rom31
|
699 |
|
|
module rom31 (o,a);
|
700 |
|
|
input [4:0] a;
|
701 |
|
|
output [7:0] o;
|
702 |
41 |
simont |
ROM32X1 u0 (o[0],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e0408" */;
|
703 |
|
|
ROM32X1 u1 (o[1],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00001140" */;
|
704 |
|
|
ROM32X1 u2 (o[2],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e20a0" */;
|
705 |
|
|
ROM32X1 u3 (o[3],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000e1200" */;
|
706 |
|
|
ROM32X1 u4 (o[4],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=00004c18" */;
|
707 |
|
|
ROM32X1 u5 (o[5],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000475ac" */;
|
708 |
|
|
ROM32X1 u6 (o[6],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000450b4" */;
|
709 |
|
|
ROM32X1 u7 (o[7],a[0],a[1],a[2],a[3],a[4]) /* synthesis xc_props="INIT=000038f2" */;
|
710 |
19 |
simont |
endmodule
|
711 |
|
|
|