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[/] [8b10b_encdec/] [trunk/] [encdec_8b10b_TB.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------
--
-- Title        : Test Bench for enc_8b10b and dec_8b10b
-- Design       : 8b-10b Encoder/Decoder Test Bench
-- Project      : 8000 - 8b10b_encdec
-- Author       : Ken Boyette
-- Company      : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File                 : encdec_8b10b_TB.vhd
-- Version              : 1.0
-- Generated    : 09.25.2006
-- From                 : y:\Projects\8000\FPGA\VHDLSource\8b10b\8b10_enc.vhd
-- By                   : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
-------------------------------------------------------------------------------
--
-- Description : Test Bench for combined enc_8b10b_tb & dec_8b10b
--
--
--      This testbench provides a sequence of data pattern stimuli for the
--      enc_8b10b component.  It latches the encoded output and provides this
--      as input to the dec_8b10b component.  The test pattern generator
--      alternately drives all data patterns and then the 12 defined K patterns.
--      
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
entity endec_8b10b_tb is
end endec_8b10b_tb;
 
architecture TB_ARCHITECTURE of endec_8b10b_tb is
 
        component enc_8b10b
        port(
                RESET : in std_logic;
                SBYTECLK : in std_logic;
                KI : in std_logic;
                AI : in std_logic;
                BI : in std_logic;
                CI : in std_logic;
                DI : in std_logic;
                EI : in std_logic;
                FI : in std_logic;
                GI : in std_logic;
                HI : in std_logic;
                AO : out std_logic;
                BO : out std_logic;
                CO : out std_logic;
                DO : out std_logic;
                EO : out std_logic;
                IO : out std_logic;
                FO : out std_logic;
                GO : out std_logic;
                HO : out std_logic;
                JO : out std_logic
                );
        end component;
 
        component dec_8b10b
        port(
                RESET : in std_logic;
                RBYTECLK : in std_logic;
                AI : in std_logic;
                BI : in std_logic;
                CI : in std_logic;
                DI : in std_logic;
                EI : in std_logic;
                II : in std_logic;
                FI : in std_logic;
                GI : in std_logic;
                HI : in std_logic;
                JI : in std_logic;
                AO : out std_logic;
                BO : out std_logic;
                CO : out std_logic;
                DO : out std_logic;
                EO : out std_logic;
                FO : out std_logic;
                GO : out std_logic;
                HO : out std_logic;
                KO : out std_logic
                );
        end component;
 
        -- Special character code values
        constant K28d0 : std_logic_vector := "00011100"; -- Balanced
        constant K28d1 : std_logic_vector := "00111100"; -- Unbalanced comma
        constant K28d2 : std_logic_vector := "01011100"; -- Unbalanced
        constant K28d3 : std_logic_vector := "01111100"; -- Unbalanced
        constant K28d4 : std_logic_vector := "10011100"; -- Balanced
        constant K28d5 : std_logic_vector := "10111100"; -- Unbalanced comma
        constant K28d6 : std_logic_vector := "11011100"; -- Unbalanced
        constant K28d7 : std_logic_vector := "11111100"; -- Balanced comma
        constant K23d7 : std_logic_vector := "11110111"; -- Balanced
        constant K27d7 : std_logic_vector := "11111011"; -- Balanced
        constant K29d7 : std_logic_vector := "11111101"; -- Balanced
        constant K30d7 : std_logic_vector := "11111110"; -- Balanced
 
        -- Stimulus signals - mapped to the input  of enc_8b10b
        signal TRESET : std_logic;
        signal TBYTECLK : std_logic;
        signal TKO : std_logic;
        signal TAO : std_logic;
        signal TBO : std_logic;
        signal TCO : std_logic;
        signal TDO : std_logic;
        signal TEO : std_logic;
        signal TFO : std_logic;
        signal TGO : std_logic;
        signal THO : std_logic;
 
        -- Observed signals - mapped from output of enc_8b10b
        signal TA : std_logic;
        signal TB : std_logic;
        signal TC : std_logic;
        signal TD : std_logic;
        signal TE : std_logic;
        signal TF : std_logic;
        signal TI : std_logic;
        signal TG : std_logic;
        signal TH : std_logic;
        signal TJ : std_logic;
 
        -- Observed signals - mapped from output of dec_8b10b
        signal TDA : std_logic;
        signal TDB : std_logic;
        signal TDC : std_logic;
        signal TDD : std_logic;
        signal TDE : std_logic;
        signal TDF : std_logic;
        signal TDG : std_logic;
        signal TDH : std_logic;
        signal TDK : std_logic;
 
        -- Signals for TestBench control functions
        signal tchar : std_logic_vector (7 downto 0) ;           -- All character vector
        signal kcounter : std_logic_vector (3 downto 0) ;        -- K character counter
        signal dcounter : std_logic_vector (7 downto 0) ;        -- D value counter
        signal tcharout, tlcharout : std_logic_vector (9 downto 0) ;     -- Character output vector
        signal tclken : std_logic ; -- Enables clock after short delay starting up
        signal tcnten : std_logic ; -- Enables count after 1 cycle
        signal tks : std_logic ; -- Use to select control function of encoder
        signal dk : std_logic ; -- '0' if D, '1' if K
        signal tdec : std_logic_vector (7 downto 0) ;    -- Decoder output monitor
        signal tdeck : std_logic ; -- Decoder K output monitor
begin
        ---------------------------------------------------------------------------
        -- Instantiate modules
        ---------------------------------------------------------------------------
        encoder : enc_8b10b
                port map (
                        RESET => TRESET,
                        SBYTECLK => TBYTECLK,
                        KI => TKO,
                        AI => TAO,
                        BI => TBO,
                        CI => TCO,
                        DI => TDO,
                        EI => TEO,
                        FI => TFO,
                        GI => TGO,
                        HI => THO,
                        AO => TA,
                        BO => TB,
                        CO => TC,
                        DO => TD,
                        EO => TE,
                        IO => TI,
                        FO => TF,
                        GO => TG,
                        HO => TH,
                        JO => TJ
                );
        decoder : dec_8b10b
                port map (
                        RESET => TRESET,
                        RBYTECLK => TBYTECLK,
                        AI => tlcharout(0),      -- Note: Use the latched encoded data
                        BI => tlcharout(1),
                        CI => tlcharout(2),
                        DI => tlcharout(3),
                        EI => tlcharout(4),
                        II => tlcharout(5),
                        FI => tlcharout(6),
                        GI => tlcharout(7),
                        HI => tlcharout(8),
                        JI => tlcharout(9),
                        AO => TDA,
                        BO => TDB,
                        CO => TDC,
                        DO => TDD,
                        EO => TDE,
                        FO => TDF,
                        GO => TDG,
                        HO => TDH,
                        KO => TDK
                );
 
TRESET <= '1', '0' after 200 ns ; -- Start with a valid reset for 100ns
tclken <= '0', '1' after 10 ns ; -- Start clock with valid state, then 10MHz
 
process (TBYTECLK, tclken)
begin
        If (tclken = '0') then
                TBYTECLK <= '0';
        else TBYTECLK <= (not TBYTECLK) after 50 ns ;   -- Generate 10MHz byte clock
        end if;
end process ;
 
process (TRESET, TBYTECLK)
begin
        if (TRESET = '1') then  -- Delay count 1 cycle 
                tcnten <= '0' ;
        elsif (TBYTECLK'event and TBYTECLK = '0') then
                tcnten <= '1' ;
        end if ;
end process ;
 
process (TRESET, TBYTECLK, tks, tcnten, kcounter, dcounter, tchar)
begin
        if (TRESET = '1') then
                tchar <= "00000000" ;
                tks <= '1' ; -- Set for K initially
                dk <= '0' ;
                kcounter <= "0000" ; -- Preset K counter
                dcounter <= "00000000" ;        -- Preset D counter
        elsif (TBYTECLK'event and TBYTECLK = '1') then
                dk <= tks ;
                if tks = '1' then       -- Output K characters
                        kcounter <= kcounter + tcnten ; -- Increment counter
                        dcounter <= "00000000" ;
                        case kcounter is
                                when "0000" => tchar <= K28d0 ;
                                when "0001" => tchar <= K28d1 ;
                                when "0010" => tchar <= K28d2 ;
                                when "0011" => tchar <= K28d3 ;
                                when "0100" => tchar <= K28d4 ;
                                when "0101" => tchar <= K28d5 ;
                                when "0110" => tchar <= K28d6 ;
                                when "0111" => tchar <= K28d7 ;
                                when "1000" => tchar <= K23d7 ;
                                when "1001" => tchar <= K27d7 ;
                                when "1010" => tchar <= K29d7 ;
                                when "1011" => tchar <= K30d7 ;
                                        tks <= '0' ;     -- Switch to D output
                                when "1100" => tchar <= "00000000" ;
                                when others => tchar(7 downto 0) <= K28d5 ;
                        end case;
                else dcounter <= dcounter + tcnten ;    -- Output D values
                        tchar <= dcounter ;
                        if dcounter = "11111111" then
                                tks <= '1' ;    -- Repeat K portion
                                kcounter <= "0000" ; -- Reset K counter
                        end if;
                end if ;
        end if;
end process ;
 
-- Latch encoder output each rising edge for simulation and input into decoder
process (TBYTECLK)
begin
        if (TBYTECLK'event and TBYTECLK = '1') then
                tlcharout(0) <= TA;
                tlcharout(1) <= TB;
                tlcharout(2) <= TC;
                tlcharout(3) <= TD;
                tlcharout(4) <= TE;
                tlcharout(5) <= TI;
                tlcharout(6) <= TF;
                tlcharout(7) <= TG;
                tlcharout(8) <= TH;
                tlcharout(9) <= TJ;
        end if;
end process ;
 
-- Connect our test values to the encoder inputs
TAO <= tchar(0);
TBO <= tchar(1);
TCO <= tchar(2);
TDO <= tchar(3);
TEO <= tchar(4);
TFO <= tchar(5);
TGO <= tchar(6);
THO <= tchar(7);
TKO <= dk;
 
-- Monitor encoder output
tcharout(0) <= TA;
tcharout(1) <= TB;
tcharout(2) <= TC;
tcharout(3) <= TD;
tcharout(4) <= TE;
tcharout(5) <= TI;
tcharout(6) <= TF;
tcharout(7) <= TG;
tcharout(8) <= TH;
tcharout(9) <= TJ;
 
-- Monitor decoder output
tdec(0) <= TDA;
tdec(1) <= TDB;
tdec(2) <= TDC;
tdec(3) <= TDD;
tdec(4) <= TDE;
tdec(5) <= TDF;
tdec(6) <= TDG;
tdec(7) <= TDH;
tdeck <= TDK;
 
end TB_ARCHITECTURE;
 
 

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Subversion Repositories 8b10b_encdec

[/] [8b10b_encdec/] [trunk/] [encdec_8b10b_TB.vhd] - Blame information for rev 3

Line No.	Rev	Author	Line
1	2	kboyette	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Title : Test Bench for enc_8b10b and dec_8b10b`
4			`-- Design : 8b-10b Encoder/Decoder Test Bench`
5			`-- Project : 8000 - 8b10b_encdec`
6			`-- Author : Ken Boyette`
7			`-- Company : Critia Computer, Inc.`
8			`--`
9			`-------------------------------------------------------------------------------`
10			`--`
11			`-- File : encdec_8b10b_TB.vhd`
12			`-- Version : 1.0`
13			`-- Generated : 09.25.2006`
14			`-- From : y:\Projects\8000\FPGA\VHDLSource\8b10b\8b10_enc.vhd`
15			`-- By : Active-HDL Built-in Test Bench Generator ver. 1.2s`
16			`--`
17			`-------------------------------------------------------------------------------`
18			`--`
19			`-- Description : Test Bench for combined enc_8b10b_tb & dec_8b10b`
20			`--`
21			`--`
22			`-- This testbench provides a sequence of data pattern stimuli for the`
23			`-- enc_8b10b component. It latches the encoded output and provides this`
24			`-- as input to the dec_8b10b component. The test pattern generator`
25			`-- alternately drives all data patterns and then the 12 defined K patterns.`
26			`--`
27			`-------------------------------------------------------------------------------`
28			`-- This program is licensed under the GPL`
29			`-------------------------------------------------------------------------------`
30
31			`library ieee;`
32			`use ieee.std_logic_1164.all;`
33			`use ieee.std_logic_unsigned.all;`
34
35			`entity endec_8b10b_tb is`
36			`end endec_8b10b_tb;`
37
38			`architecture TB_ARCHITECTURE of endec_8b10b_tb is`
39
40			`component enc_8b10b`
41			`port(`
42			`RESET : in std_logic;`
43			`SBYTECLK : in std_logic;`
44			`KI : in std_logic;`
45			`AI : in std_logic;`
46			`BI : in std_logic;`
47			`CI : in std_logic;`
48			`DI : in std_logic;`
49			`EI : in std_logic;`
50			`FI : in std_logic;`
51			`GI : in std_logic;`
52			`HI : in std_logic;`
53			`AO : out std_logic;`
54			`BO : out std_logic;`
55			`CO : out std_logic;`
56			`DO : out std_logic;`
57			`EO : out std_logic;`
58			`IO : out std_logic;`
59			`FO : out std_logic;`
60			`GO : out std_logic;`
61			`HO : out std_logic;`
62			`JO : out std_logic`
63			`);`
64			`end component;`
65
66			`component dec_8b10b`
67			`port(`
68			`RESET : in std_logic;`
69			`RBYTECLK : in std_logic;`
70			`AI : in std_logic;`
71			`BI : in std_logic;`
72			`CI : in std_logic;`
73			`DI : in std_logic;`
74			`EI : in std_logic;`
75			`II : in std_logic;`
76			`FI : in std_logic;`
77			`GI : in std_logic;`
78			`HI : in std_logic;`
79			`JI : in std_logic;`
80			`AO : out std_logic;`
81			`BO : out std_logic;`
82			`CO : out std_logic;`
83			`DO : out std_logic;`
84			`EO : out std_logic;`
85			`FO : out std_logic;`
86			`GO : out std_logic;`
87			`HO : out std_logic;`
88			`KO : out std_logic`
89			`);`
90			`end component;`
91
92			`-- Special character code values`
93			`constant K28d0 : std_logic_vector := "00011100"; -- Balanced`
94			`constant K28d1 : std_logic_vector := "00111100"; -- Unbalanced comma`
95			`constant K28d2 : std_logic_vector := "01011100"; -- Unbalanced`
96			`constant K28d3 : std_logic_vector := "01111100"; -- Unbalanced`
97			`constant K28d4 : std_logic_vector := "10011100"; -- Balanced`
98			`constant K28d5 : std_logic_vector := "10111100"; -- Unbalanced comma`
99			`constant K28d6 : std_logic_vector := "11011100"; -- Unbalanced`
100			`constant K28d7 : std_logic_vector := "11111100"; -- Balanced comma`
101			`constant K23d7 : std_logic_vector := "11110111"; -- Balanced`
102			`constant K27d7 : std_logic_vector := "11111011"; -- Balanced`
103			`constant K29d7 : std_logic_vector := "11111101"; -- Balanced`
104			`constant K30d7 : std_logic_vector := "11111110"; -- Balanced`
105
106			`-- Stimulus signals - mapped to the input of enc_8b10b`
107			`signal TRESET : std_logic;`
108			`signal TBYTECLK : std_logic;`
109			`signal TKO : std_logic;`
110			`signal TAO : std_logic;`
111			`signal TBO : std_logic;`
112			`signal TCO : std_logic;`
113			`signal TDO : std_logic;`
114			`signal TEO : std_logic;`
115			`signal TFO : std_logic;`
116			`signal TGO : std_logic;`
117			`signal THO : std_logic;`
118
119			`-- Observed signals - mapped from output of enc_8b10b`
120			`signal TA : std_logic;`
121			`signal TB : std_logic;`
122			`signal TC : std_logic;`
123			`signal TD : std_logic;`
124			`signal TE : std_logic;`
125			`signal TF : std_logic;`
126			`signal TI : std_logic;`
127			`signal TG : std_logic;`
128			`signal TH : std_logic;`
129			`signal TJ : std_logic;`
130
131			`-- Observed signals - mapped from output of dec_8b10b`
132			`signal TDA : std_logic;`
133			`signal TDB : std_logic;`
134			`signal TDC : std_logic;`
135			`signal TDD : std_logic;`
136			`signal TDE : std_logic;`
137			`signal TDF : std_logic;`
138			`signal TDG : std_logic;`
139			`signal TDH : std_logic;`
140			`signal TDK : std_logic;`
141
142			`-- Signals for TestBench control functions`
143			`signal tchar : std_logic_vector (7 downto 0) ; -- All character vector`
144			`signal kcounter : std_logic_vector (3 downto 0) ; -- K character counter`
145			`signal dcounter : std_logic_vector (7 downto 0) ; -- D value counter`
146			`signal tcharout, tlcharout : std_logic_vector (9 downto 0) ; -- Character output vector`
147			`signal tclken : std_logic ; -- Enables clock after short delay starting up`
148			`signal tcnten : std_logic ; -- Enables count after 1 cycle`
149			`signal tks : std_logic ; -- Use to select control function of encoder`
150			`signal dk : std_logic ; -- '0' if D, '1' if K`
151			`signal tdec : std_logic_vector (7 downto 0) ; -- Decoder output monitor`
152			`signal tdeck : std_logic ; -- Decoder K output monitor`
153			`begin`
154			`---------------------------------------------------------------------------`
155			`-- Instantiate modules`
156			`---------------------------------------------------------------------------`
157			`encoder : enc_8b10b`
158			`port map (`
159			`RESET => TRESET,`
160			`SBYTECLK => TBYTECLK,`
161			`KI => TKO,`
162			`AI => TAO,`
163			`BI => TBO,`
164			`CI => TCO,`
165			`DI => TDO,`
166			`EI => TEO,`
167			`FI => TFO,`
168			`GI => TGO,`
169			`HI => THO,`
170			`AO => TA,`
171			`BO => TB,`
172			`CO => TC,`
173			`DO => TD,`
174			`EO => TE,`
175			`IO => TI,`
176			`FO => TF,`
177			`GO => TG,`
178			`HO => TH,`
179			`JO => TJ`
180			`);`
181			`decoder : dec_8b10b`
182			`port map (`
183			`RESET => TRESET,`
184			`RBYTECLK => TBYTECLK,`
185			`AI => tlcharout(0), -- Note: Use the latched encoded data`
186			`BI => tlcharout(1),`
187			`CI => tlcharout(2),`
188			`DI => tlcharout(3),`
189			`EI => tlcharout(4),`
190			`II => tlcharout(5),`
191			`FI => tlcharout(6),`
192			`GI => tlcharout(7),`
193			`HI => tlcharout(8),`
194			`JI => tlcharout(9),`
195			`AO => TDA,`
196			`BO => TDB,`
197			`CO => TDC,`
198			`DO => TDD,`
199			`EO => TDE,`
200			`FO => TDF,`
201			`GO => TDG,`
202			`HO => TDH,`
203			`KO => TDK`
204			`);`
205
206			`TRESET <= '1', '0' after 200 ns ; -- Start with a valid reset for 100ns`
207			`tclken <= '0', '1' after 10 ns ; -- Start clock with valid state, then 10MHz`
208
209			`process (TBYTECLK, tclken)`
210			`begin`
211			`If (tclken = '0') then`
212			`TBYTECLK <= '0';`
213			`else TBYTECLK <= (not TBYTECLK) after 50 ns ; -- Generate 10MHz byte clock`
214			`end if;`
215			`end process ;`
216
217			`process (TRESET, TBYTECLK)`
218			`begin`
219			`if (TRESET = '1') then -- Delay count 1 cycle`
220			`tcnten <= '0' ;`
221			`elsif (TBYTECLK'event and TBYTECLK = '0') then`
222			`tcnten <= '1' ;`
223			`end if ;`
224			`end process ;`
225
226			`process (TRESET, TBYTECLK, tks, tcnten, kcounter, dcounter, tchar)`
227			`begin`
228			`if (TRESET = '1') then`
229			`tchar <= "00000000" ;`
230			`tks <= '1' ; -- Set for K initially`
231			`dk <= '0' ;`
232			`kcounter <= "0000" ; -- Preset K counter`
233			`dcounter <= "00000000" ; -- Preset D counter`
234			`elsif (TBYTECLK'event and TBYTECLK = '1') then`
235			`dk <= tks ;`
236			`if tks = '1' then -- Output K characters`
237			`kcounter <= kcounter + tcnten ; -- Increment counter`
238			`dcounter <= "00000000" ;`
239			`case kcounter is`
240			`when "0000" => tchar <= K28d0 ;`
241			`when "0001" => tchar <= K28d1 ;`
242			`when "0010" => tchar <= K28d2 ;`
243			`when "0011" => tchar <= K28d3 ;`
244			`when "0100" => tchar <= K28d4 ;`
245			`when "0101" => tchar <= K28d5 ;`
246			`when "0110" => tchar <= K28d6 ;`
247			`when "0111" => tchar <= K28d7 ;`
248			`when "1000" => tchar <= K23d7 ;`
249			`when "1001" => tchar <= K27d7 ;`
250			`when "1010" => tchar <= K29d7 ;`
251			`when "1011" => tchar <= K30d7 ;`
252			`tks <= '0' ; -- Switch to D output`
253			`when "1100" => tchar <= "00000000" ;`
254			`when others => tchar(7 downto 0) <= K28d5 ;`
255			`end case;`
256			`else dcounter <= dcounter + tcnten ; -- Output D values`
257			`tchar <= dcounter ;`
258			`if dcounter = "11111111" then`
259			`tks <= '1' ; -- Repeat K portion`
260			`kcounter <= "0000" ; -- Reset K counter`
261			`end if;`
262			`end if ;`
263			`end if;`
264			`end process ;`
265
266			`-- Latch encoder output each rising edge for simulation and input into decoder`
267			`process (TBYTECLK)`
268			`begin`
269			`if (TBYTECLK'event and TBYTECLK = '1') then`
270			`tlcharout(0) <= TA;`
271			`tlcharout(1) <= TB;`
272			`tlcharout(2) <= TC;`
273			`tlcharout(3) <= TD;`
274			`tlcharout(4) <= TE;`
275			`tlcharout(5) <= TI;`
276			`tlcharout(6) <= TF;`
277			`tlcharout(7) <= TG;`
278			`tlcharout(8) <= TH;`
279			`tlcharout(9) <= TJ;`
280			`end if;`
281			`end process ;`
282
283			`-- Connect our test values to the encoder inputs`
284			`TAO <= tchar(0);`
285			`TBO <= tchar(1);`
286			`TCO <= tchar(2);`
287			`TDO <= tchar(3);`
288			`TEO <= tchar(4);`
289			`TFO <= tchar(5);`
290			`TGO <= tchar(6);`
291			`THO <= tchar(7);`
292			`TKO <= dk;`
293
294			`-- Monitor encoder output`
295			`tcharout(0) <= TA;`
296			`tcharout(1) <= TB;`
297			`tcharout(2) <= TC;`
298			`tcharout(3) <= TD;`
299			`tcharout(4) <= TE;`
300			`tcharout(5) <= TI;`
301			`tcharout(6) <= TF;`
302			`tcharout(7) <= TG;`
303			`tcharout(8) <= TH;`
304			`tcharout(9) <= TJ;`
305
306			`-- Monitor decoder output`
307			`tdec(0) <= TDA;`
308			`tdec(1) <= TDB;`
309			`tdec(2) <= TDC;`
310			`tdec(3) <= TDD;`
311			`tdec(4) <= TDE;`
312			`tdec(5) <= TDF;`
313			`tdec(6) <= TDG;`
314			`tdec(7) <= TDH;`
315			`tdeck <= TDK;`
316
317			`end TB_ARCHITECTURE;`
318
319