OpenCores
URL https://opencores.org/ocsvn/Aquarius/Aquarius/trunk

Subversion Repositories Aquarius

[/] [Aquarius/] [trunk/] [verification/] [sha_testsource/] [testdiv.src] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 thorn_aitc 
/*
2 
===================
3 
test source program
4 
testdiv.src
5 
 
6 
Jan.28 2003
7 
===================
8 
 
9 
address           size wait width device
10 
00000000-00001FFF  8K  0    32    ROM
11 
00010000-00011FFF  8K  3    32    ROM
12 
00020000-00021FFF  8K  0    16    ROM
13 
00030000-00031FFF  8K  3    16    ROM
14 
ABCD0000-ABCD0003   4  3    32    PIO
15 
ABCD0100-ABCD0103   4  3    32    UART
16 
ABCD0200-ABCD0207   8  3    32    SYS
17 
FFFCE000-FFFCFFFF  8K  0    32    RAM
18 
FFFDE000-FFFDFFFF  8K  3    32    RAM
19 
FFFEE000-FFFEFFFF  8K  0    16    RAM
20 
FFFFE000-FFFFFFFF  8K  3    16    RAM
21 
*/
22 
 
23 
.equ _rom0, 0x00000000
24 
.equ _rom1, 0x00010000
25 
.equ _rom2, 0x00020000
26 
.equ _rom3, 0x00030000
27 
.equ _pio,  0xabcd0000
28 
.equ _uart, 0xabcd0100
29 
.equ _sys,  0xabcd0200
30 
.equ _ram0, 0xfffce000
31 
.equ _ram1, 0xfffde000
32 
.equ _ram2, 0xfffee000
33 
.equ _ram3, 0xffffe000
34 
 
35 
.org _rom0
36 
.long _rom0 + _init - _rom0
37 
.long _ram0 + 0x02000
38 
 
39 
.org 0x0400
40 
 
41 
/**************
42 
 Initialization
43 
 **************/
44 
_init:
45 
_start:
46 
 mov    #0, r14
47 
_test:
48 
 mov.l  _pfail, r13 !fail address
49 
 bra    _testgo
50 
 nop
51 
_pfail: .long _fail
52 
 
53 
_testgo:
54 
 mov.l  _ptestvalue, r9
55 
/******************************************
56 
 Unsigned R1(32bit) / R0(16bit) -> R1(16bit)
57 
 ******************************************/
58 
 mov.l @r9+, r1
59 
 mov.l @r9+, r0
60 
 div0u
61 
 div1 r0, r1
62 
 div1 r0, r1
63 
 div1 r0, r1
64 
 div1 r0, r1
65 
 div1 r0, r1
66 
 div1 r0, r1
67 
 div1 r0, r1
68 
 div1 r0, r1
69 
 div1 r0, r1
70 
 div1 r0, r1
71 
 div1 r0, r1
72 
 div1 r0, r1
73 
 div1 r0, r1
74 
 div1 r0, r1
75 
 div1 r0, r1
76 
 div1 r0, r1
77 
 rotcl r1
78 
 mov.l @r9+, r2
79 
 cmp/eq r2, r1
80 
 bt     .+6
81 
 jmp    @r13
82 
 nop
83 
/**********************************************
84 
 Unsigned R1:R2(64bit) / R0(32bit) -> R2(32bit)
85 
 **********************************************/
86 
 mov.l @r9+, r1
87 
 mov.l @r9+, r2
88 
 mov.l @r9+, r0
89 
 div0u
90 
 rotcl r2
91 
 div1  r0,r1
92 
 rotcl r2
93 
 div1  r0,r1
94 
 rotcl r2
95 
 div1  r0,r1
96 
 rotcl r2
97 
 div1  r0,r1
98 
 rotcl r2
99 
 div1  r0,r1
100 
 rotcl r2
101 
 div1  r0,r1
102 
 rotcl r2
103 
 div1  r0,r1
104 
 rotcl r2
105 
 div1  r0,r1
106 
 
107 
 rotcl r2
108 
 div1  r0,r1
109 
 rotcl r2
110 
 div1  r0,r1
111 
 rotcl r2
112 
 div1  r0,r1
113 
 rotcl r2
114 
 div1  r0,r1
115 
 rotcl r2
116 
 div1  r0,r1
117 
 rotcl r2
118 
 div1  r0,r1
119 
 rotcl r2
120 
 div1  r0,r1
121 
 rotcl r2
122 
 div1  r0,r1
123 
 
124 
 rotcl r2
125 
 div1  r0,r1
126 
 rotcl r2
127 
 div1  r0,r1
128 
 rotcl r2
129 
 div1  r0,r1
130 
 rotcl r2
131 
 div1  r0,r1
132 
 rotcl r2
133 
 div1  r0,r1
134 
 rotcl r2
135 
 div1  r0,r1
136 
 rotcl r2
137 
 div1  r0,r1
138 
 rotcl r2
139 
 div1  r0,r1
140 
 
141 
 rotcl r2
142 
 div1  r0,r1
143 
 rotcl r2
144 
 div1  r0,r1
145 
 rotcl r2
146 
 div1  r0,r1
147 
 rotcl r2
148 
 div1  r0,r1
149 
 rotcl r2
150 
 div1  r0,r1
151 
 rotcl r2
152 
 div1  r0,r1
153 
 rotcl r2
154 
 div1  r0,r1
155 
 rotcl r2
156 
 div1  r0,r1
157 
 
158 
 rotcl r2
159 
 mov.l @r9+, r3
160 
 cmp/eq r3, r2
161 
 bt     .+6
162 
 jmp    @r13
163 
 nop
164 
/*****************************************
165 
 Signed R1(16bit) / R0(16bit) -> R1(16bit)
166 
 *****************************************/
167 
 mov.l @r9+, r1
168 
 mov.l @r9+, r0
169 
 div0s r0, r1
170 
 div1  r0, r1
171 
 div1  r0, r1
172 
 div1  r0, r1
173 
 div1  r0, r1
174 
 div1  r0, r1
175 
 div1  r0, r1
176 
 div1  r0, r1
177 
 div1  r0, r1
178 
 div1  r0, r1
179 
 div1  r0, r1
180 
 div1  r0, r1
181 
 div1  r0, r1
182 
 div1  r0, r1
183 
 div1  r0, r1
184 
 div1  r0, r1
185 
 div1  r0, r1
186 
 mov.l @r9+, r2
187 
 cmp/eq r2, r1
188 
 bt     .+6
189 
 jmp    @r13
190 
 nop
191 
/*****************************************
192 
 Signed R2(32bit) / R0(32bit) -> R2(32bit)
193 
 *****************************************/
194 
 mov.l @r9+, r1
195 
 mov.l @r9+, r2
196 
 mov.l @r9+, r0
197 
 div0s r0, r1
198 
 rotcl r2
199 
 div1  r0, r1
200 
 rotcl r2
201 
 div1  r0, r1
202 
 rotcl r2
203 
 div1  r0, r1
204 
 rotcl r2
205 
 div1  r0, r1
206 
 rotcl r2
207 
 div1  r0, r1
208 
 rotcl r2
209 
 div1  r0, r1
210 
 rotcl r2
211 
 div1  r0, r1
212 
 rotcl r2
213 
 div1  r0, r1
214 
 
215 
 rotcl r2
216 
 div1  r0, r1
217 
 rotcl r2
218 
 div1  r0, r1
219 
 rotcl r2
220 
 div1  r0, r1
221 
 rotcl r2
222 
 div1  r0, r1
223 
 rotcl r2
224 
 div1  r0, r1
225 
 rotcl r2
226 
 div1  r0, r1
227 
 rotcl r2
228 
 div1  r0, r1
229 
 rotcl r2
230 
 div1  r0, r1
231 
 
232 
 rotcl r2
233 
 div1  r0, r1
234 
 rotcl r2
235 
 div1  r0, r1
236 
 rotcl r2
237 
 div1  r0, r1
238 
 rotcl r2
239 
 div1  r0, r1
240 
 rotcl r2
241 
 div1  r0, r1
242 
 rotcl r2
243 
 div1  r0, r1
244 
 rotcl r2
245 
 div1  r0, r1
246 
 rotcl r2
247 
 div1  r0, r1
248 
 
249 
 rotcl r2
250 
 div1  r0, r1
251 
 rotcl r2
252 
 div1  r0, r1
253 
 rotcl r2
254 
 div1  r0, r1
255 
 rotcl r2
256 
 div1  r0, r1
257 
 rotcl r2
258 
 div1  r0, r1
259 
 rotcl r2
260 
 div1  r0, r1
261 
 rotcl r2
262 
 div1  r0, r1
263 
 rotcl r2
264 
 div1  r0, r1
265 
 
266 
 rotcl r2
267 
 mov.l @r9+, r3
268 
 cmp/eq r3, r2
269 
 bt     .+6
270 
 jmp    @r13
271 
 nop
272 
!----
273 
 bra    _testfinish
274 
 nop
275 
!----
276 
 .align 4
277 
_ptestvalue: .long _testvalue
278 
_testvalue :
279 
!----32 by 16 unsigned
280 
 .long 0x71c638e4
281 
 .long 0xaaaa0000
282 
 .long 0xaaacaaaa
283 
!----64 by 32 unsigned
284 
 .long 0x0b00ea4e
285 
 .long 0x242d2080
286 
 .long 0x9abcdef0
287 
 .long 0x12345678
288 
!----16 by 16 signed
289 
 .long 0xfffffeff !=ffffff00-1
290 
 .long 0x00100000
291 
 .long 0x000ffff7
292 
!----32 by 32 signed
293 
 .long 0xffffffff
294 
 .long 0xdb97530f
295 
 .long 0xfffffffe
296 
 .long 0x12345678
297 
 
298 
_testfinish:
299 
/*********************************************************
300 
 Move to another Next ROM area to check hardware operation
301 
 *********************************************************/
302 
 mov.l _pbranch_table, r13
303 
 add r14, r13
304 
 mov.l @r13, r12
305 
 jmp @r12
306 
 add #4, r14
307 
.align 4
308 
_pbranch_table: .long _branch_table
309 
_branch_table:
310 
 .long _rom1+_test
311 
 .long _rom2+_test
312 
 .long _rom3+_test
313 
 .long _rom0+_pass
314 
 
315 
/**************
316 
 Congraturation
317 
 **************/
318 
_pass:
319 
 mov.l _ppass_value, r0
320 
 mov.l _ppass_value, r1
321 
 mov.l r0, @r1
322 
 bra   _pass
323 
 nop
324 
.align 4
325 
_ppass_value: .long 0x12345678
326 
 
327 
/**********
328 
 You Failed
329 
 **********/
330 
_fail:
331 
 mov.l _pfail_value, r0
332 
 mov.l _pfail_value, r1
333 
 bra   _fail
334 
 nop
335 
.align 4
336 
_pfail_value: .long 0x88888888
337 
 
338 
.end

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.