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1 2 thorn_aitc 
//======================================================
2 
// Aquarius Project
3 
//    SuperH-2 ISA Compatible RISC CPU
4 
//------------------------------------------------------
5 
// Module      : Decode Unit
6 
//------------------------------------------------------
7 
// File        : decode.v
8 
// Library     : none
9 
// Description : Decode Unit in CPU.
10 
// Simulator   : Icarus Verilog (Cygwin)
11 
// Synthesizer : Xilinx XST (Windows XP)
12 
// Author      : Thorn Aitch
13 
//------------------------------------------------------
14 
// Revision Number : 1
15 
// Date of Change  : 8th April 2002
16 
// Creator         : Thorn Aitch
17 
// Description     : Initial Design
18 
//------------------------------------------------------
19 
// Revision Number : 2
20 
// Date of Change  : 11th August 2002
21 
// Modifier        : Thorn Aitch
22 
// Description     : Have Checked Memory Controller I/F
23 
//------------------------------------------------------
24 
// Revision Number : 3
25 
// Date of Change  : 30th April 2003
26 
// Modifier        : Thorn Aitch
27 11 thorn_aitc 
// Description     : Release Version 1.0
28 
//------------------------------------------------------
29 
// Revision Number : 4
30 
// Date of Change  : 10th December 2003
31 
// Modifier        : Thorn Aitch
32 
// Description     : Release Version 1.1
33 
//                   Inhibit substitution of "x"
34 
//                   except for defalut statement whose
35 
//                   case describes all logic spaces.
36 2 thorn_aitc 
//======================================================
37 
// Copyright (C) 2002-2003, Thorn Aitch
38 
//
39 
// Designs can be altered while keeping list of
40 
// modifications "the same as in GNU" No money can
41 
// be earned by selling the designs themselves, but
42 
// anyone can get money by selling the implementation
43 
// of the design, such as ICs based on some cores,
44 
// boards based on some schematics or Layouts, and
45 
// even GUI interfaces to text mode drivers.
46 
// "The same as GPL SW" Any update to the design
47 
// should be documented and returned to the design.
48 
// Any derivative work based on the IP should be free
49 
// under OpenIP License. Derivative work means any
50 
// update, change or improvement on the design.
51 
// Any work based on the design can be either made
52 
// free under OpenIP license or protected by any other
53 
// license. Work based on the design means any work uses
54 
// the OpenIP Licensed core as a building black without
55 
// changing anything on it with any other blocks to
56 
// produce larger design.  There is NO WARRANTY on the
57 
// functionality or performance of the design on the
58 
// real hardware implementation.
59 
// On the other hand, the SuperH-2 ISA (Instruction Set
60 
// Architecture) executed by Aquarius is rigidly
61 
// the property of Renesas Corp. Then you have all
62 
// responsibility to judge if there are not any
63 
// infringements to Renesas's rights regarding your
64 
// Aquarius adoption into your design.
65 
// By adopting Aquarius, the user assumes all
66 
// responsibility for its use.
67 
// This project may cause any damages around you, for
68 
// example, loss of properties, data, money, profits,
69 
// life, or business etc. By adopting this source,
70 
// the user assumes all responsibility for its use.
71 
//======================================================
72 
 
73 
`include "timescale.v"
74 
`include "defines.v"
75 
 
76 
//*************************************************
77 
// Module Definition
78 
//*************************************************
79 
module decode(
80 
    // system signal
81 
    CLK, RST, SLOT,
82 
    // instruction fetch control
83 
    IF_ISSUE, IF_JP,
84 
    IF_DR, IF_BUS, IF_STALL,
85 
    // data access control
86 
    MA_ISSUE, KEEP_CYC, MA_WR, MA_SZ,
87 
    //
88 
    // multplier
89 
    //
90 
    // mult command
91 
    MULCOM1, MULCOM2, WRMACH, WRMACL,
92 
    // mult busy signal
93 
    MAC_BUSY,
94 
    //
95 
    // data path
96 
    //
97 
    // general register
98 
    RDREG_X,  RDREG_Y,  WRREG_Z,  WRREG_W,
99 
    REGNUM_X, REGNUM_Y, REGNUM_Z, REGNUM_W,
100 
    // ALU function
101 
    ALUFUNC,
102 
    // memory access
103 
    WRMAAD_Z, WRMADW_X, WRMADW_Y, RDMADR_W,
104 
    // mult
105 
    MACSEL1, MACSEL2,
106 
    RDMACH_X, RDMACL_X,
107 
    RDMACH_Y, RDMACL_Y,
108 
    // status register
109 
    RDSR_X, RDSR_Y,
110 
    WRSR_Z, WRSR_W,
111 
    // S bit for MAC
112 
    MAC_S_LATCH,
113 
    // global base register
114 
    RDGBR_X, RDGBR_Y,
115 
    WRGBR_Z, WRGBR_W,
116 
    // vector base register
117 
    RDVBR_X, RDVBR_Y,
118 
    WRVBR_Z, WRVBR_W,
119 
    // procedure register
120 
    RDPR_X, RDPR_Y,
121 
    WRPR_Z, WRPR_W, WRPR_PC,
122 
    // program counter
123 
    RDPC_X, RDPC_Y, WRPC_Z,
124 
    INCPC, IFADSEL,
125 
    // make constant
126 
    CONST_IFDR,
127 
    CONST_ZERO4, CONST_ZERO42, CONST_ZERO44,
128 
    CONST_ZERO8, CONST_ZERO82, CONST_ZERO84,
129 
    CONST_SIGN8, CONST_SIGN82, CONST_SIGN122,
130 
    RDCONST_X, RDCONST_Y,
131 
    // register forward
132 
    REG_FWD_X, REG_FWD_Y,
133 
    // commands for comparator and shifter
134 
    CMPCOM, SFTFUNC,
135 
    // read controls to Z-BUS
136 
    RDSFT_Z,
137 
    // T value for Bcc judgement
138 
    T_BCC,
139 
    // SR control
140 
    T_CMPSET, T_CRYSET, T_TSTSET, T_SFTSET,
141 
    QT_DV1SET, MQT_DV0SET, T_CLR, T_SET, MQ_CLR,
142 
    // Temporary Register
143 
    RDTEMP_X,
144 
    WRTEMP_Z, WRMAAD_TEMP,
145 
    // Hardware Exception Event
146 
    EVENT_REQ, EVENT_ACK, EVENT_INFO,
147 
    // I bit in Status Register
148 
    RST_SR, IBIT, ILEVEL, WR_IBIT,
149 
    // SLEEP
150 
    SLP
151 
    );
152 
 
153 
//-------------------
154 
// Module I/O Signals
155 
//-------------------
156 
    input  CLK;            // clock
157 
    input  RST;            // reset
158 
    input  SLOT;           // pipeline slot
159 
    output IF_ISSUE;       // fetch request
160 
    output IF_JP;          // fetch caused by jump
161 
    input  [15:0] IF_DR;   // fetched instruction
162 
    input  IF_BUS;         // fetch access done to extenal bus
163 
    input  IF_STALL;       // fetch and memory access contention
164 
    output MA_ISSUE;       // memory access request
165 
    output KEEP_CYC;       // request read-modify-write (To be issued on READ-CYC to keep CYC_O on)
166 
    output MA_WR;          // memory access kind : Write(1)/Read(0)
167 
    output [1:0] MA_SZ;    // memory access size : 00 byte, 01 word, 10 long, 11 inhibitted
168 
 
169 
    output MULCOM1;        // Mult M1 Latch Command
170 
    output [7:0] MULCOM2;  // Mult M2 Latch Command
171 
    output WRMACH, WRMACL; // Write MACH/MACL
172 
    input  MAC_BUSY;       // multiplier busy signal (negate at final operation state)
173 
 
174 
    output RDREG_X;        // read REG to X
175 
    output RDREG_Y;        // read REG to Y
176 
    output WRREG_Z;        // write REG from Z
177 
    output WRREG_W;        // write REG from W
178 
 
179 
    output [3:0] REGNUM_X; // specify REG number reading to X
180 
    output [3:0] REGNUM_Y; // specify REG number reading to Y
181 
    output [3:0] REGNUM_Z; // specify REG number writing from Z
182 
    output [3:0] REGNUM_W; // specify REG number writing from W
183 
 
184 
    output [4:0] ALUFUNC;  // ALU function
185 
 
186 
    output WRMAAD_Z;       // write MAAD from Z
187 
    output WRMADW_X;       // write MADW from X
188 
    output WRMADW_Y;       // write MADW from Y
189 
    output RDMADR_W;       // read MADR to W
190 
 
191 
    output [1:0] MACSEL1;  // MAC Selecter 1
192 
    output [1:0] MACSEL2;  // MAC Selecter 2
193 
    output RDMACH_X;       // read MACH to X
194 
    output RDMACL_X;       // read MACL to X
195 
    output RDMACH_Y;       // read MACH to Y
196 
    output RDMACL_Y;       // read MACL to Y
197 
 
198 
    output RDSR_X;         // read SR to X-bus
199 
    output RDSR_Y;         // read SR to Y-bus
200 
    output WRSR_Z;         // write SR from Z-bus
201 
    output WRSR_W;         // write SR from W-bus
202 
 
203 
    output MAC_S_LATCH;    // latch S bit before MAC operation
204 
 
205 
    output RDGBR_X;        // read GBR to X-bus
206 
    output RDGBR_Y;        // read GBR to Y-bus
207 
    output WRGBR_Z;        // write GBR from Z-bus
208 
    output WRGBR_W;        // write GBR from W-bus
209 
 
210 
    output RDVBR_X;        // read VBR to X-bus
211 
    output RDVBR_Y;        // read VBR to Y-bus
212 
    output WRVBR_Z;        // write VBR from Z-bus
213 
    output WRVBR_W;        // write VBR from W-bus
214 
 
215 
    output RDPR_X;         // read PR to X-bus
216 
    output RDPR_Y;         // read PR to Y-bus
217 
    output WRPR_Z;         // write PR from Z-bus
218 
    output WRPR_W;         // write PR from W-bus
219 
    output WRPR_PC;        // write PR from PC
220 
 
221 
    output RDPC_X;         // read PC to X
222 
    output RDPC_Y;         // read PC to Y
223 
    output WRPC_Z;         // write PC from Z
224 
    output INCPC;          // increment PC
225 
    output IFADSEL;        // IF_AD selecter
226 
 
227 
    output [15:0] CONST_IFDR; // Constant Value from Instruction Field
228 
    output CONST_ZERO4;       // Const = unsigned lower 4bit
229 
    output CONST_ZERO42;      // Const = unsigned lower 4bit * 2
230 
    output CONST_ZERO44;      // Const = unsigned lower 4bit * 4
231 
    output CONST_ZERO8;       // Const = unsigned lower 8bit
232 
    output CONST_ZERO82;      // Const = unsigned lower 8bit * 2
233 
    output CONST_ZERO84;      // Const = unsigned lower 8bit * 4
234 
    output CONST_SIGN8;       // Const = signed lower 8bit
235 
    output CONST_SIGN82;      // Const = signed lower 8bit * 2
236 
    output CONST_SIGN122;     // Const = signed lower 12bit * 2
237 
    output RDCONST_X;         // read CONST to X
238 
    output RDCONST_Y;         // read CONST to Y
239 
    output REG_FWD_X;         // forward REG from W to X
240 
    output REG_FWD_Y;         // forward REG from W to Y
241 
 
242 
    output [2:0] CMPCOM;   // define comparator operation (command)
243 
    output [4:0] SFTFUNC;  // Shifter Function
244 
 
245 
    output RDSFT_Z;        // read SFTOUT to Z-BUS
246 
 
247 
    input  T_BCC;          // T value for Bcc judgement
248 
    output T_CMPSET;       // reflect comparator result to T
249 
    output T_CRYSET;       // reflect carry/borrow out to T
250 
    output T_TSTSET;       // reflect tst result to T
251 
    output T_SFTSET;       // reflect shifted output to T
252 
    output QT_DV1SET;      // reflect DIV1 result to Q and T
253 
    output MQT_DV0SET;     // reflect DIV0S result to M, Q and T
254 
    output T_CLR;          // clear T
255 
    output T_SET;          // set T
256 
    output MQ_CLR;         // clear M and Q
257 
 
258 
    output RDTEMP_X;       // read TEMP to X-bus
259 
    output WRTEMP_Z;       // write to TEMP from Z-bus
260 
    output WRMAAD_TEMP;    // output MAAD from TEMP
261 
 
262 
    input  [2:0] EVENT_REQ;   // event request
263 
    output EVENT_ACK;         // event acknowledge
264 
    input  [11:0] EVENT_INFO; // event information (ILEVEL[3:0],VECTOR[7:0])
265 
 
266 
    output RST_SR;         // reset SR
267 
    input  [3:0] IBIT;     // I bit in SR
268 
    output [3:0] ILEVEL;   // IRQ Level
269 
    output WR_IBIT;        // Write ILEVEL to I bit in SR
270 
 
271 
    output SLP;            // Sleep output
272 
 
273 
//-----------------
274 
// Internal Signals
275 
//-----------------
276 
    reg  [15:0] IF_DR_EVT; // IF_DR reflected by Hardware Event
277 
    reg  EVENT_ACK;        // Hardware Event Acknowledge
278 
    reg  EVENT_ACK_0;      // Hardware Event Acknowledge from huge truth table
279 
    reg  [15:0] IR;     // instruction register
280 
                        // It is used by only multicycle instruction.
281 
                        // IF_DR is latched to IR when INSTR_SEQ=0.
282 
                        // This means IR is valid after ID stage (=from EX stage).
283 
    reg  [15:0] INSTR_STATE; // Instruction State (what instruction is on going.)
284 
    reg  [ 3:0] INSTR_SEQ;   // Instruction Sequence
285 
    reg  DISPATCH;      // clear INSTR_SEQ (restart sequence for new instruction)
286 
    reg  REG_CONF;      // register conflict (memory load contention)
287 
    reg  ID_STALL;      // indicate a slot of stalled ID stage
288 
    reg  NEXT_ID_STALL; // indicate next ID should be stalled
289 
    reg  INSTR_SEQ_ZERO;// if (INSTR_SEQ == 4'b0000) INSTR_SEQ_ZERO is 1 else 0
290 
    reg  INSTR_STATE_SEL; // 0:INSTR_STATE=IFDR, 1:INSTRSTATE=IR
291 
    reg  DELAY_JUMP;    // it shows ID stage of delayed jump instruction
292 
    reg  DELAY_SLOT;    // it shows ID stage of delayed slot instruction
293 
 
294 
    reg  RST_SR;        // reset SR
295 
    reg  [3:0] ILEVEL;  // IRQ Level
296 
    reg  ILEVEL_CAP;    // Capture IRQ Level
297 
    reg  WR_IBIT;       // Write ILEVEL to I bit in SR
298 
    reg  MASKINT_NEXT;  // Mask Interrupt at next slot
299 
    reg  MASKINT;       // Mask Interrupt at this slot
300 
 
301 
    reg  SLP;           // Sleep output
302 
 
303 
//---------------------------------
304 
// Multiplier related Stall Control
305 
//---------------------------------
306 
    reg  WB_MAC_BUSY, WB1_MAC_BUSY, WB2_MAC_BUSY, WB3_MAC_BUSY;
307 
    reg  EX_MAC_BUSY, EX1_MAC_BUSY;
308 
    reg  MAC_STALL;       // Shows "should-be-stalled" ID of multiplier related instruction.
309 
    reg  MAC_STALL_SENSE; // ID stage that is stalled by multiplier operation should set this.
310 
    reg  MAC_S_LATCH;     // command to latch S bit before MAC operation
311 
 
312 
    always @(posedge CLK or posedge RST)
313 
    begin
314 
        if (RST)
315 
        begin
316 
            WB1_MAC_BUSY <= 1'b0;
317 
            WB2_MAC_BUSY <= 1'b0;
318 
            WB3_MAC_BUSY <= 1'b0;
319 
            EX1_MAC_BUSY <= 1'b0;
320 
        end
321 
        else if (SLOT)
322 
        begin
323 
            WB1_MAC_BUSY <= WB_MAC_BUSY;
324 
            WB2_MAC_BUSY <= WB1_MAC_BUSY;
325 
            WB3_MAC_BUSY <= WB2_MAC_BUSY;
326 
            EX1_MAC_BUSY <= EX_MAC_BUSY;
327 
        end
328 
    end
329 
 
330 
    always @(MAC_STALL_SENSE or MAC_BUSY
331 
          or WB1_MAC_BUSY or WB2_MAC_BUSY or WB3_MAC_BUSY or EX1_MAC_BUSY)
332 
    begin
333 
        MAC_STALL <= MAC_STALL_SENSE
334 
                   & (WB1_MAC_BUSY | WB2_MAC_BUSY | WB3_MAC_BUSY | EX1_MAC_BUSY | MAC_BUSY);
335 
    end
336 
 
337 
//-----------------------------------
338 
// Control Signal & Pipeline Shifting
339 
//-----------------------------------
340 
// Examples of Naming Convention
341 
//    ID_ddd  : control signal for ID stage (output by Decoder)
342 
//    EX_eee  : control signal for EX stage (output by Decoder)
343 
//    eee     : shifted EX_eee by one slot (control output to datapath)
344 
//    WB_www  : control signal for WB stage (output by Decoder)
345 
//    WB1_www : shifted WB_www by one slot (active at EX stage)
346 
//    WB2_www : shifted WB1_www by one slot (active at MA stage)
347 
//    www     : shifted WB2_www by one slot (control output to datapath)
348 
//
349 
//-----------------------------------
350 
    reg [1:0] WB_MACSEL1, WB1_MACSEL1, WB2_MACSEL1, EX_MACSEL1, MACSEL1;
351 
    reg WB_MULCOM1, WB1_MULCOM1, WB2_MULCOM1, EX_MULCOM1, MULCOM1;
352 
    always @(posedge CLK or posedge RST)
353 
        if (RST)
354 
        begin
355 
            WB1_MULCOM1 <= 1'b0;
356 
            WB2_MULCOM1 <= 1'b0;
357 
            MULCOM1     <= 1'b0;
358 
            WB1_MACSEL1 <= 2'b00;
359 
            WB2_MACSEL1 <= 2'b00;
360 
            MACSEL1     <= 2'b00;
361 
        end
362 
        else if (SLOT)
363 
        begin
364 
            WB1_MULCOM1 <= ((NEXT_ID_STALL)? 1'b0 : WB_MULCOM1);
365 
            WB2_MULCOM1 <= WB1_MULCOM1;
366 
            MULCOM1     <= WB2_MULCOM1 | ((NEXT_ID_STALL)? 1'b0 : EX_MULCOM1);
367 
            WB1_MACSEL1 <= ((NEXT_ID_STALL)? 1'b0 : WB_MACSEL1);
368 
            WB2_MACSEL1 <= WB1_MACSEL1;
369 
            MACSEL1     <= WB2_MACSEL1 | ((NEXT_ID_STALL)? 1'b0 : EX_MACSEL1);
370 
        end
371 
 
372 
    reg [1:0] WB_MACSEL2, WB1_MACSEL2, WB2_MACSEL2, EX_MACSEL2, MACSEL2;
373 
    reg [7:0] WB_MULCOM2, WB1_MULCOM2, WB2_MULCOM2, EX_MULCOM2, MULCOM2;
374 
    always @(posedge CLK or posedge RST)
375 
        if (RST)
376 
        begin
377 
            WB1_MULCOM2 <= 8'h00;
378 
            WB2_MULCOM2 <= 8'h00;
379 
            MULCOM2     <= 8'h00;
380 
            WB1_MACSEL2 <= 2'b00;
381 
            WB2_MACSEL2 <= 2'b00;
382 
            MACSEL2     <= 2'b00;
383 
        end
384 
        else if (SLOT)
385 
        begin
386 
            WB1_MULCOM2 <= ((NEXT_ID_STALL)? 1'b0 : WB_MULCOM2);
387 
            WB2_MULCOM2 <= WB1_MULCOM2;
388 
            MULCOM2     <= WB2_MULCOM2 | ((NEXT_ID_STALL)? 1'b0 : EX_MULCOM2);
389 
            WB1_MACSEL2 <= ((NEXT_ID_STALL)? 1'b0 : WB_MACSEL2);
390 
            WB2_MACSEL2 <= WB1_MACSEL2;
391 
            MACSEL2     <= WB2_MACSEL2 | ((NEXT_ID_STALL)? 1'b0 : EX_MACSEL2);
392 
        end
393 
//-----------------------------------
394 
    reg EX_RDMACH_X, RDMACH_X;
395 
    reg EX_RDMACL_X, RDMACL_X;
396 
    reg EX_RDMACH_Y, RDMACH_Y;
397 
    reg EX_RDMACL_Y, RDMACL_Y;
398 
    always @(posedge CLK or posedge RST)
399 
        if (RST)
400 
        begin
401 
             RDMACH_X <= 1'b0;
402 
             RDMACL_X <= 1'b0;
403 
             RDMACH_Y <= 1'b0;
404 
             RDMACL_Y <= 1'b0;
405 
        end
406 
        else if (SLOT)
407 
        begin
408 
             RDMACH_X <= EX_RDMACH_X;
409 
             RDMACL_X <= EX_RDMACL_X;
410 
             RDMACH_Y <= EX_RDMACH_Y;
411 
             RDMACL_Y <= EX_RDMACL_Y;
412 
        end
413 
 
414 
    reg WB_WRMACH, EX_WRMACH, WRMACH, WB1_WRMACH, WB2_WRMACH;
415 
    always @(posedge CLK or posedge RST)
416 
        if (RST)
417 
        begin
418 
            WB1_WRMACH <= 1'b0;
419 
            WB2_WRMACH <= 1'b0;
420 
            WRMACH     <= 1'b0;
421 
        end
422 
        else if (SLOT)
423 
        begin
424 
            WB1_WRMACH <= ((NEXT_ID_STALL)? 1'b0 : WB_WRMACH);
425 
            WB2_WRMACH <= WB1_WRMACH;
426 
            WRMACH     <= WB2_WRMACH | ((NEXT_ID_STALL)? 1'b0 : EX_WRMACH);
427 
        end
428 
 
429 
    reg WB_WRMACL, EX_WRMACL, WRMACL, WB1_WRMACL, WB2_WRMACL;
430 
    always @(posedge CLK or posedge RST)
431 
        if (RST)
432 
        begin
433 
            WB1_WRMACL <= 1'b0;
434 
            WB2_WRMACL <= 1'b0;
435 
            WRMACL     <= 1'b0;
436 
        end
437 
        else if (SLOT)
438 
        begin
439 
            WB1_WRMACL <= ((NEXT_ID_STALL)? 1'b0 : WB_WRMACL);
440 
            WB2_WRMACL <= WB1_WRMACL;
441 
            WRMACL     <= WB2_WRMACL | ((NEXT_ID_STALL)? 1'b0 : EX_WRMACL);
442 
        end
443 
//-----------------------------------
444 
    reg EX_RDREG_X, RDREG_X;
445 
    reg EX_RDREG_Y, RDREG_Y;
446 
    reg [3:0] EX_REGNUM_X, REGNUM_X;
447 
    reg [3:0] EX_REGNUM_Y, REGNUM_Y;
448 
    always @(posedge CLK or posedge RST)
449 
        if (RST)
450 
        begin
451 
            RDREG_X <= 1'b0;
452 
            RDREG_Y <= 1'b0;
453 
        end
454 
        else if (SLOT)
455 
        begin
456 
            RDREG_X  <= EX_RDREG_X;
457 
            RDREG_Y  <= EX_RDREG_Y;
458 
            REGNUM_X <= EX_REGNUM_X;
459 
            REGNUM_Y <= EX_REGNUM_Y;
460 
        end
461 
 
462 
    reg EX_WRREG_Z, WRREG_Z;
463 
    reg [3:0] EX_REGNUM_Z, REGNUM_Z;
464 
    always @(posedge CLK or posedge RST)
465 
        if (RST)
466 
        begin
467 
            WRREG_Z  <= 1'b0;
468 
        end
469 
        else if (SLOT)
470 
        begin
471 
            WRREG_Z  <= ((NEXT_ID_STALL)? 1'b0 : EX_WRREG_Z);
472 
            REGNUM_Z <= EX_REGNUM_Z;
473 
        end
474 
 
475 
    reg WB_WRREG_W, WRREG_W, WB1_WRREG_W, WB2_WRREG_W;
476 
    reg [3:0] WB_REGNUM_W, REGNUM_W, WB1_REGNUM_W, WB2_REGNUM_W;
477 
    always @(posedge CLK or posedge RST)
478 
        if (RST)
479 
        begin
480 
            WB1_WRREG_W  <= 1'b0;
481 
            WB2_WRREG_W  <= 1'b0;
482 
            WRREG_W      <= 1'b0;
483 
        end
484 
        else if (SLOT) begin
485 
            WB1_WRREG_W  <= ((NEXT_ID_STALL)? 1'b0 : WB_WRREG_W);
486 
            WB2_WRREG_W  <= WB1_WRREG_W;
487 
            WRREG_W      <= WB2_WRREG_W;
488 
            WB1_REGNUM_W <= WB_REGNUM_W;
489 
            WB2_REGNUM_W <= WB1_REGNUM_W;
490 
            REGNUM_W     <= WB2_REGNUM_W;
491 
        end
492 
//-----------------------------------
493 
    reg [4:0] EX_ALUFUNC, ALUFUNC;
494 
    always @(posedge CLK or posedge RST)
495 
        if (RST)
496 
            ALUFUNC <= `ALU_NOP;
497 
        else if (SLOT) begin
498 
            ALUFUNC <= EX_ALUFUNC;
499 
        end
500 
//-----------------------------------
501 
    reg EX_WRMAAD_Z, WRMAAD_Z;
502 
    reg EX_WRMADW_X, WRMADW_X;
503 
    reg EX_WRMADW_Y, WRMADW_Y;
504 
    always @(posedge CLK or posedge RST)
505 
        if (RST)
506 
        begin
507 
            WRMAAD_Z <= 1'b0;
508 
            WRMADW_X <= 1'b0;
509 
            WRMADW_Y <= 1'b0;
510 
        end
511 
        else if (SLOT)
512 
        begin
513 
            WRMAAD_Z <= ((NEXT_ID_STALL)? 1'b0 : EX_WRMAAD_Z);
514 
            WRMADW_X <= ((NEXT_ID_STALL)? 1'b0 : EX_WRMADW_X);
515 
            WRMADW_Y <= ((NEXT_ID_STALL)? 1'b0 : EX_WRMADW_Y);
516 
        end
517 
 
518 
    reg WB_RDMADR_W, RDMADR_W, WB1_RDMADR_W, WB2_RDMADR_W;
519 
    always @(posedge CLK or posedge RST)
520 
        if (RST)
521 
        begin
522 
            WB1_RDMADR_W <= 1'b0;
523 
            WB2_RDMADR_W <= 1'b0;
524 
            RDMADR_W     <= 1'b0;
525 
        end
526 
        else if (SLOT)
527 
        begin
528 
            WB1_RDMADR_W <= WB_RDMADR_W;
529 
            WB2_RDMADR_W <= WB1_RDMADR_W;
530 
            RDMADR_W     <= WB2_RDMADR_W;
531 
        end
532 
//-----------------------------------
533 
    reg EX_RDPC_X, RDPC_X;
534 
    reg EX_RDPC_Y, RDPC_Y;
535 
    reg EX_WRPC_Z, WRPC_Z;
536 
    reg ID_INCPC, INCPC;
537 
    always @(posedge CLK or posedge RST)
538 
        if (RST)
539 
        begin
540 
            RDPC_X <= 1'b0;
541 
            RDPC_Y <= 1'b0;
542 
            WRPC_Z <= 1'b0;
543 
        end
544 
        else if (SLOT)
545 
        begin
546 
            RDPC_X <= EX_RDPC_X;
547 
            RDPC_Y <= EX_RDPC_Y;
548 
            WRPC_Z <= ((NEXT_ID_STALL)? 1'b0 : EX_WRPC_Z);
549 
        end
550 
 
551 
    always @(ID_INCPC or NEXT_ID_STALL)
552 
    begin
553 
        INCPC <= ((NEXT_ID_STALL)? 1'b0 : ID_INCPC);
554 
    end
555 
 
556 
    reg EX_IFADSEL, ID_IFADSEL, IFADSEL, EX1_IFADSEL;
557 
    always @(posedge CLK or posedge RST)
558 
        if (RST)
559 
            EX1_IFADSEL <= 1'b0;
560 
        else if (SLOT) begin
561 
            EX1_IFADSEL <= EX_IFADSEL;
562 
        end
563 
 
564 
    always @(EX1_IFADSEL or ID_IFADSEL)
565 
        IFADSEL <= EX1_IFADSEL | ID_IFADSEL;
566 
 
567 
    reg  EX_IF_ISSUE, ID_IF_ISSUE, IF_ISSUE, EX1_IF_ISSUE;  // fetch request
568 
    reg  EX_IF_JP, ID_IF_JP, IF_JP, EX1_IF_JP;              // fetch caused by jump
569 
    always @(posedge CLK or posedge RST)
570 
        if (RST)
571 
        begin
572 
            EX1_IF_ISSUE <= 1'b0;
573 
            EX1_IF_JP    <= 1'b0;
574 
        end
575 
        else if (SLOT) begin
576 
            EX1_IF_ISSUE <= ((NEXT_ID_STALL)? 1'b0 : EX_IF_ISSUE);
577 
            EX1_IF_JP    <= ((NEXT_ID_STALL)? 1'b0 : EX_IF_JP);
578 
        end
579 
 
580 
    // [CAUTION]
581 
    // IF_ISSUE and IF_JP should be masked by REG_CONF.
582 
    // If they are masked by NEXT_ID_STALL which is made from IF_STALL,
583 
    // a oscillation loop from DECODE--(issue command)-->MEM--(IF_STALL)-->DECODE appears.
584 
    // The IF issue operation is stalled only by register conflict stall, so
585 
    // this function is correct.
586 
    // And also, IF_ISSUE should be masked by MAC_STALL, because, if the ID stage of instruction
587 
    // stalled by MAC_STALL issues IF at every stalled cycle, the fetched instruction
588 
    // may be diappeared.
589 
    always @(EX1_IF_ISSUE or ID_IF_ISSUE or EX1_IF_JP or ID_IF_JP or REG_CONF or MAC_STALL)
590 
    begin
591 
        IF_ISSUE <= EX1_IF_ISSUE | (ID_IF_ISSUE & ~REG_CONF & ~MAC_STALL);
592 
        IF_JP <= EX1_IF_JP | (ID_IF_JP & ~REG_CONF);
593 
    end
594 
//-----------------------------------
595 
    reg  EX_MA_ISSUE, MA_ISSUE;   // memory access request
596 
    reg  EX_KEEP_CYC, KEEP_CYC;   // request read-modify-write (To be issued on READ-CYC to keep CYC_O on)
597 
    reg  EX_MA_WR, MA_WR;         // memory access kind : Write(1)/Read(0)
598 
    reg  [1:0] EX_MA_SZ, MA_SZ;   // memory access size : 00 byte, 01 word, 10 long, 11 inhibitted
599 
    always @(posedge CLK or posedge RST)
600 
        if (RST)
601 
        begin
602 
            MA_ISSUE <= 1'b0;
603 
            KEEP_CYC <= 1'b0;
604 
            MA_WR    <= 1'b0;
605 
            MA_SZ    <= 2'b00;
606 
        end
607 
        else if (SLOT)
608 
        begin
609 
            MA_ISSUE <= ((NEXT_ID_STALL)? 1'b0 : EX_MA_ISSUE);
610 
            KEEP_CYC <= EX_KEEP_CYC;
611 
            MA_WR <= EX_MA_WR;
612 
            MA_SZ <= EX_MA_SZ;
613 
        end
614 
//-----------------------------------
615 
    reg EX_CONST_ZERO4,  CONST_ZERO4;
616 
    reg EX_CONST_ZERO42, CONST_ZERO42;
617 
    reg EX_CONST_ZERO44, CONST_ZERO44;
618 
    reg EX_CONST_ZERO8,  CONST_ZERO8;
619 
    reg EX_CONST_ZERO82, CONST_ZERO82;
620 
    reg EX_CONST_ZERO84, CONST_ZERO84;
621 
    reg EX_CONST_SIGN8,  CONST_SIGN8;
622 
    reg EX_CONST_SIGN82, CONST_SIGN82;
623 
    reg EX_CONST_SIGN122,CONST_SIGN122;
624 
    reg EX_RDCONST_X, RDCONST_X;
625 
    reg EX_RDCONST_Y, RDCONST_Y;
626 
    always @(posedge CLK or posedge RST)
627 
        if (RST)
628 
        begin
629 
            CONST_ZERO4  <= 1'b0;
630 
            CONST_ZERO42 <= 1'b0;
631 
            CONST_ZERO44 <= 1'b0;
632 
            CONST_ZERO8  <= 1'b0;
633 
            CONST_ZERO82 <= 1'b0;
634 
            CONST_ZERO84 <= 1'b0;
635 
            CONST_SIGN8  <= 1'b0;
636 
            CONST_SIGN82 <= 1'b0;
637 
            CONST_SIGN122<= 1'b0;
638 
            RDCONST_X    <= 1'b0;
639 
            RDCONST_Y    <= 1'b0;
640 
        end
641 
        else if (SLOT)
642 
        begin
643 
            CONST_ZERO4  <= EX_CONST_ZERO4;
644 
            CONST_ZERO44 <= EX_CONST_ZERO44;
645 
            CONST_ZERO42 <= EX_CONST_ZERO42;
646 
            CONST_ZERO8  <= EX_CONST_ZERO8;
647 
            CONST_ZERO82 <= EX_CONST_ZERO82;
648 
            CONST_ZERO84 <= EX_CONST_ZERO84;
649 
            CONST_SIGN8  <= EX_CONST_SIGN8;
650 
            CONST_SIGN82 <= EX_CONST_SIGN82;
651 
            CONST_SIGN122<= EX_CONST_SIGN122;
652 
            RDCONST_X    <= EX_RDCONST_X;
653 
            RDCONST_Y    <= EX_RDCONST_Y;
654 
        end
655 
 
656 
    reg [15:0] CONST_IFDR;
657 
    //always @(posedge CLK)
658 
    //    if (SLOT & INSTR_SEQ_ZERO & ~NEXT_ID_STALL)
659 
    //        CONST_IFDR <= IF_DR[15:0];
660 
    //    else if (SLOT & ~INSTR_SEQ_ZERO & ~NEXT_ID_STALL)
661 
    //        CONST_IFDR <= IR[15:0];
662 
    always @(posedge CLK)
663 
        if (SLOT)
664 
            CONST_IFDR <= INSTR_STATE;
665 
//-----------------------------------
666 
    reg EX_RDSR_X, RDSR_X;
667 
    reg EX_RDSR_Y, RDSR_Y;
668 
    reg EX_WRSR_Z, WRSR_Z;
669 
    reg WB_WRSR_W, WRSR_W, WB1_WRSR_W, WB2_WRSR_W;
670 
    always @(posedge CLK or posedge RST)
671 
        if (RST)
672 
        begin
673 
            RDSR_X     <= 1'b0;
674 
            RDSR_Y     <= 1'b0;
675 
            WRSR_Z     <= 1'b0;
676 
            WB1_WRSR_W <= 1'b0;
677 
            WB2_WRSR_W <= 1'b0;
678 
            WRSR_W     <= 1'b0;
679 
        end
680 
        else if (SLOT)
681 
        begin
682 
            RDSR_X     <= EX_RDSR_X;
683 
            RDSR_Y     <= EX_RDSR_Y;
684 
            WRSR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRSR_Z);
685 
            WB1_WRSR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRSR_W);
686 
            WB2_WRSR_W <= WB1_WRSR_W;
687 
            WRSR_W     <= WB2_WRSR_W;
688 
        end
689 
//-----------------------------------
690 
    reg EX_RDGBR_X, RDGBR_X;
691 
    reg EX_RDGBR_Y, RDGBR_Y;
692 
    reg EX_WRGBR_Z, WRGBR_Z;
693 
    reg WB_WRGBR_W, WRGBR_W, WB1_WRGBR_W, WB2_WRGBR_W;
694 
    always @(posedge CLK or posedge RST)
695 
        if (RST)
696 
        begin
697 
            RDGBR_X     <= 1'b0;
698 
            RDGBR_Y     <= 1'b0;
699 
            WRGBR_Z     <= 1'b0;
700 
            WB1_WRGBR_W <= 1'b0;
701 
            WB2_WRGBR_W <= 1'b0;
702 
            WRGBR_W     <= 1'b0;
703 
        end
704 
        else if (SLOT)
705 
        begin
706 
            RDGBR_X     <= EX_RDGBR_X;
707 
            RDGBR_Y     <= EX_RDGBR_Y;
708 
            WRGBR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRGBR_Z);
709 
            WB1_WRGBR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRGBR_W);
710 
            WB2_WRGBR_W <= WB1_WRGBR_W;
711 
            WRGBR_W     <= WB2_WRGBR_W;
712 
        end
713 
//-----------------------------------
714 
    reg EX_RDVBR_X, RDVBR_X;
715 
    reg EX_RDVBR_Y, RDVBR_Y;
716 
    reg EX_WRVBR_Z, WRVBR_Z;
717 
    reg WB_WRVBR_W, WRVBR_W, WB1_WRVBR_W, WB2_WRVBR_W;
718 
    always @(posedge CLK or posedge RST)
719 
        if (RST)
720 
        begin
721 
            RDVBR_X     <= 1'b0;
722 
            RDVBR_Y     <= 1'b0;
723 
            WRVBR_Z     <= 1'b0;
724 
            WB1_WRVBR_W <= 1'b0;
725 
            WB2_WRVBR_W <= 1'b0;
726 
            WRVBR_W     <= 1'b0;
727 
        end
728 
        else if (SLOT)
729 
        begin
730 
            RDVBR_X     <= EX_RDVBR_X;
731 
            RDVBR_Y     <= EX_RDVBR_Y;
732 
            WRVBR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRVBR_Z);
733 
            WB1_WRVBR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRVBR_W);
734 
            WB2_WRVBR_W <= WB1_WRVBR_W;
735 
            WRVBR_W     <= WB2_WRVBR_W;
736 
        end
737 
//-----------------------------------
738 
    reg EX_RDPR_X, RDPR_X;
739 
    reg EX_RDPR_Y, RDPR_Y;
740 
    reg EX_WRPR_Z, WRPR_Z;
741 
    reg WB_WRPR_W, WRPR_W, WB1_WRPR_W, WB2_WRPR_W;
742 
    reg EX_WRPR_PC,WRPR_PC;
743 
    always @(posedge CLK or posedge RST)
744 
        if (RST)
745 
        begin
746 
            RDPR_X     <= 1'b0;
747 
            RDPR_Y     <= 1'b0;
748 
            WRPR_Z     <= 1'b0;
749 
            WB1_WRPR_W <= 1'b0;
750 
            WB2_WRPR_W <= 1'b0;
751 
            WRPR_W     <= 1'b0;
752 
            WRPR_PC    <= 1'b0;
753 
        end
754 
        else if (SLOT)
755 
        begin
756 
            RDPR_X     <= EX_RDPR_X;
757 
            RDPR_Y     <= EX_RDPR_Y;
758 
            WRPR_Z     <= ((NEXT_ID_STALL)? 1'b0 : EX_WRPR_Z);
759 
            WB1_WRPR_W <= ((NEXT_ID_STALL)? 1'b0 : WB_WRPR_W);
760 
            WB2_WRPR_W <= WB1_WRPR_W;
761 
            WRPR_W     <= WB2_WRPR_W;
762 
            WRPR_PC    <= ((NEXT_ID_STALL)? 1'b0 : EX_WRPR_PC);
763 
        end
764 
//-----------------------------------
765 
    reg [2:0] EX_CMPCOM, CMPCOM;
766 
    reg [4:0] EX_SFTFUNC, SFTFUNC;
767 
    reg EX_RDSFT_Z, RDSFT_Z;
768 
    reg EX_T_CMPSET, T_CMPSET;
769 
    reg EX_T_CRYSET, T_CRYSET;
770 
    reg EX_T_TSTSET, T_TSTSET;
771 
    reg EX_T_SFTSET, T_SFTSET;
772 
    reg EX_QT_DV1SET, QT_DV1SET;
773 
    reg EX_MQT_DV0SET, MQT_DV0SET;
774 
    reg EX_T_CLR, T_CLR;
775 
    reg EX_T_SET, T_SET;
776 
    reg EX_MQ_CLR, MQ_CLR;
777 
 
778 
    always @(posedge CLK or posedge RST)
779 
        if (RST)
780 
        begin
781 
            RDSFT_Z    <= 1'b0;
782 
            T_CMPSET   <= 1'b0;
783 
            T_CRYSET   <= 1'b0;
784 
            T_TSTSET   <= 1'b0;
785 
            T_SFTSET   <= 1'b0;
786 
            QT_DV1SET  <= 1'b0;
787 
            MQT_DV0SET <= 1'b0;
788 
            T_CLR      <= 1'b0;
789 
            T_SET      <= 1'b0;
790 
            MQ_CLR     <= 1'b0;
791 
        end
792 
        else if (SLOT)
793 
        begin
794 
            CMPCOM     <= ((NEXT_ID_STALL)? 3'b000 : EX_CMPCOM);
795 
            SFTFUNC    <= ((NEXT_ID_STALL)? 3'b000 : EX_SFTFUNC);
796 
            RDSFT_Z    <= ((NEXT_ID_STALL)? 1'b0: EX_RDSFT_Z);
797 
            T_CMPSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_CMPSET);
798 
            T_CRYSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_CRYSET);
799 
            T_TSTSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_TSTSET);
800 
            T_SFTSET   <= ((NEXT_ID_STALL)? 1'b0: EX_T_SFTSET);
801 
            QT_DV1SET  <= ((NEXT_ID_STALL)? 1'b0: EX_QT_DV1SET);
802 
            MQT_DV0SET <= ((NEXT_ID_STALL)? 1'b0: EX_MQT_DV0SET);
803 
            T_CLR      <= ((NEXT_ID_STALL)? 1'b0: EX_T_CLR);
804 
            T_SET      <= ((NEXT_ID_STALL)? 1'b0: EX_T_SET);
805 
            MQ_CLR     <= ((NEXT_ID_STALL)? 1'b0: EX_MQ_CLR);
806 
        end
807 
//-----------------------------------
808 
    reg EX_RDTEMP_X,    RDTEMP_X;
809 
    reg EX_WRTEMP_Z,    WRTEMP_Z;
810 
    reg EX_WRMAAD_TEMP, WRMAAD_TEMP;
811 
    reg EX_FWD_W2X,     FWD_W2X;     // force forward from W-bus to X-bus
812 
    always @(posedge CLK or posedge RST)
813 
        if (RST)
814 
        begin
815 
            RDTEMP_X    <= 1'b0;
816 
            WRTEMP_Z    <= 1'b0;
817 
            WRMAAD_TEMP <= 1'b0;
818 
            FWD_W2X     <= 1'b0;
819 
        end
820 
        else if (SLOT)
821 
        begin
822 
            RDTEMP_X    <= ((NEXT_ID_STALL)? 1'b0: EX_RDTEMP_X);
823 
            WRTEMP_Z    <= ((NEXT_ID_STALL)? 1'b0: EX_WRTEMP_Z);
824 
            WRMAAD_TEMP <= ((NEXT_ID_STALL)? 1'b0: EX_WRMAAD_TEMP);
825 
            FWD_W2X     <= ((NEXT_ID_STALL)? 1'b0: EX_FWD_W2X);
826 
        end
827 
 
828 
//-------------------
829 
// Main State Machine
830 
//-------------------
831 
    // ----------------------Input State------------------ : ---Output--  ---@Next Slot---
832 
    // SLOT  NEXT_ID_STALL  ID_STALL  DISPATCH  INSTR_SEQ  : INSTR_STATE  INSTR_SEQ  IR
833 
    // --------------------------------------------------- : -----------------------------
834 
    // 0     *              *         *         *          : IR           Keep       Keep
835 
    // --------------------------------------------------- : -----------------------------
836 
    // 1     0              0         0         >=0001     : IR           +1         Keep
837 
    // 1     0              0         0         ==0000     : IF_DR        +1         IF_DR
838 
    // 1     0              0         1         >=0001     : IR           Clear0     Keep
839 
    // 1     0              0         1         ==0000     : IF_DR        Clear0     IF_DR
840 
    // 1     0              1         0         >=0001     : IR           +1         Keep
841 
    // 1     0              1         0         ==0000     : IR           +1         Keep
842 
    // 1     0              1         1         >=0001     : IR           Clear0     Keep
843 
    // 1     0              1         1         ==0000     : IR           Clear0     Keep
844 
    // --------------------------------------------------- : -----------------------------
845 
    // 1     1              0         0         >=0001     : IR           Keep       Keep
846 
    // 1     1              0         0         ==0000     : IF_DR        Keep       IF_DR
847 
    // 1     1              0         1         >=0001     : IR           Keep       Keep
848 
    // 1     1              0         1         ==0000     : IF_DR        Keep       IF_DR
849 
    // 1     1              1         0         >=0001     : IR           Keep       Keep
850 
    // 1     1              1         0         ==0000     : IR           Keep       Keep
851 
    // 1     1              1         1         >=0001     : IR           Keep       Keep
852 
    // 1     1              1         1         ==0000     : IR           Keep       Keep
853 
    //
854 
 
855 
    //-----------------------
856 
    // Detect Exception Event
857 
    //-----------------------
858 
    always @(IF_DR or EVENT_REQ or EVENT_INFO or MASKINT or IBIT or DELAY_SLOT)
859 
    begin
860 
        //--------Hardware Event--------
861 
        if (~DELAY_SLOT & (
862 
               (~MASKINT & (EVENT_REQ == `NMI))
863 
             | (~MASKINT & (EVENT_REQ == `IRQ) & (IBIT < EVENT_INFO[11:8]))
864 
             | (EVENT_REQ == `CPUERR)
865 
             | (EVENT_REQ == `DMAERR)
866 
             | (EVENT_REQ == `MRES)
867 
           ))
868 
            begin
869 
                IF_DR_EVT <= {5'b11110, EVENT_REQ, EVENT_INFO[7:0]};
870 
            end
871 
        //--------General & Slot Illegal Instruction--------
872 
        else if (DELAY_SLOT)
873 
            casex (IF_DR)
874 
                16'b0000????00?00011 : IF_DR_EVT <= `SLOT_ILGL; // BSRF,BRAF
875 
                16'b0000000000101011 : IF_DR_EVT <= `SLOT_ILGL; // RTE
876 
                16'b0100????00?01011 : IF_DR_EVT <= `SLOT_ILGL; // JSR, JMP
877 
                16'b10001??1???????? : IF_DR_EVT <= `SLOT_ILGL; // Bcc, Bcc/S
878 
                16'b101????????????? : IF_DR_EVT <= `SLOT_ILGL; // RRA, BSR
879 
                16'b11000011???????? : IF_DR_EVT <= `SLOT_ILGL; // TRAPA
880 
                16'b11111111???????? : IF_DR_EVT <= `SLOT_ILGL; // General Illegal
881 
                default              : IF_DR_EVT <= IF_DR;
882 
            endcase
883 
        else if (IF_DR[15:8] == 8'hFF)
884 
                IF_DR_EVT <= `GNRL_ILGL; // General Illegal Instruction
885 
        else
886 
                IF_DR_EVT <= IF_DR;
887 
    end
888 
    //----------------------
889 
    always @(posedge CLK)
890 
    begin
891 
        if (SLOT & ILEVEL_CAP) ILEVEL <= EVENT_INFO[11:8];
892 
    end
893 
    //----------------------
894 
    always @(posedge CLK or posedge RST)
895 
    begin
896 
        if (RST)
897 
            MASKINT <= 1'b0;
898 
        else if (SLOT)
899 
            MASKINT <= MASKINT_NEXT;
900 
    end
901 
    //----------------------
902 
    always @(posedge CLK or posedge RST)
903 
    begin
904 
        if (RST)
905 
            DELAY_SLOT <= 1'b0;
906 
        else if (SLOT)
907 
            DELAY_SLOT <= (NEXT_ID_STALL)? DELAY_SLOT : DELAY_JUMP;
908 
    end
909 
    //----------------------
910 
    always@ (EVENT_ACK_0 or SLOT) EVENT_ACK <= SLOT & EVENT_ACK_0;
911 
 
912 
    //---------------------
913 
    // instruction register
914 
    //---------------------
915 
    always @(posedge CLK or posedge RST)
916 
    begin
917 
        if (RST)
918 
            IR <= `POWERON_RESET;
919 
        //else if ((SLOT & ~DISPATCH & INSTR_SEQ_ZERO) | (~SLOT & ~DISPATCH))
920 
        else if (SLOT & ~ID_STALL & INSTR_SEQ_ZERO)
921 
        begin
922 
            IR <= IF_DR_EVT;
923 
        end
924 
    end
925 
 
926 
    //------------------
927 
    // instruction state
928 
    //------------------
929 
    always @(ID_STALL or INSTR_SEQ_ZERO)
930 
    begin
931 
        case ({ID_STALL, INSTR_SEQ_ZERO})
932 
            2'b00 : INSTR_STATE_SEL <= 1'b1;
933 
            2'b01 : INSTR_STATE_SEL <= 1'b0;
934 
            2'b10 : INSTR_STATE_SEL <= 1'b1;
935 
            3'b11 : INSTR_STATE_SEL <= 1'b1;
936 
            default : INSTR_STATE_SEL <= 1'bx;
937 
        endcase
938 
    end
939 
 
940 
    always @(INSTR_STATE_SEL or IR or IF_DR_EVT)
941 
    begin
942 
        if (INSTR_STATE_SEL)
943 
            INSTR_STATE <= IR;
944 
        else
945 
            INSTR_STATE <= IF_DR_EVT;
946 
    end
947 
 
948 
    //--------------
949 
    // Next ID STALL
950 
    //--------------
951 
    always @(REG_CONF or IF_STALL or MAC_STALL)
952 
    begin
953 
        if (REG_CONF | IF_STALL | MAC_STALL)
954 
            NEXT_ID_STALL <= 1'b1;
955 
        else
956 
            NEXT_ID_STALL <= 1'b0;
957 
    end
958 
 
959 
    //---------
960 
    // ID STALL
961 
    //---------
962 
    always @(posedge CLK or posedge RST)
963 
    begin
964 
        if (RST)
965 
            ID_STALL <= 1'b0;
966 
        else if (SLOT)
967 
            ID_STALL <= NEXT_ID_STALL;
968 
    end
969 
 
970 
    //---------------------
971 
    // instruction sequence
972 
    //---------------------
973 
    always @(posedge CLK or posedge RST) begin
974 
        if (RST)
975 
            INSTR_SEQ <= 4'b0001;
976 
        else if (SLOT & ~NEXT_ID_STALL & DISPATCH)
977 
            INSTR_SEQ <= 4'b0000;
978 
        else if (SLOT & ~NEXT_ID_STALL & ~DISPATCH)
979 
            INSTR_SEQ <= INSTR_SEQ + 1;
980 
    end
981 
 
982 
    always @(INSTR_SEQ)
983 
    begin
984 
        if (INSTR_SEQ == 4'b0000)
985 
            INSTR_SEQ_ZERO <= 1'b1;
986 
        else
987 
            INSTR_SEQ_ZERO <= 1'b0;
988 
    end
989 
 
990 
    //------------------------
991 
    // check register conflict
992 
    //------------------------
993 
    // following conditions mean register conflict
994 
    // (1) EX_RDREG_X and WB1_WRREG_W and (EX_REGNUM_X == WB1_REGNUM_W)
995 
    // (2) EX_RDREG_Y and WB1_WRREG_W and (EX_REGNUM_Y == WB1_REGNUM_W)
996 
    // (3) EX_WRREG_Z and WB1_WRREG_W and (EX_REGNUM_Z == WB1_REGNUM_W)
997 
    // (4) EX_RDPR_X and WB1_WRPR_W
998 
    // (5) EX_RDPR_Y and WB1_WRPR_W
999 
    // (6) EX_WRPR_Z and WB1_WRPR_W
1000 
    // (7) (EX_ALUFUNC == `ALU_ADDR0) and WB1_WRREG_W and (WB1_REGNUM_W == 4'h0)
1001 
 
1002 
 
1003 
    always @(EX_RDREG_X  or EX_RDREG_Y or EX_WRREG_Z
1004 11 thorn_aitc 
          or EX_REGNUM_X or EX_REGNUM_Y or EX_REGNUM_Z  // Thorn Aitch 2003/12/10
1005 2 thorn_aitc 
          or WB1_WRREG_W or WB1_REGNUM_W
1006 
          or EX_RDPR_X   or EX_RDPR_Y  or EX_WRPR_Z
1007 
          or WB1_WRPR_W
1008 
       // or EX_RDMACH_X or EX_RDMACH_Y or WB1_WRMACH
1009 
       // or EX_RDMACL_X or EX_RDMACL_Y or WB1_WRMACL
1010 
          or EX_ALUFUNC)
1011 
    //always @(posedge CLK)
1012 
    begin
1013 
        if ((EX_RDREG_X & WB1_WRREG_W & (EX_REGNUM_X == WB1_REGNUM_W))
1014 
          | (EX_RDREG_Y & WB1_WRREG_W & (EX_REGNUM_Y == WB1_REGNUM_W))
1015 
          | (EX_WRREG_Z & WB1_WRREG_W & (EX_REGNUM_Z == WB1_REGNUM_W))
1016 
          | (EX_RDPR_X & WB1_WRPR_W)
1017 
          | (EX_RDPR_Y & WB1_WRPR_W)
1018 
          | (EX_WRPR_Z & WB1_WRPR_W)
1019 
       // | (EX_RDMACH_X & WB1_WRMACH)
1020 
       // | (EX_RDMACH_Y & WB1_WRMACH)
1021 
       // | (EX_RDMACL_X & WB1_WRMACL)
1022 
       // | (EX_RDMACL_Y & WB1_WRMACL)
1023 
          | ((EX_ALUFUNC == `ALU_ADDR0) & WB1_WRREG_W & (WB1_REGNUM_W == 4'h0))
1024 
           )
1025 
            REG_CONF <= 1;
1026 
        else
1027 
            REG_CONF <= 0;
1028 
    end
1029 
 
1030 
    //---------------------------
1031 
    // check forwarding condition
1032 
    //---------------------------
1033 
    // following conditions mean register forwarding from W-bus to X/Y-bus
1034 
    // (1) RDREG_X and WRREG_W and (REGNUM_X == REGNUM_W) : W-bus to X-bus
1035 
    // (2) RDREG_Y and WRREG_W and (REGNUM_Y == REGNUM_W) : W-bus to Y-bus
1036 
    // (3) RDPR_X and WRPR_W : W-bus to X-bus
1037 
    // (4) RDPR_Y and WRPR_W : W-bus to Y-bus
1038 
    // (5) RDMACH_X and WRMACH : W-bus to X-bus
1039 
    // (6) RDMACH_Y and WRMACH : W-bus to Y-bus
1040 
    // (7) RDMACL_X and WRMACL : W-bus to X-bus
1041 
    // (8) RDMACL_Y and WRMACL : W-bus to Y-bus
1042 
 
1043 
    reg  REG_FWD_X;     // register forward from W-bus to X-bus
1044 
    reg  REG_FWD_Y;     // register forward from W-bus to Y-bus
1045 
 
1046 
    always @(RDREG_X  or RDREG_Y
1047 
          or REGNUM_X or REGNUM_Y
1048 
          or WRREG_W or REGNUM_W
1049 
          or RDPR_X or RDPR_Y or WRPR_W
1050 
       // or RDMACH_X or RDMACH_Y or WRMACH
1051 
       // or RDMACL_X or RDMACL_Y or WRMACL
1052 
          or FWD_W2X)
1053 
    begin
1054 
        if ((FWD_W2X)
1055 
          | (RDREG_X & WRREG_W & (REGNUM_X == REGNUM_W))
1056 
          | (RDPR_X & WRPR_W))
1057 
       // | (RDMACH_X & WRMACH)
1058 
       // | (RDMACL_X & WRMACL)
1059 
            REG_FWD_X <= 1'b1;
1060 
        else
1061 
            REG_FWD_X <= 1'b0;
1062 
 
1063 
        if ((RDREG_Y & WRREG_W & (REGNUM_Y == REGNUM_W))
1064 
          | (RDPR_Y & WRPR_W))
1065 
       // | (RDMACH_Y & WRMACH)
1066 
       // | (RDMACL_Y & WRMACL)
1067 
            REG_FWD_Y <= 1'b1;
1068 
        else
1069 
            REG_FWD_Y <= 1'b0;
1070 
    end
1071 
 
1072 
//------------------------------------
1073 
// Output Signals : A huge truth table
1074 
//------------------------------------
1075 
    always @(INSTR_STATE or INSTR_SEQ or T_BCC or NEXT_ID_STALL)
1076 
    begin
1077 
        // ---- CAUTION ----------------------------------------------------------------
1078 
        // To simplify the RTL description rule,
1079 
        // only non-blocking substitution (<=) is recommended for this project.
1080 
        // But in this "always @" statement,
1081 
        // I use blocking substitution (=) to reduce typing errors.
1082 
        // You should take care when you modify or reuse this statement.
1083 
        //
1084 
        // Moreover, in this scope area, I use casex to specify "don't care input ?".
1085 
            // But the use of casex is permitted only for this truth table.
1086 
        //------------------------------------------------------------------------------
1087 
 
1088 
           //===============
1089 
        // default values
1090 
           //===============
1091 
        DISPATCH = 0;
1092 
        {ID_IF_ISSUE,ID_IF_JP} =  2'b00;
1093 
        {EX_IF_ISSUE,EX_IF_JP} =  2'b00;
1094 
        {EX_RDREG_X, EX_RDREG_Y, EX_WRREG_Z, WB_WRREG_W } =  4'b0000;
1095 11 thorn_aitc 
        // {EX_REGNUM_X,EX_REGNUM_Y,EX_REGNUM_Z,WB_REGNUM_W} = 16'hxxxx; // Thorn Aitch 2003/12/10
1096 
           {EX_REGNUM_X,EX_REGNUM_Y,EX_REGNUM_Z,WB_REGNUM_W} = 16'h0000;    // Thorn Aitch 2003/12/10
1097 2 thorn_aitc 
        {EX_ALUFUNC}  = `ALU_NOP;
1098 
        {EX_MULCOM1, EX_MULCOM2}   = 9'b000000000;
1099 
        {WB_MULCOM1, WB_MULCOM2}   = 9'b000000000;
1100 
        {EX_MACSEL1,EX_MACSEL2}   =  4'b0000;
1101 
        {WB_MACSEL1,WB_MACSEL2}   =  4'b0000;
1102 
        {EX_WRMACH,EX_WRMACL}     =  2'b00;
1103 
        {WB_WRMACH,WB_WRMACL}     =  2'b00;
1104 
        {EX_RDMACH_X,EX_RDMACL_X} = 2'b00;
1105 
        {EX_RDMACH_Y,EX_RDMACL_Y} = 2'b00;
1106 
        {WB_MAC_BUSY, EX_MAC_BUSY, MAC_STALL_SENSE} = 3'b000;
1107 
        {EX_RDSR_X, EX_RDSR_Y, EX_WRSR_Z, WB_WRSR_W}     = 4'b0000;
1108 
        {MAC_S_LATCH} = 1'b0;
1109 
        {EX_RDGBR_X, EX_RDGBR_Y, EX_WRGBR_Z, WB_WRGBR_W} = 4'b0000;
1110 
        {EX_RDVBR_X, EX_RDVBR_Y, EX_WRVBR_Z, WB_WRVBR_W} = 4'b0000;
1111 
        {EX_RDPR_X, EX_RDPR_Y, EX_WRPR_Z, WB_WRPR_W, EX_WRPR_PC} = 5'b00000;
1112 11 thorn_aitc 
        // {EX_MA_ISSUE,EX_MA_WR,EX_MA_SZ,EX_KEEP_CYC} =  5'b0xxxx; // Thorn Aitch 2003/12/10
1113 
           {EX_MA_ISSUE,EX_MA_WR,EX_MA_SZ,EX_KEEP_CYC} =  5'b00000;    // Thorn Aitch 2003/12/10
1114 2 thorn_aitc 
        {EX_WRMAAD_Z,EX_WRMADW_X,EX_WRMADW_Y,WB_RDMADR_W} = 4'b0000;
1115 
        {EX_RDPC_X,EX_RDPC_Y,EX_WRPC_Z,ID_INCPC} = 4'b0000;
1116 
        {ID_IFADSEL, EX_IFADSEL}                 = 2'b00;
1117 
        {EX_CONST_ZERO4,EX_CONST_ZERO42,EX_CONST_ZERO44} = 3'b000;
1118 
        {EX_CONST_ZERO8,EX_CONST_ZERO82,EX_CONST_ZERO84} = 3'b000;
1119 
        {EX_CONST_SIGN8,EX_CONST_SIGN82,EX_CONST_SIGN122} = 3'b000;
1120 
        {EX_RDCONST_X,EX_RDCONST_Y} = 2'b00;
1121 11 thorn_aitc 
        // {EX_CMPCOM}  = 3'bxxx;  // Thorn Aitch 2003/12/10
1122 
           {EX_CMPCOM}  = 3'b000;     // Thorn Aitch 2003/12/10
1123 
        // {EX_SFTFUNC} = 5'bxxxx; // Thorn Aitch 2003/12/10
1124 
           {EX_SFTFUNC} = 5'b0000;    // Thorn Aitch 2003/12/10
1125 2 thorn_aitc 
        {EX_RDSFT_Z} = 1'b0;
1126 
        {EX_T_CMPSET, EX_T_CRYSET, EX_T_TSTSET, EX_T_SFTSET} = 4'b0000;
1127 
        {EX_QT_DV1SET, EX_MQT_DV0SET} = 2'b00;
1128 
        {EX_T_CLR, EX_T_SET, EX_MQ_CLR} = 3'b000;
1129 
        {EX_RDTEMP_X, EX_WRTEMP_Z, EX_WRMAAD_TEMP} = 3'b000;
1130 
        {EX_FWD_W2X} = 1'b0;
1131 
        {EVENT_ACK_0, RST_SR, ILEVEL_CAP, WR_IBIT} = 4'b0000;
1132 
        {MASKINT_NEXT} = 1'b0;
1133 
        {SLP} = 1'b0;
1134 
        {DELAY_JUMP} = 1'b0;
1135 
 
1136 
        //============================================
1137 
        // Line 0xxx
1138 
        //============================================
1139 
        casex (INSTR_STATE[15:12])
1140 
          4'b0000 : // 0xxx
1141 
        //------------------
1142 
        // STC SR,  Rn (0n02)
1143 
        // STC GBR, Rn (0n12)
1144 
        // STC VBR, Rn (0n22)
1145 
        //------------------
1146 
            casex (INSTR_STATE[3:0])
1147 
              4'b0010 : // 0xx2
1148 
                begin
1149 
                  casex (INSTR_STATE[5:4])
1150 
                    2'b00   : EX_RDSR_Y  = 1'b1;
1151 
                    2'b01   : EX_RDGBR_Y = 1'b1;
1152 
                    2'b1?   : EX_RDVBR_Y = 1'b1;
1153 
                    default : ;
1154 
                  endcase
1155 
                  EX_ALUFUNC = `ALU_THRUY;
1156 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1157 
                  EX_WRREG_Z = 1'b1;
1158 
                  ID_INCPC = 1'b1;
1159 
                  ID_IF_ISSUE = 1'b1;
1160 
                  DISPATCH = 1'b1;
1161 
                end
1162 
        //---------------
1163 
        // BSRF Rm (0m03)
1164 
        // BRAF Rm (0m23)
1165 
        //---------------
1166 
              4'b0011 : // 0xx3
1167 
                begin
1168 
                  case (INSTR_SEQ)
1169 
                    0: begin
1170 
                         EX_RDPC_X = 1'b1;
1171 
                         EX_RDREG_Y = 1'b1;
1172 
                         EX_REGNUM_Y = INSTR_STATE[11:8];
1173 
                         EX_ALUFUNC = `ALU_ADD;
1174 
                         EX_WRPC_Z = 1'b1;
1175 
                         if (~INSTR_STATE[5]) EX_WRPR_PC = 1; // BSRF operation
1176 
                         ID_INCPC = 1'b1;
1177 
                       end
1178 
                    1: begin
1179 
                         ID_IF_ISSUE = 1'b1;
1180 
                         ID_IFADSEL = 1'b1;
1181 
                         ID_IF_JP = 1'b1;
1182 
                         DISPATCH = 1'b1;
1183 
                         DELAY_JUMP = 1'b1;
1184 
                       end
1185 
                    default : ;
1186 
                  endcase
1187 
                end
1188 
        //---------------------------
1189 
        // MUL.L Rm, Rn        (0nm7)
1190 
        //---------------------------
1191 
              4'b01?? : // 0xx4, 0xx5, 0xx6, 0xx7
1192 
                begin
1193 
                  if (INSTR_STATE[1:0] == 2'b11) // 0xx7
1194 
                    begin
1195 
                      MAC_STALL_SENSE = 1'b1;
1196 
                      EX_MAC_BUSY = (NEXT_ID_STALL)? 1'b0:1'b1;
1197 
                      EX_RDREG_X = 1'b1;
1198 
                      EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1199 
                      EX_RDREG_Y = 1'b1;
1200 
                      EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1201 
                      EX_MACSEL1 = 2'b00; // XBUS -> MACIN1
1202 
                      EX_MACSEL2 = 2'b00; // YBUS -> MACIN2
1203 
                      EX_MULCOM1 = 1'b1;
1204 
                      EX_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
1205 
                      ID_INCPC = 1'b1;
1206 
                      ID_IF_ISSUE = 1'b1;
1207 
                      DISPATCH = 1'b1;
1208 
                    end
1209 
        //---------------------------
1210 
        // MOV.B Rm, @(R0, Rn) (0nm4)
1211 
        // MOV.W Rm, @(R0, Rn) (0nm5)
1212 
        // MOV.L Rm, @(R0, Rn) (0nm6)
1213 
        //---------------------------
1214 
                  else // 0xx4, 0xx5, 0xx6
1215 
                    begin
1216 
                      EX_RDREG_X = 1'b1;
1217 
                      EX_REGNUM_X = INSTR_STATE[11:8]; //Rn
1218 
                      EX_ALUFUNC = `ALU_ADDR0; //@(R0, Rn)
1219 
                      EX_WRMAAD_Z = 1'b1;
1220 
                      EX_RDREG_Y = 1'b1;
1221 
                      EX_REGNUM_Y = INSTR_STATE[7:4];  //Rm
1222 
                      EX_WRMADW_Y = 1'b1;
1223 
                      {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
1224 
                      EX_MA_SZ = INSTR_STATE[1:0];
1225 
                      ID_INCPC = 1'b1;
1226 
                      ID_IF_ISSUE = 1'b1;
1227 
                      DISPATCH = 1'b1;
1228 
                    end
1229 
                  end
1230 
        //--------------
1231 
        // CLRT   (0008)
1232 
        // SETT   (0018)
1233 
        // CLRMAC (0028)
1234 
        //--------------
1235 
              4'b1000 : // 0xx8
1236 
                begin
1237 
                  casex (INSTR_STATE[5:4])
1238 
                    2'b00   : EX_T_CLR = 1'b1;
1239 
                    2'b01   : EX_T_SET = 1'b1;
1240 
                    2'b1?   : {EX_WRMACH, EX_WRMACL, MAC_STALL_SENSE} = 3'b111;
1241 
                    default : ;
1242 
                  endcase
1243 
                  ID_INCPC = 1'b1;
1244 
                  ID_IF_ISSUE = 1'b1;
1245 
                  DISPATCH = 1'b1;
1246 
                end
1247 
        //---------------
1248 
        // NOP (0009)
1249 
        //---------------
1250 
              4'b1001 : // 0xx9
1251 
                begin
1252 
                  if(INSTR_STATE[5:4] == 2'b00) //(don't care INSTR_STATE[11:6])
1253 
                    begin // ID
1254 
                      ID_INCPC = 1'b1;
1255 
                      ID_IF_ISSUE = 1'b1;
1256 
                      DISPATCH = 1'b1;
1257 
                    end
1258 
        //---------------
1259 
        // DIV0U (0019)
1260 
        //---------------
1261 
                  else if (INSTR_STATE[5:4] == 2'b01) //(don't care INSTR_STATE[11:6])
1262 
                    begin
1263 
                      EX_T_CLR = 1'b1;
1264 
                      EX_MQ_CLR = 1'b1;
1265 
                      ID_INCPC = 1'b1;
1266 
                      ID_IF_ISSUE = 1'b1;
1267 
                      DISPATCH = 1'b1;
1268 
                    end
1269 
        //---------------
1270 
        // MOVT Rn (0n29)
1271 
        //---------------
1272 
                  else
1273 
                    begin
1274 
                      if (T_BCC) EX_ALUFUNC = `ALU_INCX; // if T=1 then 1->Rn else 0->Rn
1275 
                      EX_WRREG_Z = 1'b1;
1276 
                      EX_REGNUM_Z = INSTR_STATE[11:8];
1277 
                      ID_INCPC = 1'b1;
1278 
                      ID_IF_ISSUE = 1'b1;
1279 
                      DISPATCH = 1'b1;
1280 
                    end
1281 
                end
1282 
        //--------------------
1283 
        // STS MACH, Rn (0n0A)
1284 
        // STS MACL, Rn (0n1A)
1285 
        // STS PR  , Rn (0n2A)
1286 
        //--------------------
1287 
              4'b1010 : // 0xxA
1288 
                begin
1289 
                  casex (INSTR_STATE[5:4])
1290 
                    2'b00   : // don't care INSTR_STATE[7:6]
1291 
                              {EX_RDMACH_Y, MAC_STALL_SENSE} = 2'b11;
1292 
                    2'b01   : // don't care INSTR_STATE[7:6]
1293 
                              {EX_RDMACL_Y, MAC_STALL_SENSE} = 2'b11;
1294 
                    2'b1?   : EX_RDPR_Y = 1'b1;   // don't care INSTR_STATE[7:6],[4]
1295 
                    default : ;
1296 
                  endcase
1297 
                  EX_ALUFUNC = `ALU_THRUY;
1298 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1299 
                  EX_WRREG_Z = 1'b1;
1300 
                  ID_INCPC = 1'b1;
1301 
                  ID_IF_ISSUE = 1'b1;
1302 
                  DISPATCH = 1'b1;
1303 
                end
1304 
        //-----------
1305 
        // RTS (000B)
1306 
        //-----------
1307 
              4'b1011 : // 0xxB
1308 
                begin
1309 
                  if(INSTR_STATE[5:4] == 2'b00) // 000B (don't care INSTR_STATE[11:6])
1310 
                    case (INSTR_SEQ)
1311 
                      0: begin
1312 
                           EX_RDPR_Y = 1'b1;
1313 
                           EX_ALUFUNC = `ALU_THRUY;
1314 
                           EX_WRPC_Z = 1'b1;
1315 
                         end
1316 
                      1: begin
1317 
                           ID_IF_ISSUE = 1'b1;
1318 
                           ID_IFADSEL = 1'b1;
1319 
                           ID_IF_JP = 1'b1;
1320 
                           DISPATCH = 1'b1;
1321 
                           DELAY_JUMP = 1'b1;
1322 
                         end
1323 
                      default : ;
1324 
                    endcase
1325 
        //-----------
1326 
        // RTE (002B)
1327 
        //-----------
1328 
                  else if(INSTR_STATE[5:4] == 2'b10) // 002B (don't care INSTR_STATE[11:6])
1329 
                    case (INSTR_SEQ)
1330 
                      0: begin
1331 
                           EX_RDREG_X = 1'b1;
1332 
                           EX_REGNUM_X = 4'hF;
1333 
                           EX_ALUFUNC = `ALU_INCX4;
1334 
                           EX_WRREG_Z = 1'b1;
1335 
                           EX_REGNUM_Z = 4'hF;
1336 
                           EX_WRMAAD_Z = 0; // MAAD = XBUS
1337 
                           {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1338 
                           EX_MA_SZ = 2'b10;
1339 
                           WB_RDMADR_W = 1'b1;
1340 
                           ID_INCPC = 1'b1;
1341 
                         end
1342 
                      1: begin
1343 
                           EX_RDREG_X = 1'b1;
1344 
                           EX_REGNUM_X = 4'hF;
1345 
                           EX_ALUFUNC = `ALU_INCX4;
1346 
                           EX_WRREG_Z = 1'b1;
1347 
                           EX_REGNUM_Z = 4'hF;
1348 
                           EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
1349 
                           {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1350 
                           EX_MA_SZ = 2'b10;
1351 
                           WB_RDMADR_W = 1'b1;
1352 
                           WB_WRSR_W = 1'b1;
1353 
                         end
1354 
                      2: begin
1355 
                           EX_ALUFUNC = `ALU_THRUW;
1356 
                           EX_WRPC_Z = 1'b1;
1357 
                         end
1358 
                      3: begin
1359 
                           ID_IF_ISSUE = 1'b1;
1360 
                           ID_IFADSEL = 1'b1;
1361 
                           ID_IF_JP = 1'b1;
1362 
                           DISPATCH = 1'b1;
1363 
                           DELAY_JUMP = 1'b1;
1364 
                         end
1365 
                      default : ;
1366 
                    endcase
1367 
        //-------------
1368 
        // SLEEP (001B)
1369 
        //-------------
1370 
                  else // 001B
1371 
                    case (INSTR_SEQ)
1372 
                      0: begin
1373 
                         end
1374 
                      1: begin
1375 
                           SLP = 1'b1;
1376 
                         end
1377 
                      2: begin
1378 
                         end
1379 
                      3: begin
1380 
                           ID_INCPC = 1'b1;
1381 
                           ID_IF_ISSUE = 1'b1;
1382 
                           DISPATCH = 1'b1;
1383 
                         end
1384 
                    endcase
1385 
                end
1386 
        //------------------------
1387 
        // MAC.L @Rm+, @Rn+ (0nmF)
1388 
        //------------------------
1389 
              4'b11?? : // 0xxC, 0xxD, 0xxE, 0xxF
1390 
                begin
1391 
                  if (INSTR_STATE[1:0] == 2'b11)
1392 
                    case (INSTR_SEQ)
1393 
                      0: begin
1394 
                           EX_RDREG_X = 1'b1;
1395 
                           EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn+
1396 
                           EX_ALUFUNC = `ALU_INCX4;
1397 
                           EX_WRREG_Z = 1'b1;
1398 
                           EX_REGNUM_Z = INSTR_STATE[11:8]; //@Rn+
1399 
                           EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
1400 
                           {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1401 
                           EX_MA_SZ = 2'b10;
1402 
                           WB_RDMADR_W = 1'b1;
1403 
                           WB_MACSEL1 = 2'b10; // WBUS -> MACIN1
1404 
                           WB_MULCOM1 = 1'b1;
1405 
                         end
1406 
                      1: begin
1407 
                           WB_MAC_BUSY = 1'b1;
1408 
                           MAC_S_LATCH = 1'b1;
1409 
                           EX_RDREG_X = 1'b1;
1410 
                           EX_REGNUM_X = INSTR_STATE[7:4]; //@Rm+
1411 
                           EX_ALUFUNC = `ALU_INCX4;
1412 
                           EX_WRREG_Z = 1'b1;
1413 
                           EX_REGNUM_Z = INSTR_STATE[7:4]; //@Rm+
1414 
                           EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
1415 
                           {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1416 
                           EX_MA_SZ = 2'b10;
1417 
                           WB_RDMADR_W = 1'b1;
1418 
                           WB_MACSEL2 = 2'b10; // WBUS -> MACIN2
1419 
                           WB_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
1420 
                           ID_INCPC = 1'b1;
1421 
                           ID_IF_ISSUE = 1'b1;
1422 
                           DISPATCH = 1'b1;
1423 
                         end
1424 
                      default : ;
1425 
                    endcase
1426 
        //------------------------------
1427 
        // MOV.B    @(R0, Rm), Rn (0nmC)
1428 
        // MOV.W    @(R0, Rm), Rn (0nmD)
1429 
        // MOV.L    @(R0, Rm), Rn (0nmE)
1430 
        //------------------------------
1431 
                  else
1432 
                    begin
1433 
                       EX_RDREG_X = 1'b1;
1434 
                       EX_REGNUM_X = INSTR_STATE[7:4]; //Rm
1435 
                       EX_ALUFUNC = `ALU_ADDR0; //@(R0, Rm)
1436 
                       EX_WRMAAD_Z = 1'b1;
1437 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1438 
                       EX_MA_SZ = INSTR_STATE[1:0];
1439 
                       WB_RDMADR_W = 1'b1;
1440 
                       WB_WRREG_W = 1'b1;
1441 
                       WB_REGNUM_W = INSTR_STATE[11:8]; //Rn
1442 
                       ID_INCPC = 1'b1;
1443 
                       ID_IF_ISSUE = 1'b1;
1444 
                       DISPATCH = 1'b1;
1445 
                    end
1446 
                end
1447 
        //---------------
1448 
        // Default = NOP
1449 
        //---------------
1450 
              default :
1451 
                begin
1452 
                  ID_INCPC = 1'b1;
1453 
                  ID_IF_ISSUE = 1'b1;
1454 
                  DISPATCH = 1'b1;
1455 
                end
1456 
            endcase
1457 
        //============================================
1458 
        // Line 1xxx
1459 
        //============================================
1460 
        //-----------------------------
1461 
        // MOV.L Rm, @(disp, Rn) (1nmd)
1462 
        //-----------------------------
1463 
          4'b0001 : // 1xxx
1464 
            begin
1465 
                EX_RDREG_X = 1'b1;
1466 
                EX_REGNUM_X = INSTR_STATE[11:8]; //Rn
1467 
                EX_CONST_ZERO44 = 1'b1;
1468 
                EX_ALUFUNC = `ALU_ADDCN; //@(disp, Rn)
1469 
                EX_WRMAAD_Z = 1'b1;
1470 
                EX_RDREG_Y = 1'b1;
1471 
                EX_REGNUM_Y = INSTR_STATE[7:4];  //Rm
1472 
                EX_WRMADW_Y = 1'b1;
1473 
                {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
1474 
                EX_MA_SZ = 2'b10;
1475 
                ID_INCPC = 1'b1;
1476 
                ID_IF_ISSUE = 1'b1;
1477 
                DISPATCH = 1'b1;
1478 
            end
1479 
        //============================================
1480 
        // Line 2xxx
1481 
        //============================================
1482 
          4'b0010 : // 2xxx
1483 
            casex (INSTR_STATE[3:0])
1484 
        //-----------------------------------
1485 
        // MOV.L/W/B Rm, @Rn (2nm2/2nm1/2nm0)
1486 
        //-----------------------------------
1487 
              4'b00?? : // 2xx0, 2xx1, 2xx2 (don't care 2xx3)
1488 
                begin
1489 
                  EX_RDREG_X = 1'b1;
1490 
                  EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn
1491 
                  EX_RDREG_Y = 1'b1;
1492 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
1493 
                  EX_WRMADW_Y = 1'b1;
1494 
                  EX_ALUFUNC = `ALU_THRUX;
1495 
                  EX_WRMAAD_Z = 1'b1;
1496 
                  {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
1497 
                  EX_MA_SZ = INSTR_STATE[1:0];
1498 
                  ID_INCPC = 1'b1;
1499 
                  ID_IF_ISSUE = 1'b1;
1500 
                  DISPATCH = 1'b1;
1501 
                end
1502 
        //------------------------------------
1503 
        // MOV.L/W/B Rm, @-Rn (2nm6/2nm5/2nm4)
1504 
        // DIV0S              (2nm7)
1505 
        //------------------------------------
1506 
              4'b01?? : // 2xx4, 2xx5, 2xx6, 2xx7
1507 
                begin
1508 
                  if (INSTR_STATE[1:0] == 2'b11) // 2xx7
1509 
                    begin
1510 
                       EX_RDREG_X = 1'b1;
1511 
                       EX_REGNUM_X = INSTR_STATE[11:8]; //Rn
1512 
                       EX_RDREG_Y = 1'b1;
1513 
                       EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
1514 
                       EX_MQT_DV0SET = 1'b1;
1515 
                       ID_INCPC = 1'b1;
1516 
                       ID_IF_ISSUE = 1'b1;
1517 
                       DISPATCH = 1'b1;
1518 
                    end
1519 
                  else // 2xx4, 2xx5, 2xx6
1520 
                    begin
1521 
                       EX_RDREG_X = 1'b1;
1522 
                       EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn
1523 
                       case (INSTR_STATE[1:0])
1524 
                           2'b00   : EX_ALUFUNC = `ALU_DECX;
1525 
                           2'b01   : EX_ALUFUNC = `ALU_DECX2;
1526 
                           2'b10   : EX_ALUFUNC = `ALU_DECX4;
1527 
                           default : EX_ALUFUNC = `ALU_NOP;
1528 
                       endcase
1529 
                       EX_WRREG_Z = 1'b1;
1530 
                       EX_REGNUM_Z = INSTR_STATE[11:8]; // @-Rn
1531 
                       EX_WRMAAD_Z = 1'b1;
1532 
                       EX_RDREG_Y = 1'b1;
1533 
                       EX_REGNUM_Y = INSTR_STATE[7:4]; //Rm
1534 
                       EX_WRMADW_Y = 1'b1;
1535 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
1536 
                       EX_MA_SZ = INSTR_STATE[1:0];
1537 
                       ID_INCPC = 1'b1;
1538 
                       ID_IF_ISSUE = 1'b1;
1539 
                       DISPATCH = 1'b1;
1540 
                    end
1541 
                end
1542 
        //------------------
1543 
        // TST Rm, Rn (2nm8)
1544 
        // AND Rm, Rn (2nm9)
1545 
        // XOR Rm, Rn (2nmA)
1546 
        // OR  Rm, Rn (2nmB)
1547 
        //------------------
1548 
              4'b10?? : // 2xx8, 2xx9, 2xxA, 2xxB
1549 
                begin
1550 
                  EX_RDREG_X = 1'b1;
1551 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1552 
                  EX_RDREG_Y = 1'b1;
1553 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1554 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1555 
                  case (INSTR_STATE[1:0])
1556 
                      2'b00   : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_AND, 1'b0, 1'b1};
1557 
                      2'b01   : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_AND, 1'b1, 1'b0};
1558 
                      2'b10   : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_XOR, 1'b1, 1'b0};
1559 
                      2'b11   : {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_OR , 1'b1, 1'b0};
1560 
                      default : ;
1561 
                  endcase
1562 
                  ID_INCPC = 1'b1;
1563 
                  ID_IF_ISSUE = 1'b1;
1564 
                  DISPATCH = 1'b1;
1565 
                end
1566 
        //----------------------
1567 
        // CMP/STR Rm, Rn (2nmC)
1568 
        //----------------------
1569 
              4'b1100 : // 2xxC
1570 
                begin
1571 
                  EX_RDREG_X = 1'b1;
1572 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1573 
                  EX_RDREG_Y = 1'b1;
1574 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1575 
                  EX_CMPCOM = INSTR_STATE[2:0];
1576 
                  EX_T_CMPSET = 1'b1;
1577 
                  ID_INCPC = 1'b1;
1578 
                  ID_IF_ISSUE = 1'b1;
1579 
                  DISPATCH = 1'b1;
1580 
                end
1581 
        //--------------------
1582 
        // XTRCT Rm, Rn (2nmD)
1583 
        //--------------------
1584 
              4'b1101 : // 2xxD
1585 
                begin
1586 
                  EX_RDREG_X = 1'b1;
1587 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1588 
                  EX_RDREG_Y = 1'b1;
1589 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1590 
                  EX_ALUFUNC = `ALU_XTRCT;
1591 
                  EX_WRREG_Z = 1'b1;
1592 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1593 
                  ID_INCPC = 1'b1;
1594 
                  ID_IF_ISSUE = 1'b1;
1595 
                  DISPATCH = 1'b1;
1596 
                end
1597 
        //-----------------------------
1598 
        // MULU/S.W Rm, Rn (2nmE/2nmF)
1599 
        //-----------------------------
1600 
              4'b111? : // 2nmE/2nmF
1601 
                begin
1602 
                  MAC_STALL_SENSE = 1'b1;
1603 
                  EX_MAC_BUSY = (NEXT_ID_STALL)? 1'b0:1'b1;
1604 
                  EX_RDREG_X = 1'b1;
1605 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1606 
                  EX_RDREG_Y = 1'b1;
1607 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1608 
                  EX_MACSEL1 = 2'b00; // XBUS -> MACIN1
1609 
                  EX_MACSEL2 = 2'b00; // YBUS -> MACIN2
1610 
                  EX_MULCOM1 = 1'b1;
1611 
                  EX_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
1612 
                  ID_INCPC = 1'b1;
1613 
                  ID_IF_ISSUE = 1'b1;
1614 
                  DISPATCH = 1'b1;
1615 
                end
1616 
        //---------------
1617 
        // Default = NOP
1618 
        //---------------
1619 
              default :
1620 
                begin
1621 
                  ID_INCPC = 1'b1;
1622 
                  ID_IF_ISSUE = 1'b1;
1623 
                  DISPATCH = 1'b1;
1624 
                end
1625 
            endcase
1626 
        //============================================
1627 
        // Line 3xxx
1628 
        //============================================
1629 
          4'b0011 : // 3xxx
1630 
            casex (INSTR_STATE[3:0])
1631 
        //--------------------------------------------------------------
1632 
        // CMP/xx Rm, Rn (EQ, HS, GE, HI, GT) (3nm0/3nm2/3nm3/3nm6/3nm7)
1633 
        //--------------------------------------------------------------
1634 
              4'b0000 : // 3xx0
1635 
                begin
1636 
                  EX_RDREG_X = 1'b1;
1637 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1638 
                  EX_RDREG_Y = 1'b1;
1639 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1640 
                  EX_CMPCOM = INSTR_STATE[2:0];
1641 
                  EX_T_CMPSET = 1'b1;
1642 
                  ID_INCPC = 1'b1;
1643 
                  ID_IF_ISSUE = 1'b1;
1644 
                  DISPATCH = 1'b1;
1645 
                end
1646 
              4'b0?1? : // 3xx2, 3xx3, 3xx6, 3xx7
1647 
                begin
1648 
                  EX_RDREG_X = 1'b1;
1649 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1650 
                  EX_RDREG_Y = 1'b1;
1651 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1652 
                  EX_CMPCOM = INSTR_STATE[2:0];
1653 
                  EX_T_CMPSET = 1'b1;
1654 
                  ID_INCPC = 1'b1;
1655 
                  ID_IF_ISSUE = 1'b1;
1656 
                  DISPATCH = 1'b1;
1657 
                end
1658 
        //------------
1659 
        // DIV1 (3nm4)
1660 
        //------------
1661 
              4'b0100 : // 3nm4
1662 
                begin
1663 
                  EX_RDREG_X = 1'b1;
1664 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1665 
                  EX_RDREG_Y = 1'b1;
1666 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1667 
 
1668 
                  EX_SFTFUNC = `ROTCL;
1669 
                  EX_ALUFUNC = `ALU_DIV;
1670 
 
1671 
                  EX_QT_DV1SET = 1'b1;
1672 
                  EX_WRREG_Z = 1'b1;
1673 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1674 
                  ID_INCPC = 1'b1;
1675 
                  ID_IF_ISSUE = 1'b1;
1676 
                  DISPATCH = 1'b1;
1677 
                end
1678 
        //-----------------------------
1679 
        // DMULU/S.L Rm, Rn (3nm5/3nmD)
1680 
        //-----------------------------
1681 
              4'b?101 : // 3nm5/3nmD
1682 
                begin
1683 
                  MAC_STALL_SENSE = 1'b1;
1684 
                  EX_MAC_BUSY = (NEXT_ID_STALL)? 1'b0:1'b1;
1685 
                  EX_RDREG_X = 1'b1;
1686 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1687 
                  EX_RDREG_Y = 1'b1;
1688 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1689 
                  EX_MACSEL1 = 2'b00; // XBUS -> MACIN1
1690 
                  EX_MACSEL2 = 2'b00; // YBUS -> MACIN2
1691 
                  EX_MULCOM1 = 1'b1;
1692 
                  EX_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
1693 
                  ID_INCPC = 1'b1;
1694 
                  ID_IF_ISSUE = 1'b1;
1695 
                  DISPATCH = 1'b1;
1696 
                end
1697 
        //------------------
1698 
        // SUB Rm, Rn (3nm8)
1699 
        // ADD Rm, Rn (3nmC)
1700 
        //------------------
1701 
              4'b1?00 : // 3xx8, 3xxC
1702 
                begin
1703 
                  EX_RDREG_X = 1'b1;
1704 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1705 
                  EX_RDREG_Y = 1'b1;
1706 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1707 
                  case (INSTR_STATE[2])
1708 
                      1'b0 : EX_ALUFUNC = `ALU_SUB;
1709 
                      1'b1 : EX_ALUFUNC = `ALU_ADD;
1710 
                      default : ;
1711 
                  endcase
1712 
                  EX_WRREG_Z = 1'b1;
1713 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1714 
                  ID_INCPC = 1'b1;
1715 
                  ID_IF_ISSUE = 1'b1;
1716 
                  DISPATCH = 1'b1;
1717 
                end
1718 
        //-------------------
1719 
        // SUBC Rm, Rn (3nmA)
1720 
        // SUBV Rm, Rn (3nmB)
1721 
        // ADDC Rm, Rn (3nmE)
1722 
        // ADDV Rm, Rn (3nmF)
1723 
        //-------------------
1724 
              4'b1?1? : // 3xxA, 3xxB, 3xxE, 3xxF
1725 
                begin
1726 
                  EX_RDREG_X = 1'b1;
1727 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1728 
                  EX_RDREG_Y = 1'b1;
1729 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
1730 
                  case ({INSTR_STATE[2], INSTR_STATE[0]})
1731 
                      2'b00 : EX_ALUFUNC = `ALU_SUBC;
1732 
                      2'b01 : EX_ALUFUNC = `ALU_SUBV;
1733 
                      2'b10 : EX_ALUFUNC = `ALU_ADDC;
1734 
                      2'b11 : EX_ALUFUNC = `ALU_ADDV;
1735 
                      default : ;
1736 
                  endcase
1737 
                  EX_T_CRYSET = 1'b1;
1738 
                  EX_WRREG_Z = 1'b1;
1739 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1740 
                  ID_INCPC = 1'b1;
1741 
                  ID_IF_ISSUE = 1'b1;
1742 
                  DISPATCH = 1'b1;
1743 
                end
1744 
        //---------------
1745 
        // Default = NOP
1746 
        //---------------
1747 
              default :
1748 
                begin
1749 
                  ID_INCPC = 1'b1;
1750 
                  ID_IF_ISSUE = 1'b1;
1751 
                  DISPATCH = 1'b1;
1752 
                end
1753 
            endcase
1754 
        //============================================
1755 
        // Line 4xxx
1756 
        //============================================
1757 
          4'b0100 : // 4xxx
1758 
            casex (INSTR_STATE[5:0])
1759 
        //------------------------
1760 
        // SHLL   Rn (4n00) 000000
1761 
        // SHAL   Rn (4n20) 100000
1762 
        // SHLR   Rn (4n01) 000001
1763 
        // SHAR   Rn (4n21) 100001
1764 
        // ROTL   Rn (4n04) 000100
1765 
        // ROTCL  Rn (4n24) 100100
1766 
        // ROTR   Rn (4n05) 000101
1767 
        // ROTCR  Rn (4n25) 100101
1768 
        //------------------------
1769 
              6'b?00?0? :
1770 
                begin
1771 
                  EX_RDREG_X = 1'b1;
1772 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1773 
                  EX_SFTFUNC = {INSTR_STATE[5:2], INSTR_STATE[0]};
1774 
                  EX_T_SFTSET = 1'b1;
1775 
                  EX_RDSFT_Z = 1'b1;
1776 
                  EX_WRREG_Z = 1'b1;
1777 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1778 
                  ID_INCPC = 1'b1;
1779 
                  ID_IF_ISSUE = 1'b1;
1780 
                  DISPATCH = 1'b1;
1781 
                end
1782 
        //------------------------
1783 
        // SHLL2  Rn (4n08) 001000
1784 
        // SHLL8  Rn (4n18) 011000
1785 
        // SHLL16 Rn (4n28) 101000
1786 
        // SHLR2  Rn (4n09) 001001
1787 
        // SHLR8  Rn (4n19) 011001
1788 
        // SHLR16 Rn (4n29) 101001
1789 
        //------------------------
1790 
              6'b??100? :
1791 
                begin
1792 
                  EX_RDREG_X = 1'b1;
1793 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1794 
                  EX_SFTFUNC = {INSTR_STATE[5:2], INSTR_STATE[0]};
1795 
                  EX_RDSFT_Z = 1'b1;
1796 
                  EX_WRREG_Z = 1'b1;
1797 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1798 
                  ID_INCPC = 1'b1;
1799 
                  ID_IF_ISSUE = 1'b1;
1800 
                  DISPATCH = 1'b1;
1801 
                end
1802 
        //-------------
1803 
        // DT Rn (4n10)
1804 
        //-------------
1805 
              6'b010000 : // 4x10 (don't care INSTR_STATE[7:6])
1806 
                begin
1807 
                  EX_RDREG_X = 1'b1;
1808 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1809 
                  EX_ALUFUNC = `ALU_DECX;
1810 
                  EX_T_TSTSET = 1'b1;
1811 
                  EX_WRREG_Z = 1'b1;
1812 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
1813 
                  ID_INCPC = 1'b1;
1814 
                  ID_IF_ISSUE = 1'b1;
1815 
                  DISPATCH = 1'b1;
1816 
                end
1817 
        //-------------------------------
1818 
        // CMP/xx Rn (PL, PZ) (4n15/4n11)
1819 
        //-------------------------------
1820 
              6'b010?01 : // 4x11, 4x15 (don't care INSTR_STATE[7:6])
1821 
                begin
1822 
                  EX_RDREG_X = 1'b1;
1823 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
1824 
                  EX_CMPCOM = INSTR_STATE[2:0]; //Y-BUS is default zero
1825 
                  EX_T_CMPSET = 1'b1;
1826 
                  ID_INCPC = 1'b1;
1827 
                  ID_IF_ISSUE = 1'b1;
1828 
                  DISPATCH = 1'b1;
1829 
                end
1830 
        //------------------------
1831 
        // STS.L MACH, @-Rn (4n02)
1832 
        // STS.L MACL, @-Rn (4n12)
1833 
        // STS.L PR,   @-Rn (4n22)
1834 
        //------------------------
1835 
              6'b??0010 : // 4xx2 (don't care INSTR_STATE[7:6])
1836 
                begin
1837 
                  casex (INSTR_STATE[5:4])
1838 
                    2'b00   : // don't care INSTR_STATE[7:6]
1839 
                              begin
1840 
                                {EX_RDMACH_Y, MAC_STALL_SENSE} = 2'b11;
1841 
                              end
1842 
                    2'b01   : // don't care INSTR_STATE[7:6]
1843 
                              begin
1844 
                                {EX_RDMACL_Y, MAC_STALL_SENSE} = 2'b11;
1845 
                              end
1846 
                    2'b1?   : EX_RDPR_Y = 1'b1;   // don't care INSTR_STATE[7:6],[4]
1847 
                    default : ;
1848 
                  endcase
1849 
                  EX_RDREG_X = 1'b1;
1850 
                  EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn
1851 
                  EX_ALUFUNC = `ALU_DECX4;
1852 
                  EX_WRREG_Z = 1'b1;
1853 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // @-Rn
1854 
                  EX_WRMAAD_Z = 1'b1;
1855 
                  EX_WRMADW_Y = 1'b1;
1856 
                  {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
1857 
                  EX_MA_SZ = 2'b10;
1858 
                  ID_INCPC = 1'b1;
1859 
                  ID_IF_ISSUE = 1'b1;
1860 
                  DISPATCH = 1'b1;
1861 
                end
1862 
        //-----------------------
1863 
        // STC.L SR,  @-Rn (4n03)
1864 
        // STC.L GBR, @-Rn (4n13)
1865 
        // STC.L VBR, @-Rn (4n23)
1866 
        //-----------------------
1867 
              6'b??0011 : // 4xx3 (don't care INSTR_STATE[7:6])
1868 
                begin
1869 
                  case (INSTR_SEQ)
1870 
                    0: begin
1871 
                         EX_RDREG_X = 1'b1;
1872 
                         EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn
1873 
                         EX_ALUFUNC = `ALU_DECX4;
1874 
                         EX_WRREG_Z = 1'b1;
1875 
                         EX_REGNUM_Z = INSTR_STATE[11:8]; // @-Rn
1876 
                         EX_WRMAAD_Z = 1'b1;
1877 
                         casex (INSTR_STATE[5:4])
1878 
                           2'b00   : EX_RDSR_Y  = 1'b1;
1879 
                           2'b01   : EX_RDGBR_Y = 1'b1;
1880 
                           2'b1?   : EX_RDVBR_Y = 1'b1;
1881 
                           default : ;
1882 
                         endcase
1883 
                         EX_WRMADW_Y = 1'b1;
1884 
                         {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
1885 
                         EX_MA_SZ = 2'b10;
1886 
                       end
1887 
                    1: begin
1888 
                         ID_INCPC = 1'b1;
1889 
                         ID_IF_ISSUE = 1'b1;
1890 
                         DISPATCH = 1'b1;
1891 
                       end
1892 
                    default: ;
1893 
                  endcase
1894 
                end
1895 
        //----------------------
1896 
        // LDS.L @Rm+, MACH (4m06)
1897 
        // LDS.L @Rm+, MACL (4m16)
1898 
        // LDS.L @Rm+, PR   (4m26)
1899 
        //----------------------
1900 
              6'b??0110 : // 4xx6 (don't care INSTR_STATE[7:6])
1901 
                begin
1902 
                  EX_RDREG_X = 1'b1;
1903 
                  EX_REGNUM_X = INSTR_STATE[11:8]; //@Rm
1904 
                  EX_ALUFUNC = `ALU_INCX4;
1905 
                  EX_WRREG_Z = 1'b1;
1906 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // @Rm+
1907 
                  EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
1908 
                  {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1909 
                  EX_MA_SZ = 2'b10;
1910 
                  WB_RDMADR_W = 1'b1;
1911 
                  casex (INSTR_STATE[5:4])
1912 
                    2'b00   : begin
1913 
                                {WB_MACSEL1, WB_WRMACH, MAC_STALL_SENSE} = 4'b1011; // from WBUS
1914 
                                WB_MAC_BUSY = (NEXT_ID_STALL)? 1'b0:1'b1;
1915 
                              end
1916 
                    2'b01   : begin
1917 
                                {WB_MACSEL2, WB_WRMACL, MAC_STALL_SENSE} = 4'b1011; // from WBUS
1918 
                                WB_MAC_BUSY = (NEXT_ID_STALL)? 1'b0:1'b1;
1919 
                              end
1920 
                    2'b1?   : WB_WRPR_W = 1'b1; // don't care INSTR_STATE[7:6],[4]
1921 
                    default : ;
1922 
                  endcase
1923 
                  ID_INCPC = 1'b1;
1924 
                  ID_IF_ISSUE = 1'b1;
1925 
                  DISPATCH = 1'b1;
1926 
                end
1927 
        //-----------------------
1928 
        // LDC.L @Rm+, SR  (4n07)
1929 
        // LDC.L @Rm+, GBR (4n17)
1930 
        // LDC.L @Rm+, VBR (4n27)
1931 
        //-----------------------
1932 
              6'b??0111 : // 4xx7 (don't care INSTR_STATE[7:6])
1933 
                begin
1934 
                  case (INSTR_SEQ)
1935 
                    0: begin  // ID
1936 
                         EX_RDREG_X = 1'b1;
1937 
                         EX_REGNUM_X = INSTR_STATE[11:8]; //@Rm
1938 
                         EX_ALUFUNC = `ALU_INCX4;
1939 
                         EX_WRREG_Z = 1'b1;
1940 
                         EX_REGNUM_Z = INSTR_STATE[11:8]; // @-Rm
1941 
                         EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
1942 
                         {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
1943 
                         EX_MA_SZ = 2'b10;
1944 
                         WB_RDMADR_W = 1'b1;
1945 
                         casex (INSTR_STATE[5:4])
1946 
                           2'b00   : WB_WRSR_W  = 1'b1;
1947 
                           2'b01   : WB_WRGBR_W = 1'b1;
1948 
                           2'b1?   : WB_WRVBR_W = 1'b1;
1949 
                           default : ;
1950 
                         endcase
1951 
                       end
1952 
                    1: begin // EX
1953 
                       end
1954 
                    2: begin // MA
1955 
                         ID_INCPC = 1'b1;
1956 
                         ID_IF_ISSUE = 1'b1;
1957 
                         DISPATCH = 1'b1;
1958 
                         MASKINT_NEXT = 1'b1;
1959 
                       end
1960 
                    default: ;
1961 
                  endcase
1962 
                end
1963 
        //--------------------
1964 
        // LDS Rm, MACH (4m0A)
1965 
        // LDS Rm, MACL (4m1A)
1966 
        // LDS Rm, PR   (4m2A)
1967 
        //--------------------
1968 
              6'b??1010 : // 4xxA
1969 
                begin
1970 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rm
1971 
                  EX_RDREG_X = 1'b1;
1972 
                  EX_ALUFUNC = `ALU_THRUX;
1973 
                  casex (INSTR_STATE[5:4])
1974 
                    2'b00   : {EX_MACSEL1, EX_WRMACH, MAC_STALL_SENSE} = 4'b0111; // from ZBUS
1975 
                    2'b01   : {EX_MACSEL2, EX_WRMACL, MAC_STALL_SENSE} = 4'b0111; // from ZBUS
1976 
                    2'b1?   : EX_WRPR_Z = 1'b1; // don't care INSTR_STATE[7:6],[4]
1977 
                    default : ;
1978 
                  endcase
1979 
                  ID_INCPC = 1'b1;
1980 
                  ID_IF_ISSUE = 1'b1;
1981 
                  DISPATCH = 1'b1;
1982 
                end
1983 
        //------------------------
1984 
        // JMP/JSR @Rm (4m2B/4m0B)
1985 
        //------------------------
1986 
              6'b?01011 : // 4x0B, 4x2B (don't care INSTR_STATE[7:6])
1987 
                case (INSTR_SEQ)
1988 
                  0: begin
1989 
                       EX_RDREG_X = 1'b1;
1990 
                       EX_REGNUM_X = INSTR_STATE[11:8]; // Rm
1991 
                       EX_ALUFUNC = `ALU_THRUX;
1992 
                       EX_WRPC_Z = 1'b1;
1993 
                       if (INSTR_STATE[5] == 1'b0) EX_WRPR_PC = 1'b1; // JSR operation
1994 
                       ID_INCPC = 1'b1;
1995 
                     end
1996 
                  1: begin
1997 
                       ID_IF_ISSUE = 1'b1;
1998 
                       ID_IFADSEL = 1'b1;
1999 
                       ID_IF_JP = 1'b1;
2000 
                       DISPATCH = 1'b1;
2001 
                       DELAY_JUMP = 1'b1;
2002 
                     end
2003 
                  default : ;
2004 
                endcase
2005 
        //-----------------
2006 
        // TAS.B @Rn (4n1B)
2007 
        //-----------------
2008 
              6'b011011 : // 4x1B (don't care INSTR_STATE[7:6])
2009 
                case (INSTR_SEQ)
2010 
                  0: begin //ID
2011 
                       EX_RDREG_X = 1'b1;
2012 
                       EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
2013 
                       EX_ALUFUNC = `ALU_THRUX;
2014 
                       EX_WRTEMP_Z = 1'b1;
2015 
                       EX_WRMAAD_Z = 1'b1;
2016 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2017 
                       EX_MA_SZ = 2'b00;
2018 
                       EX_KEEP_CYC = 1'b1;
2019 
                       WB_RDMADR_W = 1'b1;
2020 
                     end
2021 
                  1: begin //EX ID
2022 
                     end
2023 
                  2: begin //MA -- ID
2024 
                       EX_FWD_W2X = 1'b1;
2025 
                       EX_ALUFUNC = `ALU_TAS;
2026 
                       EX_T_TSTSET = 1'b1;
2027 
                       EX_WRMAAD_TEMP = 1'b1;
2028 
                       // WRMADW = ZBUS (default path)
2029 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2030 
                       EX_MA_SZ = 2'b00;
2031 
                     end
2032 
                  3: begin //WB -- EX  ID
2033 
                       ID_INCPC = 1'b1;
2034 
                       ID_IF_ISSUE = 1'b1;
2035 
                       DISPATCH = 1'b1;
2036 
                     end
2037 
                  default : ;
2038 
                endcase
2039 
        //-------------------
2040 
        // LDC Rm, SR  (4m0E)
2041 
        // LDC Rm, GBR (4m1E)
2042 
        // LDC Rm, VBR (4m2E)
2043 
        //-------------------
2044 
              6'b??1110 : // 4xxE
2045 
                begin
2046 
                  EX_REGNUM_X = INSTR_STATE[11:8]; // Rm
2047 
                  EX_RDREG_X = 1'b1;
2048 
                  EX_ALUFUNC = `ALU_THRUX;
2049 
                  casex (INSTR_STATE[5:4])
2050 
                    2'b00   : EX_WRSR_Z = 1'b1;
2051 
                    2'b01   : EX_WRGBR_Z = 1'b1;
2052 
                    2'b1?   : EX_WRVBR_Z = 1'b1;
2053 
                    default : ;
2054 
                  endcase
2055 
                  ID_INCPC = 1'b1;
2056 
                  ID_IF_ISSUE = 1'b1;
2057 
                  DISPATCH = 1'b1;
2058 
                  MASKINT_NEXT = 1'b1;
2059 
                end
2060 
        //------------------------
2061 
        // MAC.W @Rm+, @Rn+ (4nmF)
2062 
        //------------------------
2063 
              6'b??1111 : // 4xxF
2064 
                case (INSTR_SEQ)
2065 
                  0: begin
2066 
                       EX_RDREG_X = 1'b1;
2067 
                       EX_REGNUM_X = INSTR_STATE[11:8]; //@Rn+
2068 
                       EX_ALUFUNC = `ALU_INCX2;
2069 
                       EX_WRREG_Z = 1'b1;
2070 
                       EX_REGNUM_Z = INSTR_STATE[11:8]; //@Rn+
2071 
                       EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
2072 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2073 
                       EX_MA_SZ = 2'b01;
2074 
                       WB_RDMADR_W = 1'b1;
2075 
                       WB_MACSEL1 = 2'b10; // WBUS -> MACIN1
2076 
                       WB_MULCOM1 = 1'b1;
2077 
                     end
2078 
                  1: begin
2079 
                       WB_MAC_BUSY = 1'b1;
2080 
                       MAC_S_LATCH = 1'b1;
2081 
                       EX_RDREG_X = 1'b1;
2082 
                       EX_REGNUM_X = INSTR_STATE[7:4]; //@Rm+
2083 
                       EX_ALUFUNC = `ALU_INCX2;
2084 
                       EX_WRREG_Z = 1'b1;
2085 
                       EX_REGNUM_Z = INSTR_STATE[7:4]; //@Rm+
2086 
                       EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
2087 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2088 
                       EX_MA_SZ = 2'b01;
2089 
                       WB_RDMADR_W = 1'b1;
2090 
                       WB_MACSEL2 = 2'b10; // WBUS -> MACIN2
2091 
                       WB_MULCOM2 = {1'b1, INSTR_STATE[14:12], INSTR_STATE[3:0]};
2092 
                       ID_INCPC = 1'b1;
2093 
                       ID_IF_ISSUE = 1'b1;
2094 
                       DISPATCH = 1'b1;
2095 
                     end
2096 
                  default : ;
2097 
                endcase
2098 
        //---------------
2099 
        // Default = NOP
2100 
        //---------------
2101 
              default :
2102 
                begin
2103 
                  ID_INCPC = 1'b1;
2104 
                  ID_IF_ISSUE = 1'b1;
2105 
                  DISPATCH = 1'b1;
2106 
                end
2107 
            endcase
2108 
        //============================================
2109 
        // Line 5xxx
2110 
        //============================================
2111 
        //-----------------------------
2112 
        // MOV.L @(disp, Rm), Rn (5nmd)
2113 
        //-----------------------------
2114 
          4'b0101 : // 5xxx
2115 
                    begin
2116 
                       EX_RDREG_X = 1'b1;
2117 
                       EX_REGNUM_X = INSTR_STATE[7:4]; //Rm
2118 
                       EX_CONST_ZERO44 = 1'b1;
2119 
                       EX_ALUFUNC = `ALU_ADDCN; //@(disp, Rm)
2120 
                       EX_WRMAAD_Z = 1'b1;
2121 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2122 
                       EX_MA_SZ = 2'b10;
2123 
                       WB_RDMADR_W = 1'b1;
2124 
                       WB_WRREG_W = 1'b1;
2125 
                       WB_REGNUM_W = INSTR_STATE[11:8]; //Rn
2126 
                       ID_INCPC = 1'b1;
2127 
                       ID_IF_ISSUE = 1'b1;
2128 
                       DISPATCH = 1'b1;
2129 
                    end
2130 
        //============================================
2131 
        // Line 6xxx
2132 
        //============================================
2133 
          4'b0110 : // 6xxx
2134 
            casex (INSTR_STATE[3:0])
2135 
              4'b00?? : // 6xx0, 6xx1, 6xx2, 6xx3
2136 
                begin
2137 
        //------------------
2138 
        // MOV Rm, Rn (6nm3)
2139 
        //------------------
2140 
                  if (INSTR_STATE[1:0] == 2'b11) // 6xx3
2141 
                    begin
2142 
                      EX_RDREG_Y = 1'b1;
2143 
                      EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
2144 
                      EX_ALUFUNC = `ALU_THRUY;
2145 
                      EX_WRREG_Z = 1'b1;
2146 
                      EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2147 
                      ID_INCPC = 1'b1;
2148 
                      ID_IF_ISSUE = 1'b1;
2149 
                      DISPATCH = 1'b1;
2150 
                    end
2151 
        //-----------------------------------
2152 
        // MOV.L/W/B @Rm, Rn (6nm2/6nm1/6nm0)
2153 
        //-----------------------------------
2154 
                  else // 6xx0, 6xx1, 6xx2
2155 
                    begin
2156 
                       EX_RDREG_Y = 1'b1;
2157 
                       EX_REGNUM_Y = INSTR_STATE[7:4]; //@Rm
2158 
                       EX_ALUFUNC = `ALU_THRUY;
2159 
                       EX_WRMAAD_Z = 1'b1;
2160 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2161 
                       EX_MA_SZ = INSTR_STATE[1:0];
2162 
                       WB_RDMADR_W = 1'b1;
2163 
                       WB_WRREG_W = 1'b1;
2164 
                       WB_REGNUM_W = INSTR_STATE[11:8]; //Rn
2165 
                       ID_INCPC = 1'b1;
2166 
                       ID_IF_ISSUE = 1'b1;
2167 
                       DISPATCH = 1'b1;
2168 
                    end
2169 
                end
2170 
        //------------------
2171 
        // NOT Rm, Rn (6nm7)
2172 
        //------------------
2173 
              4'b01?? : // 6xx4, 6xx5, 6xx6, 6xx7
2174 
                begin
2175 
                  if (INSTR_STATE[1:0] == 2'b11) // 6xx7
2176 
                    begin
2177 
                      EX_RDREG_Y = 1'b1;
2178 
                      EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
2179 
                      EX_ALUFUNC = `ALU_NOT;
2180 
                      EX_WRREG_Z = 1'b1;
2181 
                      EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2182 
                      ID_INCPC = 1'b1;
2183 
                      ID_IF_ISSUE = 1'b1;
2184 
                      DISPATCH = 1'b1;
2185 
                    end
2186 
        //-----------------------------------
2187 
        // MOV.L/W/B @Rm+, Rn (6nm6/6nm5/6nm4)
2188 
        //-----------------------------------
2189 
                  else // 6xx4, 6xx5, 6xx6
2190 
                    begin
2191 
                       EX_RDREG_X = 1'b1;
2192 
                       EX_REGNUM_X = INSTR_STATE[7:4]; //@Rm
2193 
                       case (INSTR_STATE[1:0])
2194 
                           2'b00   : EX_ALUFUNC = `ALU_INCX;
2195 
                           2'b01   : EX_ALUFUNC = `ALU_INCX2;
2196 
                           2'b10   : EX_ALUFUNC = `ALU_INCX4;
2197 
                           default : EX_ALUFUNC = `ALU_NOP;
2198 
                       endcase
2199 
                       EX_WRREG_Z = 1'b1;
2200 
                       EX_REGNUM_Z = INSTR_STATE[7:4]; // @Rm+
2201 
                       EX_WRMAAD_Z = 1'b0; // MAAD = XBUS
2202 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2203 
                       EX_MA_SZ = INSTR_STATE[1:0];
2204 
                       WB_RDMADR_W = 1'b1;
2205 
                       WB_WRREG_W = 1'b1;
2206 
                       WB_REGNUM_W = INSTR_STATE[11:8]; //Rn
2207 
                       ID_INCPC = 1'b1;
2208 
                       ID_IF_ISSUE = 1'b1;
2209 
                       DISPATCH = 1'b1;
2210 
                    end
2211 
                end
2212 
        //---------------------
2213 
        // SWAP.B Rm, Rn (6nm8)
2214 
        // SWAP.W Rm, Rn (6nm9)
2215 
        //---------------------
2216 
              4'b100? : // 6xx8, 6xx9
2217 
                begin
2218 
                  EX_RDREG_Y = 1'b1;
2219 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
2220 
                  case (INSTR_STATE[0])
2221 
                      1'b0 : EX_ALUFUNC = `ALU_SWAPB;
2222 
                      1'b1 : EX_ALUFUNC = `ALU_SWAPW;
2223 
                      default : ;
2224 
                  endcase
2225 
                  EX_WRREG_Z = 1'b1;
2226 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2227 
                  ID_INCPC = 1'b1;
2228 
                  ID_IF_ISSUE = 1'b1;
2229 
                  DISPATCH = 1'b1;
2230 
                end
2231 
        //---------------------
2232 
        // NEGC Rm, Rn (6nmA)
2233 
        // NEG  Rm, Rn (6nmB)
2234 
        //---------------------
2235 
              4'b101? : // 6xxA, 6xxB
2236 
                begin
2237 
                  EX_RDREG_Y = 1'b1;
2238 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
2239 
                  case (INSTR_STATE[0])
2240 
                      1'b0 : EX_ALUFUNC = `ALU_SUBC;
2241 
                      1'b1 : EX_ALUFUNC = `ALU_SUB;
2242 
                      default : ;
2243 
                  endcase
2244 
                  case (INSTR_STATE[0])
2245 
                      1'b0 : EX_T_CRYSET = 1'b1;
2246 
                      1'b1 : EX_T_CRYSET = 1'b0;
2247 
                      default : ;
2248 
                  endcase
2249 
                  EX_WRREG_Z = 1'b1;
2250 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2251 
                  ID_INCPC = 1'b1;
2252 
                  ID_IF_ISSUE = 1'b1;
2253 
                  DISPATCH = 1'b1;
2254 
                end
2255 
        //---------------------
2256 
        // EXTU.B Rm, Rn (6nmC)
2257 
        // EXTU.W Rm, Rn (6nmD)
2258 
        // EXTS.B Rm, Rn (6nmE)
2259 
        // EXTS.W Rm, Rn (6nmF)
2260 
        //---------------------
2261 
              4'b11?? : // 6xxC, 6xxD, 6xxE, 6xxF
2262 
                begin
2263 
                  EX_RDREG_Y = 1'b1;
2264 
                  EX_REGNUM_Y = INSTR_STATE[7:4]; // Rm
2265 
                  case (INSTR_STATE[1:0])
2266 
                      2'b00 : EX_ALUFUNC = `ALU_EXTUB;
2267 
                      2'b01 : EX_ALUFUNC = `ALU_EXTUW;
2268 
                      2'b10 : EX_ALUFUNC = `ALU_EXTSB;
2269 
                      2'b11 : EX_ALUFUNC = `ALU_EXTSW;
2270 
                      default : ;
2271 
                  endcase
2272 
                  EX_WRREG_Z = 1'b1;
2273 
                  EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2274 
                  ID_INCPC = 1'b1;
2275 
                  ID_IF_ISSUE = 1'b1;
2276 
                  DISPATCH = 1'b1;
2277 
                end
2278 
        //---------------
2279 
        // Default = NOP
2280 
        //---------------
2281 
              default :
2282 
                begin
2283 
                  ID_INCPC = 1'b1;
2284 
                  ID_IF_ISSUE = 1'b1;
2285 
                  DISPATCH = 1'b1;
2286 
                end
2287 
            endcase
2288 
        //============================================
2289 
        // Line 7xxx
2290 
        //============================================
2291 
        //---------------------
2292 
        // ADD #imm8, Rn (7nii)
2293 
        //---------------------
2294 
          4'b0111 : // 7xxx
2295 
            begin
2296 
              EX_RDREG_X = 1'b1;
2297 
              EX_REGNUM_X = INSTR_STATE[11:8]; // Rn
2298 
              EX_CONST_SIGN8 = 1'b1;
2299 
              EX_RDCONST_Y = 1'b1;
2300 
              EX_ALUFUNC = `ALU_ADD;
2301 
              EX_WRREG_Z = 1'b1;
2302 
              EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2303 
              ID_INCPC = 1'b1;
2304 
              ID_IF_ISSUE = 1'b1;
2305 
              DISPATCH = 1'b1;
2306 
            end
2307 
        //============================================
2308 
        // Line 8xxx
2309 
        //============================================
2310 
          4'b1000 : // 8xxx
2311 
            casex (INSTR_STATE[11:8])
2312 
        //-----------------------------
2313 
        // MOV.B R0, @(disp, Rn) (80nd)
2314 
        // MOV.W R0, @(disp, Rn) (81nd)
2315 
        //-----------------------------
2316 
              4'b000? : // 80xx, 81xx
2317 
                begin
2318 
                  EX_RDREG_X = 1'b1;
2319 
                  EX_REGNUM_X = INSTR_STATE[7:4]; //Rn
2320 
                  if (INSTR_STATE[8])
2321 
                      EX_CONST_ZERO42 = 1'b1; //.W
2322 
                  else
2323 
                      EX_CONST_ZERO4  = 1'b1; //.B
2324 
                  EX_ALUFUNC = `ALU_ADDCN; //@(disp, Rn)
2325 
                  EX_WRMAAD_Z = 1'b1;
2326 
                  EX_RDREG_Y = 1'b1;
2327 
                  EX_REGNUM_Y = 4'h0;  //R0
2328 
                  EX_WRMADW_Y = 1'b1;
2329 
                  {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2330 
                  EX_MA_SZ = INSTR_STATE[9:8];
2331 
                  ID_INCPC = 1'b1;
2332 
                  ID_IF_ISSUE = 1'b1;
2333 
                  DISPATCH = 1'b1;
2334 
                end
2335 
        //-----------------------------
2336 
        // MOV.B @(disp, Rm), R0 (84md)
2337 
        // MOV.W @(disp, Rm), R0 (85md)
2338 
        //-----------------------------
2339 
              4'b010? : // 84xx, 85xx
2340 
                begin
2341 
                  EX_RDREG_X = 1'b1;
2342 
                  EX_REGNUM_X = INSTR_STATE[7:4]; //Rm
2343 
                  if (INSTR_STATE[8])
2344 
                      EX_CONST_ZERO42 = 1'b1; //.W
2345 
                  else
2346 
                      EX_CONST_ZERO4  = 1'b1; //.B
2347 
                  EX_ALUFUNC = `ALU_ADDCN; //@(disp, Rm)
2348 
                  EX_WRMAAD_Z = 1'b1;
2349 
                  {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2350 
                  EX_MA_SZ = INSTR_STATE[9:8];
2351 
                  WB_RDMADR_W = 1'b1;
2352 
                  WB_WRREG_W = 1'b1;
2353 
                  WB_REGNUM_W = 4'h0; //R0
2354 
                  ID_INCPC = 1'b1;
2355 
                  ID_IF_ISSUE = 1'b1;
2356 
                  DISPATCH = 1'b1;
2357 
                end
2358 
        //------------------------
2359 
        // CMP/EQ #imm8, R0 (88ii)
2360 
        //------------------------
2361 
              4'b1000 : // 88xx
2362 
                begin
2363 
                  EX_RDREG_X = 1'b1;
2364 
                  EX_REGNUM_X = 4'b0000; // R0
2365 
                  EX_CONST_SIGN8 = 1'b1;
2366 
                  EX_RDCONST_Y = 1'b1;
2367 
                  EX_CMPCOM = 3'b000; //equal command
2368 
                  EX_T_CMPSET = 1'b1;
2369 
                  ID_INCPC = 1'b1;
2370 
                  ID_IF_ISSUE = 1'b1;
2371 
                  DISPATCH = 1'b1;
2372 
                end
2373 
        //------------------------
2374 
        // BT/BF disp8 (89dd/8Bdd)
2375 
        //------------------------
2376 
              4'b10?1 : // 89xx, 8Bxx
2377 
                case (INSTR_SEQ)
2378 
                  0: begin
2379 
                       ID_INCPC = 1'b1;
2380 
                       ID_IF_ISSUE = 1'b1;
2381 
                       EX_RDPC_X = 1'b1;
2382 
                       EX_CONST_SIGN82 = 1'b1;
2383 
                       EX_RDCONST_Y = 1'b1;
2384 
                       EX_ALUFUNC = `ALU_ADD;
2385 
                       if (INSTR_STATE[9] == T_BCC) // if not taken (same as NOP)
2386 
                         DISPATCH = 1'b1;
2387 
                       else // if taken
2388 
                         EX_WRPC_Z = 1'b1;
2389 
                     end
2390 
                  1: begin
2391 
                       ID_IF_ISSUE = 1'b1;
2392 
                       ID_IFADSEL = 1'b1;
2393 
                       ID_IF_JP = 1'b1;
2394 
                     end
2395 
                  2: begin
2396 
                       ID_INCPC = 1'b1;
2397 
                       ID_IF_ISSUE = 1'b1;
2398 
                       DISPATCH = 1'b1;
2399 
                     end
2400 
                  default: ;
2401 
                endcase
2402 
        //------------------
2403 
        // BT/S disp8 (8Ddd)
2404 
        // BF/S disp8 (8Fdd)
2405 
        //------------------
2406 
              4'b11?1 : // 8Dxx, 8Fxx
2407 
                case (INSTR_SEQ)
2408 
                  0: begin
2409 
                       ID_INCPC = 1'b1;
2410 
                       EX_RDPC_X = 1'b1;
2411 
                       EX_CONST_SIGN82 = 1'b1;
2412 
                       EX_RDCONST_Y = 1'b1;
2413 
                       EX_ALUFUNC = `ALU_ADD;
2414 
                       if (INSTR_STATE[9] == T_BCC) // if not taken (same as NOP)
2415 
                         begin
2416 
                           ID_IF_ISSUE = 1'b1;
2417 
                           DISPATCH = 1'b1;
2418 
                         end
2419 
                       else // if taken
2420 
                         EX_WRPC_Z = 1'b1;
2421 
                     end
2422 
                  1: begin
2423 
                       ID_IF_ISSUE = 1'b1;
2424 
                       ID_IFADSEL = 1'b1;
2425 
                       ID_IF_JP = 1'b1;
2426 
                       DISPATCH = 1'b1;
2427 
                       DELAY_JUMP = 1'b1;
2428 
                     end
2429 
                  default : ;
2430 
                endcase
2431 
        //---------------
2432 
        // Default = NOP
2433 
        //---------------
2434 
              default :
2435 
                begin
2436 
                  ID_INCPC = 1'b1;
2437 
                  ID_IF_ISSUE = 1'b1;
2438 
                  DISPATCH = 1'b1;
2439 
                end
2440 
            endcase
2441 
        //============================================
2442 
        // Line 9xxx
2443 
        //============================================
2444 
        //------------------------------
2445 
        // MOV.W @(disp8, PC), Rn (9ndd)
2446 
        //------------------------------
2447 
          4'b1001 : // 9xxx
2448 
            begin
2449 
              EX_RDPC_X = 1;
2450 
              EX_CONST_ZERO82 = 1'b1;
2451 
              EX_RDCONST_Y = 1'b1;
2452 
              EX_ALUFUNC = `ALU_ADD;
2453 
              EX_WRMAAD_Z = 1'b1;
2454 
              {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2455 
              EX_MA_SZ = 2'b01;
2456 
              WB_RDMADR_W = 1'b1;
2457 
              WB_WRREG_W = 1'b1;
2458 
              WB_REGNUM_W = INSTR_STATE[11:8]; // Rn
2459 
              ID_INCPC = 1'b1;
2460 
              ID_IF_ISSUE = 1'b1;
2461 
              DISPATCH = 1'b1;
2462 
            end
2463 
        //============================================
2464 
        // Line Axxx / Bxxx
2465 
        //============================================
2466 
        //---------------------------
2467 
        // BRA/BSR disp12 (Addd/Bddd)
2468 
        //---------------------------
2469 
          4'b101? : // Axxx, Bxxx
2470 
            case (INSTR_SEQ)
2471 
              0: begin
2472 
                   EX_RDPC_X = 1'b1;
2473 
                   EX_CONST_SIGN122 = 1'b1;
2474 
                   EX_RDCONST_Y = 1'b1;
2475 
                   EX_ALUFUNC = `ALU_ADD;
2476 
                   EX_WRPC_Z = 1'b1;
2477 
                   if (INSTR_STATE[12]) EX_WRPR_PC = 1'b1; // BSR operation
2478 
                   ID_INCPC = 1'b1;
2479 
                 end
2480 
              1: begin
2481 
                   ID_IF_ISSUE = 1'b1;
2482 
                   ID_IFADSEL = 1'b1;
2483 
                   ID_IF_JP = 1'b1;
2484 
                   DISPATCH = 1'b1;
2485 
                   DELAY_JUMP = 1'b1;
2486 
                 end
2487 
              default : ;
2488 
            endcase
2489 
        //============================================
2490 
        // Line Cxxx
2491 
        //============================================
2492 
          4'b1100 : // Cxxx
2493 
            casex (INSTR_STATE[11:8])
2494 
        //------------------------------
2495 
        // MOV.B R0, @(disp, GBR) (C0dd)
2496 
        // MOV.W R0, @(disp, GBR) (C1dd)
2497 
        // MOV.L R0, @(disp, GBR) (C2dd)
2498 
        //------------------------------
2499 
              4'b00??: // C0xx, C1xx, C2xx, C3xx
2500 
                begin
2501 
                  if (~INSTR_STATE[9] | ~INSTR_STATE[8])
2502 
                    begin // C0xx, C1xx, C2xx
2503 
                      EX_RDGBR_X = 1'b1;
2504 
                      case (INSTR_STATE[9:8])
2505 
                          2'b00  : EX_CONST_ZERO8  = 1'b1;
2506 
                          2'b01  : EX_CONST_ZERO82 = 1'b1;
2507 
                          default: EX_CONST_ZERO84 = 1'b1;
2508 
                      endcase
2509 
                      EX_ALUFUNC = `ALU_ADDCN; //@(disp, GBR)
2510 
                      EX_WRMAAD_Z = 1'b1;
2511 
                      EX_RDREG_Y = 1'b1;
2512 
                      EX_REGNUM_Y = 4'h0;  //R0
2513 
                      EX_WRMADW_Y = 1'b1;
2514 
                      {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2515 
                      EX_MA_SZ = INSTR_STATE[9:8];
2516 
                      ID_INCPC = 1'b1;
2517 
                      ID_IF_ISSUE = 1'b1;
2518 
                      DISPATCH = 1'b1;
2519 
                    end
2520 
        //-----------
2521 
        // TRAPA #imm
2522 
        //-----------
2523 
                  else
2524 
                    begin // C3xx
2525 
                      case (INSTR_SEQ)
2526 
 
2527 
                              EX_RDREG_X = 1'b1;
2528 
                              EX_REGNUM_X = 4'hF;
2529 
                              EX_ALUFUNC = `ALU_DECX4;
2530 
                              EX_WRREG_Z = 1'b1;
2531 
                              EX_REGNUM_Z = 4'hF;
2532 
                              EX_WRMAAD_Z = 1'b1;
2533 
                              EX_RDSR_Y = 1'b1;
2534 
                              EX_WRMADW_Y = 1'b1;
2535 
                              {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2536 
                              EX_MA_SZ = 2'b10;
2537 
                            end
2538 
                        1 : begin
2539 
                              EX_RDREG_X = 1'b1;
2540 
                              EX_REGNUM_X = 4'hF;
2541 
                              EX_ALUFUNC = `ALU_DECX4;
2542 
                              EX_WRREG_Z = 1'b1;
2543 
                              EX_REGNUM_Z = 4'hF;
2544 
                              EX_WRMAAD_Z = 1'b1;
2545 
                              EX_RDPC_Y = 1'b1;
2546 
                              EX_WRMADW_Y = 1'b1;
2547 
                              {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2548 
                              EX_MA_SZ = 2'b10;
2549 
                            end
2550 
                        2 : begin
2551 
                              EX_RDCONST_X = 1'b1;
2552 
                              EX_CONST_ZERO84 = 1'b1;
2553 
                              EX_RDVBR_Y = 1'b1;
2554 
                              EX_ALUFUNC = `ALU_ADD;
2555 
                              EX_WRMAAD_Z = 1'b1;
2556 
                              {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2557 
                              EX_MA_SZ = 2'b10;
2558 
                              WB_RDMADR_W = 1'b1;
2559 
                            end
2560 
                        3 : begin
2561 
                            end
2562 
                        4 : begin
2563 
                              EX_ALUFUNC = `ALU_THRUW;
2564 
                              EX_WRPC_Z = 1'b1;
2565 
                            end
2566 
                        5 : begin
2567 
                              ID_IFADSEL = 1'b1;
2568 
                              ID_IF_ISSUE = 1'b1;
2569 
                              ID_IF_JP = 1'b1;
2570 
                            end
2571 
                        6 : begin
2572 
                              ID_INCPC = 1'b1;
2573 
                              ID_IF_ISSUE = 1'b1;
2574 
                              DISPATCH = 1'b1;
2575 
                            end
2576 
                        default : ;
2577 
                      endcase
2578 
                    end
2579 
                end
2580 
        //------------------------------
2581 
        // MOV.B @(disp, GBR), R0 (C4dd)
2582 
        // MOV.W @(disp, GBR), R0 (C5dd)
2583 
        // MOV.L @(disp, GBR), R0 (C6dd)
2584 
        //------------------------------
2585 
              4'b01??: // C4xx, C5xx, C6xx, C7xx
2586 
                begin
2587 
                  if (~INSTR_STATE[9] | ~INSTR_STATE[8])
2588 
                    begin // C4xx, C5xx, C6xx
2589 
                      EX_RDGBR_X = 1'b1;
2590 
                      case (INSTR_STATE[9:8])
2591 
                          2'b00  : EX_CONST_ZERO8  = 1'b1;
2592 
                          2'b01  : EX_CONST_ZERO82 = 1'b1;
2593 
                          default: EX_CONST_ZERO84 = 1'b1;
2594 
                      endcase
2595 
                      EX_ALUFUNC = `ALU_ADDCN; //@(disp, GBR)
2596 
                      EX_WRMAAD_Z = 1'b1;
2597 
                      {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2598 
                      EX_MA_SZ = INSTR_STATE[9:8];
2599 
                      WB_RDMADR_W = 1'b1;
2600 
                      WB_WRREG_W = 1'b1;
2601 
                      WB_REGNUM_W = 4'h0; //R0
2602 
                      ID_INCPC = 1'b1;
2603 
                      ID_IF_ISSUE = 1'b1;
2604 
                      DISPATCH = 1'b1;
2605 
                    end
2606 
        //---------------------------
2607 
        // MOVA @(disp,PC), R0 (C7dd)
2608 
        //---------------------------
2609 
                  else
2610 
                    begin // C7xx
2611 
                      EX_RDPC_X = 1'b1;
2612 
                      EX_CONST_ZERO84 = 1'b1;
2613 
                      EX_RDCONST_Y = 1'b1;
2614 
                      EX_ALUFUNC = `ALU_ADDXFC;
2615 
                      EX_WRREG_Z = 1'b1;
2616 
                      EX_REGNUM_Z = 4'h0; // R0
2617 
                      ID_INCPC = 1'b1;
2618 
                      ID_IF_ISSUE = 1'b1;
2619 
                      DISPATCH = 1'b1;
2620 
                    end
2621 
                end
2622 
        //---------------------
2623 
        // TST #imm8, R0 (C8ii)
2624 
        // AND #imm8, R0 (C9ii)
2625 
        // XOR #imm8, R0 (CAii)
2626 
        // OR  #imm8, R0 (CBii)
2627 
        //---------------------
2628 
              4'b10??: // C8xx, C9xx, CAxx, CBxx
2629 
                begin
2630 
                  EX_RDREG_X = 1'b1;
2631 
                  EX_REGNUM_X = 4'b0000; // R0
2632 
                  EX_CONST_ZERO8 = 1'b1;
2633 
                  EX_RDCONST_Y = 1'b1;
2634 
                  EX_REGNUM_Z = 4'b0000; // R0
2635 
                  case (INSTR_STATE[9:8])
2636 
                      2'b00 :  {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_AND, 1'b0, 1'b1};
2637 
                      2'b01 :  {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_AND, 1'b1, 1'b0};
2638 
                      2'b10 :  {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_XOR, 1'b1, 1'b0};
2639 
                      2'b11 :  {EX_ALUFUNC, EX_WRREG_Z, EX_T_TSTSET} = {`ALU_OR , 1'b1, 1'b0};
2640 
                      default : ;
2641 
                  endcase
2642 
                  ID_INCPC = 1'b1;
2643 
                  ID_IF_ISSUE = 1'b1;
2644 
                  DISPATCH = 1'b1;
2645 
                end
2646 
        //------------------------------
2647 
        // TST.B #imm8, @(R0,GBR) (CCii)
2648 
        // AND.B #imm8, @(R0,GBR) (CDii)
2649 
        // XOR.B #imm8, @(R0,GBR) (CEii)
2650 
        // OR.B  #imm8, @(R0,GBR) (CFii)
2651 
        //------------------------------
2652 
              4'b11??: // CCxx, CDxx, CExx, CFxx
2653 
                case (INSTR_SEQ)
2654 
                  0: begin
2655 
                       EX_RDGBR_X = 1'b1;     // GBR
2656 
                       EX_RDREG_Y = 1'b1;
2657 
                       EX_REGNUM_Y = 4'h0; // R0
2658 
                       EX_ALUFUNC = `ALU_ADD;
2659 
                       EX_WRMAAD_Z = 1'b1;
2660 
                       EX_WRTEMP_Z = 1'b1;
2661 
                       {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2662 
                       EX_MA_SZ = 2'b00;
2663 
                       WB_RDMADR_W = 1'b1;
2664 
                     end
2665 
                  1: begin
2666 
                     end
2667 
                  2: begin
2668 
                       EX_WRMAAD_TEMP = 1'b1;
2669 
                       EX_FWD_W2X = 1'b1;
2670 
                       EX_CONST_ZERO8 = 1'b1;
2671 
                       EX_RDCONST_Y = 1'b1;
2672 
                       case (INSTR_STATE[9:8])
2673 
                         2'b00 :  {EX_ALUFUNC, EX_MA_ISSUE, EX_T_TSTSET} = {`ALU_AND, 1'b0, 1'b1};
2674 
                         2'b01 :  {EX_ALUFUNC, EX_MA_ISSUE, EX_T_TSTSET} = {`ALU_AND, 1'b1, 1'b0};
2675 
                         2'b10 :  {EX_ALUFUNC, EX_MA_ISSUE, EX_T_TSTSET} = {`ALU_XOR, 1'b1, 1'b0};
2676 
                         2'b11 :  {EX_ALUFUNC, EX_MA_ISSUE, EX_T_TSTSET} = {`ALU_OR , 1'b1, 1'b0};
2677 
                         default : ;
2678 
                      endcase
2679 
                      EX_WRMAAD_TEMP = 1'b1;
2680 
                      EX_MA_WR = 1'b1;
2681 
                      EX_MA_SZ = 2'b00;
2682 
                      ID_INCPC = 1'b1;
2683 
                      ID_IF_ISSUE = 1'b1;
2684 
                      DISPATCH = 1'b1;
2685 
                     end
2686 
                  default : ;
2687 
                endcase
2688 
        //---------------
2689 
        // Default = NOP
2690 
        //---------------
2691 
              default :
2692 
                begin
2693 
                  ID_INCPC = 1'b1;
2694 
                  ID_IF_ISSUE = 1'b1;
2695 
                  DISPATCH = 1'b1;
2696 
                end
2697 
            endcase
2698 
        //============================================
2699 
        // Line Dxxx
2700 
        //============================================
2701 
        //------------------------------
2702 
        // MOV.L @(disp8, PC), Rn (Dndd)
2703 
        //------------------------------
2704 
          4'b1101 : // Dxxx
2705 
            begin
2706 
              EX_RDPC_X = 1'b1;
2707 
              EX_CONST_ZERO84 = 1'b1;
2708 
              EX_RDCONST_Y = 1'b1;
2709 
              EX_ALUFUNC = `ALU_ADDXFC;
2710 
              EX_WRMAAD_Z = 1'b1;
2711 
              {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2712 
              EX_MA_SZ = 2'b10;
2713 
              WB_RDMADR_W = 1'b1;
2714 
              WB_WRREG_W = 1'b1;
2715 
              WB_REGNUM_W = INSTR_STATE[11:8]; // Rn
2716 
              ID_INCPC = 1'b1;
2717 
              ID_IF_ISSUE = 1'b1;
2718 
              DISPATCH = 1'b1;
2719 
            end
2720 
        //============================================
2721 
        // Line Exxx
2722 
        //============================================
2723 
        //---------------------
2724 
        // MOV #imm8, Rn (Enii)
2725 
        //---------------------
2726 
          4'b1110 : // Exxx
2727 
            begin
2728 
              EX_CONST_SIGN8 = 1'b1;
2729 
              EX_RDCONST_Y = 1'b1;
2730 
              EX_ALUFUNC = `ALU_THRUY;
2731 
              EX_WRREG_Z = 1'b1;
2732 
              EX_REGNUM_Z = INSTR_STATE[11:8]; // Rn
2733 
              ID_INCPC = 1'b1;
2734 
              ID_IF_ISSUE = 1'b1;
2735 
              DISPATCH = 1'b1;
2736 
            end
2737 
        //============================================
2738 
        // Line Fxxx
2739 
        //============================================
2740 
          default : //Fxxx or else
2741 
            casex (INSTR_STATE[11:8])
2742 
        //----------------------
2743 
        // Power on Reset (F700)
2744 
        // Manual   Reset (F602)
2745 
        //----------------------
2746 
              4'b011? : // F6xx, F7xx
2747 
                begin
2748 
                  case (INSTR_SEQ)
2749 
                    1: begin // ID
2750 
                         EVENT_ACK_0 = 1'b1;
2751 
                         EX_ALUFUNC = `ALU_NOP;
2752 
                         RST_SR = 1'b1;
2753 
                       end
2754 
                    2: begin // EX ID
2755 
                         EX_CONST_ZERO84 = 1'b1;
2756 
                         EX_RDCONST_Y = 1'b1;
2757 
                         EX_ALUFUNC = `ALU_THRUY;
2758 
                         EX_WRMAAD_Z = 1'b1; // MAAD=00000000 or 00000008
2759 
                         EX_WRTEMP_Z = 1'b1;
2760 
                         EX_MA_ISSUE = 1'b1;
2761 
                         EX_MA_WR = 1'b0;
2762 
                         EX_MA_SZ = 2'b10; // read long
2763 
                         WB_RDMADR_W = 1'b1;
2764 
                       end
2765 
                    3: begin //    EX ID
2766 
                         EX_RDTEMP_X = 1'b1;
2767 
                         EX_ALUFUNC = `ALU_INCX4; // Z = TEMP + 4
2768 
                         EX_WRMAAD_Z = 1'b1; // MAAD=00000004 or 0000000C
2769 
                         EX_MA_ISSUE = 1'b1;
2770 
                         EX_MA_WR = 1'b0;
2771 
                         EX_MA_SZ = 2'b10; // read long
2772 
                         WB_RDMADR_W = 1'b1;
2773 
                         WB_WRREG_W = 1'b1;
2774 
                         WB_REGNUM_W = 4'hf;
2775 
                       end
2776 
                    4: begin //    MA EX ID
2777 
                         EX_ALUFUNC = `ALU_THRUW;
2778 
                         EX_WRPC_Z = 1'b1;
2779 
                       end
2780 
                    5: begin //    WB MA EX ID
2781 
                         EX_WRVBR_Z = 1'b1;  // clear VBR = 00000000
2782 
                         ID_IFADSEL = 1'b1;
2783 
                         ID_IF_ISSUE = 1'b1;
2784 
                         ID_IF_JP = 1'b1;
2785 
                      end
2786 
                    6: begin //       WB    EX
2787 
                         ID_INCPC = 1'b1;
2788 
                         ID_IF_ISSUE = 1'b1;
2789 
                         DISPATCH = 1'b1;
2790 
                       end
2791 
                    default : ;
2792 
                  endcase
2793 
                end
2794 
        //-------------------------
2795 
        // DMA Address Error (F30A)
2796 
        // CPU Address Error (F209)
2797 
        // NMI Interrupt     (F10B)
2798 
        // IRQ Interrupt     (F0xx)
2799 
        //-------------------------
2800 
              4'b00??: // F0xx, F1xx, F2xx, F3xx
2801 
                begin
2802 
                  case (INSTR_SEQ)
2803 
 
2804 
                          EVENT_ACK_0 = 1'b1;
2805 
                          ILEVEL_CAP = 1'b1;
2806 
                          EX_RDPC_X = 1'b1;
2807 
                          EX_ALUFUNC = `ALU_DECX2;
2808 
                          EX_WRPC_Z = 1'b1;
2809 
                        end
2810 
                    1 : begin
2811 
                          EX_RDREG_X = 1'b1;
2812 
                          EX_REGNUM_X = 4'hF;
2813 
                          EX_ALUFUNC = `ALU_ADDXFC; // prevent repeating address error
2814 
                          EX_WRTEMP_Z = 1'b1;
2815 
                        end
2816 
                    2 : begin
2817 
                          EX_RDTEMP_X = 1'b1;
2818 
                          EX_ALUFUNC = `ALU_DECX4;
2819 
                          EX_WRTEMP_Z = 1'b1;
2820 
                          EX_WRMAAD_Z = 1'b1;
2821 
                          EX_RDSR_Y = 1'b1;
2822 
                          EX_WRMADW_Y = 1'b1;
2823 
                          {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2824 
                          EX_MA_SZ = 2'b10;
2825 
                        end
2826 
                    3 : begin
2827 
                          EX_RDTEMP_X = 1'b1;
2828 
                          EX_ALUFUNC = `ALU_DECX4;
2829 
                          EX_WRTEMP_Z = 1'b1;
2830 
                          EX_WRMAAD_Z = 1'b1;
2831 
                          EX_RDPC_Y = 1'b1;
2832 
                          EX_WRMADW_Y = 1'b1;
2833 
                          {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2834 
                          EX_MA_SZ = 2'b10;
2835 
                        end
2836 
                    4 : begin
2837 
                          EX_RDVBR_X = 1'b1;
2838 
                          EX_RDCONST_Y = 1'b1;
2839 
                          EX_CONST_ZERO84 = 1'b1;
2840 
                          EX_ALUFUNC = `ALU_ADD;
2841 
                          EX_WRMAAD_Z = 1'b1;
2842 
                          {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2843 
                          EX_MA_SZ = 2'b10;
2844 
                          WB_RDMADR_W = 1'b1;
2845 
                        end
2846 
                    5 : begin
2847 
                          if (~INSTR_STATE[9]) WR_IBIT = 1'b1; // if NMI or IRQ
2848 
                          EX_RDREG_X = 1'b1;
2849 
                          EX_REGNUM_X = 4'hF;
2850 
                          EX_ALUFUNC = `ALU_DECX4;
2851 
                          EX_WRREG_Z = 1'b1;
2852 
                          EX_REGNUM_Z = 4'hF;
2853 
                        end
2854 
                    6 : begin
2855 
                          EX_ALUFUNC = `ALU_THRUW;
2856 
                          EX_WRPC_Z = 1'b1;
2857 
                        end
2858 
                    7 : begin
2859 
                          EX_RDREG_X = 1'b1;
2860 
                          EX_REGNUM_X = 4'hF;
2861 
                          EX_ALUFUNC = `ALU_DECX4;
2862 
                          EX_WRREG_Z = 1'b1;
2863 
                          EX_REGNUM_Z = 4'hF;
2864 
                          ID_IFADSEL = 1'b1;
2865 
                          ID_IF_ISSUE = 1'b1;
2866 
                          ID_IF_JP = 1'b1;
2867 
                        end
2868 
                    8 : begin
2869 
                          ID_INCPC = 1'b1;
2870 
                          ID_IF_ISSUE = 1'b1;
2871 
                          DISPATCH = 1'b1;
2872 
                        end
2873 
                    default : ;
2874 
                  endcase
2875 
                end
2876 
        //-----------------------------------
2877 
        // General Illegal Instruction (FFxx)
2878 
        // Slot    Illegal Instruction (FExx)
2879 
        //-----------------------------------
2880 
              default : // FFxx, FExx,  etc
2881 
                begin
2882 
                  case (INSTR_SEQ)
2883 
 
2884 
                          EX_RDPC_X = 1'b1;
2885 
                          if (INSTR_STATE[8])
2886 
                              EX_ALUFUNC = `ALU_DECX2; // GNRL_ILGL
2887 
                          else
2888 
                              EX_ALUFUNC = `ALU_THRUX; // SLOT_ILGL
2889 
                          EX_WRPC_Z = 1'b1;
2890 
                        end
2891 
                    1 : begin
2892 
                          EX_RDREG_X = 1'b1;
2893 
                          EX_REGNUM_X = 4'hF;
2894 
                          EX_ALUFUNC = `ALU_DECX4;
2895 
                          EX_WRREG_Z = 1'b1;
2896 
                          EX_REGNUM_Z = 4'hF;
2897 
                          EX_WRMAAD_Z = 1'b1;
2898 
                          EX_RDSR_Y = 1'b1;
2899 
                          EX_WRMADW_Y = 1'b1;
2900 
                          {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2901 
                          EX_MA_SZ = 2'b10;
2902 
                        end
2903 
                    2 : begin
2904 
                          EX_RDREG_X = 1'b1;
2905 
                          EX_REGNUM_X = 4'hF;
2906 
                          EX_ALUFUNC = `ALU_DECX4;
2907 
                          EX_WRREG_Z = 1'b1;
2908 
                          EX_REGNUM_Z = 4'hF;
2909 
                          EX_WRMAAD_Z = 1'b1;
2910 
                          EX_RDPC_Y = 1'b1;
2911 
                          EX_WRMADW_Y = 1'b1;
2912 
                          {EX_MA_ISSUE,EX_MA_WR} =  2'b11;
2913 
                          EX_MA_SZ = 2'b10;
2914 
                        end
2915 
                    3 : begin
2916 
                          EX_RDCONST_X = 1'b1;
2917 
                          EX_CONST_ZERO84 = 1'b1;
2918 
                          EX_RDVBR_Y = 1'b1;
2919 
                          EX_ALUFUNC = `ALU_ADD;
2920 
                          EX_WRMAAD_Z = 1'b1;
2921 
                          {EX_MA_ISSUE,EX_MA_WR} =  2'b10;
2922 
                          EX_MA_SZ = 2'b10;
2923 
                          WB_RDMADR_W = 1'b1;
2924 
                        end
2925 
                    4 : begin
2926 
                        end
2927 
                    5 : begin
2928 
                          EX_ALUFUNC = `ALU_THRUW;
2929 
                          EX_WRPC_Z = 1'b1;
2930 
                        end
2931 
                    6 : begin
2932 
                          ID_IFADSEL = 1'b1;
2933 
                          ID_IF_ISSUE = 1'b1;
2934 
                          ID_IF_JP = 1'b1;
2935 
                        end
2936 
                    7 : begin
2937 
                          ID_INCPC = 1'b1;
2938 
                          ID_IF_ISSUE = 1'b1;
2939 
                          DISPATCH = 1'b1;
2940 
                        end
2941 
                    default : ;
2942 
                  endcase
2943 
                end
2944 
            endcase
2945 
        endcase
2946 
    end
2947 
 
2948 
//======================================================
2949 
  endmodule
2950 
//======================================================

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