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[/] [Aquarius/] [trunk/] [verilog/] [test.v] - Blame information for rev 2

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//======================================================
// Aquarius Project
//    SuperH-2 ISA Compatible RISC CPU
//------------------------------------------------------
// Module      : Test Bench
//------------------------------------------------------
// File        : test.v
// Library     : none
// Description : Test Bench for Aquarius.
// Simulator   : Icarus Verilog (Cygwin)
// Synthesizer : Xilinx XST (Windows XP)
// Author      : Thorn Aitch
//------------------------------------------------------
// Revision Number : 1
// Date of Change  : 15th April 2002
// Creator         : Thorn Aitch
// Description     : Initial Design
//------------------------------------------------------
// Revision Number : 2
// Date of Change  : 6th July 2002
// Modifier        : Thorn Aitch
// Description     : Make CPU layer                                
//------------------------------------------------------
// Revision Number : 3
// Date of Change  : 15th August 2002
// Modifier        : Thorn Aitch
// Description     : Separated from Top Layer
//======================================================
// Copyright (C) 2002-2003, Thorn Aitch
//
// Designs can be altered while keeping list of
// modifications "the same as in GNU" No money can
// be earned by selling the designs themselves, but
// anyone can get money by selling the implementation
// of the design, such as ICs based on some cores, 
// boards based on some schematics or Layouts, and
// even GUI interfaces to text mode drivers.
// "The same as GPL SW" Any update to the design
// should be documented and returned to the design. 
// Any derivative work based on the IP should be free
// under OpenIP License. Derivative work means any
// update, change or improvement on the design. 
// Any work based on the design can be either made
// free under OpenIP license or protected by any other
// license. Work based on the design means any work uses
// the OpenIP Licensed core as a building black without
// changing anything on it with any other blocks to
// produce larger design.  There is NO WARRANTY on the
// functionality or performance of the design on the
// real hardware implementation.
// On the other hand, the SuperH-2 ISA (Instruction Set
// Architecture) executed by Aquarius is rigidly
// the property of Renesas Corp. Then you have all 
// responsibility to judge if there are not any 
// infringements to Renesas's rights regarding your 
// Aquarius adoption into your design. 
// By adopting Aquarius, the user assumes all 
// responsibility for its use.
// This project may cause any damages around you, for 
// example, loss of properties, data, money, profits,
// life, or business etc. By adopting this source, 
// the user assumes all responsibility for its use.
//======================================================
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`include "defines.v"
 
//******************************
// Test Bench
//******************************
module test(
    );
 
    reg CLK;
    reg RST_n;
 
//------------------
// Internal Signals
//------------------
 
    reg [31:0] COUNT;  //virtual signal for display
    reg [ 7:0] INDEX;  //virtual index for display
    reg [ 7:0] LCDDBI; //input port
    reg RXD, CTS;      //uart input signals
    reg [ 4:0] KEYXI;  //key input
 
//********
// Modules
//********
    top TOP(
        .CLK_SRC(CLK), .RST_n(RST_n),
           .LCDDBI(LCDDBI), .KEYXI(KEYXI),
           .RXD(RXD), .CTS(CTS)
    );
 
//----------------
// virtual counter
//----------------
    always @(posedge CLK) begin
        if (~RST_n)
            COUNT <= 32'h00000000;
        else
            COUNT <= COUNT + 1'b1;
    end
 
//-----------------
//  CLOCK generator
//-----------------
    initial begin
        CLK <= 1'b1;
    end
    always #(`HALF_CYCLE) begin
        CLK <= ~CLK;
    end
 
//-----------------
// simulation tasks
//-----------------
    task RESET;
        begin
            RST_n <= 1'b0;
        #(`CYCLE);
            RST_n <= 1'b1;
        end
    endtask
 
//--------------
// Input Pattern
//--------------                                                         PL
    initial begin
        RESET;
        LCDDBI <= 8'h00;
        RXD <= 1'b1;
            CTS <= 1'b0;
    #(`CYCLE*100);
        RXD <= 1'b0; //start bit
    #(`CYCLE*24);
        RXD <= 1'b1; //D0
    #(`CYCLE*24);
        RXD <= 1'b0; //D1
    #(`CYCLE*24);
        RXD <= 1'b1; //D2
    #(`CYCLE*24);
        RXD <= 1'b0; //D3
    #(`CYCLE*24);
        RXD <= 1'b1; //D4
    #(`CYCLE*24);
        RXD <= 1'b0; //D5
    #(`CYCLE*24);
        RXD <= 1'b1; //D6
    #(`CYCLE*24);
        RXD <= 1'b0; //D7
    #(`CYCLE*24);
        RXD <= 1'b1; //stop bit
    end
 
//-----------
// SLEEP test
//-----------
    initial begin
        KEYXI[4] <= 1'b1;
    #(`CYCLE*100);
        KEYXI[4] <= 1'b0;
    #(`CYCLE);
        KEYXI[4] <= 1'b1;
    end
 
//************************
// Write Simulation Result
//************************
    integer result;  //write file
    initial
        result = $fopen("test_result.txt");
    initial begin
        $fdisplay(result, "                                                                                                WB_MAC_BUSY/EX_MAC_BUSY/MAC_BUSY/MAC_STALL");
        $fdisplay(result, "             STB                                                              DISPATCH       REG_FWD_X&Y");
        $fdisplay(result, "            CYC IFWD                                                        INSTR_SEQ       NEXT_ID_STALL");
        $fdisplay(result, "          RESn WE                                                      INSTR_STATE         ID_STALL");
        $fdisplay(result, "         CLK  ACK                                                    SLOT                 IF_STALL");
        $fdisplay(result, "---------------------------------------------------------------------");
    end
 
    always begin
        #(`STROBE);
 
        if (COUNT[2:0] == 3'b000)
        $fdisplay(result, "COUNT#   CR CSAWI SEL- ADR----  DATI---- DATO---- PC------ EVR EVI A|S-INST-Q-D-IFDR-IR-- PIPE- ---- CNST-MQT SR------ GBR----- VBR----- PR------ MACH---- MACL---- XBUS---- YBUS---- ZBUS---- WBUS---- MAAD---- MADW---- MADR---- R0------ R1------ R2------ R3------ R4------ R5------ R6------ R7------ R8------ R9------ R10----- R11----- R12----- R13----- R14----- R15----- ");
         $fdisplay(result,
            "%8h %b%b %b%b%b%b%b %4b %8h %8h %8h %8h %3b %3h %b|%b %4h %h %b %4h %4h %b%b%b%b%b %b%b%b%b %4h %b%b%b %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h",
            //  |    |          |                              |S  INSTQ  D  IFDRIR  PIPE                CNSTM Q T  SR  GBR VBR PR  MACHMACLX   Y   Z   W   AD  DW  DR  R0  R1  R2  R3  R4  R5  R6  R7  R8  R9  R10 R11 R12 R13 R14 R15  
            COUNT, CLK ,RST_n,
            TOP.CYC,           // external bus cycle to be kept
            TOP.STB,           // external bus strobe
            TOP.ACK,           // external device acknowledge
            TOP.WE,            // external write/read
            TOP.IF_WIDTH,      // IF_WIDTH : external fetch space width
            TOP.SEL,           // external data valid position
            TOP.ADR,           // external address
            TOP.DATI,          // external data read bus
            TOP.DATO,          // external data write bus
            TOP.CPU.DATAPATH.PC,
            TOP.EVENT_REQ,
            TOP.EVENT_INFO,
            TOP.EVENT_ACK,
 
            TOP.CPU.DECODE.SLOT,
            TOP.CPU.DECODE.INSTR_STATE,
            TOP.CPU.DECODE.INSTR_SEQ,
            TOP.CPU.DECODE.DISPATCH,
            TOP.CPU.DECODE.IF_DR,
            TOP.CPU.DECODE.IR,
            TOP.CPU.DECODE.IF_STALL,
            TOP.CPU.DECODE.ID_STALL,
            TOP.CPU.DECODE.NEXT_ID_STALL,
            TOP.CPU.DECODE.REG_FWD_X,
            TOP.CPU.DECODE.REG_FWD_Y,
            TOP.CPU.DECODE.WB_MAC_BUSY,
            TOP.CPU.DECODE.EX_MAC_BUSY,
            TOP.CPU.DECODE.MAC_BUSY,
            TOP.CPU.DECODE.MAC_STALL,
            TOP.CPU.DECODE.CONST_IFDR,
            TOP.CPU.DATAPATH.SR[9], //M
            TOP.CPU.DATAPATH.SR[8], //Q
            TOP.CPU.DATAPATH.SR[0], //T
            {22'h000000, TOP.CPU.DATAPATH.SR},
            TOP.CPU.DATAPATH.GBR,
            TOP.CPU.DATAPATH.VBR,
            TOP.CPU.DATAPATH.PR,
            TOP.CPU.DATAPATH.MACH,
            TOP.CPU.DATAPATH.MACL,
            TOP.CPU.DATAPATH.XBUS,
            TOP.CPU.DATAPATH.YBUS,
            TOP.CPU.DATAPATH.ZBUS,
            TOP.CPU.DATAPATH.WBUS,
            TOP.CPU.DATAPATH.MA_AD,
            TOP.CPU.DATAPATH.MA_DW,
            TOP.CPU.DATAPATH.MA_DR,
            TOP.CPU.DATAPATH.REGISTER.REG[0],
            TOP.CPU.DATAPATH.REGISTER.REG[1],
            TOP.CPU.DATAPATH.REGISTER.REG[2],
            TOP.CPU.DATAPATH.REGISTER.REG[3],
            TOP.CPU.DATAPATH.REGISTER.REG[4],
            TOP.CPU.DATAPATH.REGISTER.REG[5],
            TOP.CPU.DATAPATH.REGISTER.REG[6],
            TOP.CPU.DATAPATH.REGISTER.REG[7],
            TOP.CPU.DATAPATH.REGISTER.REG[8],
            TOP.CPU.DATAPATH.REGISTER.REG[9],
            TOP.CPU.DATAPATH.REGISTER.REG[10],
            TOP.CPU.DATAPATH.REGISTER.REG[11],
            TOP.CPU.DATAPATH.REGISTER.REG[12],
            TOP.CPU.DATAPATH.REGISTER.REG[13],
            TOP.CPU.DATAPATH.REGISTER.REG[14],
            TOP.CPU.DATAPATH.REGISTER.REG[15]
        );
        #(`CYCLE-`STROBE);
    end
 
//--------------------------
// Simulation Stop Condition
//--------------------------
    always @(COUNT) begin
        if (COUNT == 32'h00002800)
            begin
                $fclose(result);
                $stop;
            end
    end
 
//======================================================
  endmodule
//======================================================

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Subversion Repositories Aquarius

[/] [Aquarius/] [trunk/] [verilog/] [test.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	thorn_aitc	`//======================================================`
2			`// Aquarius Project`
3			`// SuperH-2 ISA Compatible RISC CPU`
4			`//------------------------------------------------------`
5			`// Module : Test Bench`
6			`//------------------------------------------------------`
7			`// File : test.v`
8			`// Library : none`
9			`// Description : Test Bench for Aquarius.`
10			`// Simulator : Icarus Verilog (Cygwin)`
11			`// Synthesizer : Xilinx XST (Windows XP)`
12			`// Author : Thorn Aitch`
13			`//------------------------------------------------------`
14			`// Revision Number : 1`
15			`// Date of Change : 15th April 2002`
16			`// Creator : Thorn Aitch`
17			`// Description : Initial Design`
18			`//------------------------------------------------------`
19			`// Revision Number : 2`
20			`// Date of Change : 6th July 2002`
21			`// Modifier : Thorn Aitch`
22			`// Description : Make CPU layer`
23			`//------------------------------------------------------`
24			`// Revision Number : 3`
25			`// Date of Change : 15th August 2002`
26			`// Modifier : Thorn Aitch`
27			`// Description : Separated from Top Layer`
28			`//======================================================`
29			`// Copyright (C) 2002-2003, Thorn Aitch`
30			`//`
31			`// Designs can be altered while keeping list of`
32			`// modifications "the same as in GNU" No money can`
33			`// be earned by selling the designs themselves, but`
34			`// anyone can get money by selling the implementation`
35			`// of the design, such as ICs based on some cores,`
36			`// boards based on some schematics or Layouts, and`
37			`// even GUI interfaces to text mode drivers.`
38			`// "The same as GPL SW" Any update to the design`
39			`// should be documented and returned to the design.`
40			`// Any derivative work based on the IP should be free`
41			`// under OpenIP License. Derivative work means any`
42			`// update, change or improvement on the design.`
43			`// Any work based on the design can be either made`
44			`// free under OpenIP license or protected by any other`
45			`// license. Work based on the design means any work uses`
46			`// the OpenIP Licensed core as a building black without`
47			`// changing anything on it with any other blocks to`
48			`// produce larger design. There is NO WARRANTY on the`
49			`// functionality or performance of the design on the`
50			`// real hardware implementation.`
51			`// On the other hand, the SuperH-2 ISA (Instruction Set`
52			`// Architecture) executed by Aquarius is rigidly`
53			`// the property of Renesas Corp. Then you have all`
54			`// responsibility to judge if there are not any`
55			`// infringements to Renesas's rights regarding your`
56			`// Aquarius adoption into your design.`
57			`// By adopting Aquarius, the user assumes all`
58			`// responsibility for its use.`
59			`// This project may cause any damages around you, for`
60			`// example, loss of properties, data, money, profits,`
61			`// life, or business etc. By adopting this source,`
62			`// the user assumes all responsibility for its use.`
63			`//======================================================`
64
65			`// synopsys translate_off`
66			`include "timescale.v"
67			`// synopsys translate_on`
68
69			`include "defines.v"
70
71			`//******************************`
72			`// Test Bench`
73			`//******************************`
74			`module test(`
75			`);`
76
77			`reg CLK;`
78			`reg RST_n;`
79
80			`//------------------`
81			`// Internal Signals`
82			`//------------------`
83
84			`reg [31:0] COUNT; //virtual signal for display`
85			`reg [ 7:0] INDEX; //virtual index for display`
86			`reg [ 7:0] LCDDBI; //input port`
87			`reg RXD, CTS; //uart input signals`
88			`reg [ 4:0] KEYXI; //key input`
89
90			`//********`
91			`// Modules`
92			`//********`
93			`top TOP(`
94			`.CLK_SRC(CLK), .RST_n(RST_n),`
95			`.LCDDBI(LCDDBI), .KEYXI(KEYXI),`
96			`.RXD(RXD), .CTS(CTS)`
97			`);`
98
99			`//----------------`
100			`// virtual counter`
101			`//----------------`
102			`always @(posedge CLK) begin`
103			`if (~RST_n)`
104			`COUNT <= 32'h00000000;`
105			`else`
106			`COUNT <= COUNT + 1'b1;`
107			`end`
108
109			`//-----------------`
110			`// CLOCK generator`
111			`//-----------------`
112			`initial begin`
113			`CLK <= 1'b1;`
114			`end`
115			always #(`HALF_CYCLE) begin
116			`CLK <= ~CLK;`
117			`end`
118
119			`//-----------------`
120			`// simulation tasks`
121			`//-----------------`
122			`task RESET;`
123			`begin`
124			`RST_n <= 1'b0;`
125			#(`CYCLE);
126			`RST_n <= 1'b1;`
127			`end`
128			`endtask`
129
130			`//--------------`
131			`// Input Pattern`
132			`//-------------- PL`
133			`initial begin`
134			`RESET;`
135			`LCDDBI <= 8'h00;`
136			`RXD <= 1'b1;`
137			`CTS <= 1'b0;`
138			#(`CYCLE*100);
139			`RXD <= 1'b0; //start bit`
140			#(`CYCLE*24);
141			`RXD <= 1'b1; //D0`
142			#(`CYCLE*24);
143			`RXD <= 1'b0; //D1`
144			#(`CYCLE*24);
145			`RXD <= 1'b1; //D2`
146			#(`CYCLE*24);
147			`RXD <= 1'b0; //D3`
148			#(`CYCLE*24);
149			`RXD <= 1'b1; //D4`
150			#(`CYCLE*24);
151			`RXD <= 1'b0; //D5`
152			#(`CYCLE*24);
153			`RXD <= 1'b1; //D6`
154			#(`CYCLE*24);
155			`RXD <= 1'b0; //D7`
156			#(`CYCLE*24);
157			`RXD <= 1'b1; //stop bit`
158			`end`
159
160			`//-----------`
161			`// SLEEP test`
162			`//-----------`
163			`initial begin`
164			`KEYXI[4] <= 1'b1;`
165			#(`CYCLE*100);
166			`KEYXI[4] <= 1'b0;`
167			#(`CYCLE);
168			`KEYXI[4] <= 1'b1;`
169			`end`
170
171			`//************************`
172			`// Write Simulation Result`
173			`//************************`
174			`integer result; //write file`
175			`initial`
176			`result = $fopen("test_result.txt");`
177			`initial begin`
178			`$fdisplay(result, " WB_MAC_BUSY/EX_MAC_BUSY/MAC_BUSY/MAC_STALL");`
179			`$fdisplay(result, " STB DISPATCH REG_FWD_X&Y");`
180			`$fdisplay(result, " CYC IFWD INSTR_SEQ NEXT_ID_STALL");`
181			`$fdisplay(result, " RESn WE INSTR_STATE ID_STALL");`
182			`$fdisplay(result, " CLK ACK SLOT IF_STALL");`
183			`$fdisplay(result, "---------------------------------------------------------------------");`
184			`end`
185
186			`always begin`
187			#(`STROBE);
188
189			`if (COUNT[2:0] == 3'b000)`
190			`$fdisplay(result, "COUNT# CR CSAWI SEL- ADR---- DATI---- DATO---- PC------ EVR EVI A\|S-INST-Q-D-IFDR-IR-- PIPE- ---- CNST-MQT SR------ GBR----- VBR----- PR------ MACH---- MACL---- XBUS---- YBUS---- ZBUS---- WBUS---- MAAD---- MADW---- MADR---- R0------ R1------ R2------ R3------ R4------ R5------ R6------ R7------ R8------ R9------ R10----- R11----- R12----- R13----- R14----- R15----- ");`
191			`$fdisplay(result,`
192			`"%8h %b%b %b%b%b%b%b %4b %8h %8h %8h %8h %3b %3h %b\|%b %4h %h %b %4h %4h %b%b%b%b%b %b%b%b%b %4h %b%b%b %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h %8h",`
193			`// \| \| \| \|S INSTQ D IFDRIR PIPE CNSTM Q T SR GBR VBR PR MACHMACLX Y Z W AD DW DR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15`
194			`COUNT, CLK ,RST_n,`
195			`TOP.CYC, // external bus cycle to be kept`
196			`TOP.STB, // external bus strobe`
197			`TOP.ACK, // external device acknowledge`
198			`TOP.WE, // external write/read`
199			`TOP.IF_WIDTH, // IF_WIDTH : external fetch space width`
200			`TOP.SEL, // external data valid position`
201			`TOP.ADR, // external address`
202			`TOP.DATI, // external data read bus`
203			`TOP.DATO, // external data write bus`
204			`TOP.CPU.DATAPATH.PC,`
205			`TOP.EVENT_REQ,`
206			`TOP.EVENT_INFO,`
207			`TOP.EVENT_ACK,`
208
209			`TOP.CPU.DECODE.SLOT,`
210			`TOP.CPU.DECODE.INSTR_STATE,`
211			`TOP.CPU.DECODE.INSTR_SEQ,`
212			`TOP.CPU.DECODE.DISPATCH,`
213			`TOP.CPU.DECODE.IF_DR,`
214			`TOP.CPU.DECODE.IR,`
215			`TOP.CPU.DECODE.IF_STALL,`
216			`TOP.CPU.DECODE.ID_STALL,`
217			`TOP.CPU.DECODE.NEXT_ID_STALL,`
218			`TOP.CPU.DECODE.REG_FWD_X,`
219			`TOP.CPU.DECODE.REG_FWD_Y,`
220			`TOP.CPU.DECODE.WB_MAC_BUSY,`
221			`TOP.CPU.DECODE.EX_MAC_BUSY,`
222			`TOP.CPU.DECODE.MAC_BUSY,`
223			`TOP.CPU.DECODE.MAC_STALL,`
224			`TOP.CPU.DECODE.CONST_IFDR,`
225			`TOP.CPU.DATAPATH.SR[9], //M`
226			`TOP.CPU.DATAPATH.SR[8], //Q`
227			`TOP.CPU.DATAPATH.SR[0], //T`
228			`{22'h000000, TOP.CPU.DATAPATH.SR},`
229			`TOP.CPU.DATAPATH.GBR,`
230			`TOP.CPU.DATAPATH.VBR,`
231			`TOP.CPU.DATAPATH.PR,`
232			`TOP.CPU.DATAPATH.MACH,`
233			`TOP.CPU.DATAPATH.MACL,`
234			`TOP.CPU.DATAPATH.XBUS,`
235			`TOP.CPU.DATAPATH.YBUS,`
236			`TOP.CPU.DATAPATH.ZBUS,`
237			`TOP.CPU.DATAPATH.WBUS,`
238			`TOP.CPU.DATAPATH.MA_AD,`
239			`TOP.CPU.DATAPATH.MA_DW,`
240			`TOP.CPU.DATAPATH.MA_DR,`
241			`TOP.CPU.DATAPATH.REGISTER.REG[0],`
242			`TOP.CPU.DATAPATH.REGISTER.REG[1],`
243			`TOP.CPU.DATAPATH.REGISTER.REG[2],`
244			`TOP.CPU.DATAPATH.REGISTER.REG[3],`
245			`TOP.CPU.DATAPATH.REGISTER.REG[4],`
246			`TOP.CPU.DATAPATH.REGISTER.REG[5],`
247			`TOP.CPU.DATAPATH.REGISTER.REG[6],`
248			`TOP.CPU.DATAPATH.REGISTER.REG[7],`
249			`TOP.CPU.DATAPATH.REGISTER.REG[8],`
250			`TOP.CPU.DATAPATH.REGISTER.REG[9],`
251			`TOP.CPU.DATAPATH.REGISTER.REG[10],`
252			`TOP.CPU.DATAPATH.REGISTER.REG[11],`
253			`TOP.CPU.DATAPATH.REGISTER.REG[12],`
254			`TOP.CPU.DATAPATH.REGISTER.REG[13],`
255			`TOP.CPU.DATAPATH.REGISTER.REG[14],`
256			`TOP.CPU.DATAPATH.REGISTER.REG[15]`
257			`);`
258			#(`CYCLE-`STROBE);
259			`end`
260
261			`//--------------------------`
262			`// Simulation Stop Condition`
263			`//--------------------------`
264			`always @(COUNT) begin`
265			`if (COUNT == 32'h00002800)`
266			`begin`
267			`$fclose(result);`
268			`$stop;`
269			`end`
270			`end`
271
272			`//======================================================`
273			`endmodule`
274			`//======================================================`