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[/] [Aquarius/] [trunk/] [verilog/] [timescale.v] - Blame information for rev 12

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1 2 thorn_aitc
//======================================================
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// Aquarius Project
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//    SuperH-2 ISA Compatible RISC CPU
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//------------------------------------------------------
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// Module      : Time Scale Definition
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//------------------------------------------------------
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// File        : timescale.v
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// Library     : none
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// Description : A definition of time scale 
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//               to be included into each source.
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// Simulator   : Icarus Verilog (Cygwin)
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// Synthesizer : Xilinx XST (Windows XP)
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// Author      : Thorn Aitch (xxxx@opencores.org)
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//------------------------------------------------------
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// Revision Number : 1
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// Date of Change  : 15th April 2002
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// Creator         : Thorn Aitch (xxxx@opencores.org)
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// Description     : Initial Design
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//------------------------------------------------------
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// Revision Number : 2
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// Date of Change  : 30th April 2003
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// Modifier        : Thorn Aitch
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// Description     : Release Version 1.0
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//======================================================
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// Copyright (C) 2002-2003, Thorn Aitch
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//
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// Designs can be altered while keeping list of
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// modifications "the same as in GNU" No money can
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// be earned by selling the designs themselves, but
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// anyone can get money by selling the implementation
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// of the design, such as ICs based on some cores, 
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// boards based on some schematics or Layouts, and
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// even GUI interfaces to text mode drivers.
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// "The same as GPL SW" Any update to the design
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// should be documented and returned to the design. 
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// Any derivative work based on the IP should be free
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// under OpenIP License. Derivative work means any
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// update, change or improvement on the design. 
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// Any work based on the design can be either made
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// free under OpenIP license or protected by any other
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// license. Work based on the design means any work uses
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// the OpenIP Licensed core as a building black without
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// changing anything on it with any other blocks to
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// produce larger design.  There is NO WARRANTY on the
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// functionality or performance of the design on the
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// real hardware implementation.
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// On the other hand, the SuperH-2 ISA (Instruction Set
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// Architecture) executed by Aquarius is rigidly
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// the property of Renesas Corp. Then you have all 
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// responsibility to judge if there are not any 
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// infringements to Renesas's rights regarding your 
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// Aquarius adoption into your design. 
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// By adopting Aquarius, the user assumes all 
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// responsibility for its use.
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// This project may cause any damages around you, for 
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// example, loss of properties, data, money, profits,
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// life, or business etc. By adopting this source, 
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// the user assumes all responsibility for its use.
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//======================================================
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// Timescale define
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`timescale 1ns/100ps
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//======================================================
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// End of Module
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//======================================================

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