OpenCores
URL https://opencores.org/ocsvn/Aquarius/Aquarius/trunk

Subversion Repositories Aquarius

[/] [Aquarius/] [trunk/] [verilog/] [uart.v] - Blame information for rev 12

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 thorn_aitc 
//======================================================
2 
// Aquarius Project
3 
//    SuperH-2 ISA Compatible RISC CPU
4 
//------------------------------------------------------
5 
// Module      : UART (Asynchronous Serial Interface)
6 
//------------------------------------------------------
7 
// File        : uart.v
8 
// Library     : none
9 
// Description : Asynchronous Serial Interface
10 
//               8bit, 1stop-bit, non-parity
11 
//               Based on "SASC" from www.opencores.org
12 
// Simulator   : Icarus Verilog (Cygwin)
13 
// Synthesizer : Xilinx XST (Windows XP)
14 
// Author      : Thorn Aitch
15 
//------------------------------------------------------
16 
// Revision Number : 1
17 
// Date of Change  : 30th October 2002
18 
// Creator         : Thorn Aitch
19 
// Description     : Initial Design
20 
//------------------------------------------------------
21 
// Revision Number : 2
22 
// Date of Change  : 30th April 2003
23 
// Modifier        : Thorn Aitch
24 
// Description     : Release Version 1.0
25 
//======================================================
26 
// Copyright (C) 2002-2003, Thorn Aitch
27 
//
28 
// Designs can be altered while keeping list of
29 
// modifications "the same as in GNU" No money can
30 
// be earned by selling the designs themselves, but
31 
// anyone can get money by selling the implementation
32 
// of the design, such as ICs based on some cores,
33 
// boards based on some schematics or Layouts, and
34 
// even GUI interfaces to text mode drivers.
35 
// "The same as GPL SW" Any update to the design
36 
// should be documented and returned to the design.
37 
// Any derivative work based on the IP should be free
38 
// under OpenIP License. Derivative work means any
39 
// update, change or improvement on the design.
40 
// Any work based on the design can be either made
41 
// free under OpenIP license or protected by any other
42 
// license. Work based on the design means any work uses
43 
// the OpenIP Licensed core as a building black without
44 
// changing anything on it with any other blocks to
45 
// produce larger design.  There is NO WARRANTY on the
46 
// functionality or performance of the design on the
47 
// real hardware implementation.
48 
// On the other hand, the SuperH-2 ISA (Instruction Set
49 
// Architecture) executed by Aquarius is rigidly
50 
// the property of Renesas Corp. Then you have all
51 
// responsibility to judge if there are not any
52 
// infringements to Renesas's rights regarding your
53 
// Aquarius adoption into your design.
54 
// By adopting Aquarius, the user assumes all
55 
// responsibility for its use.
56 
// This project may cause any damages around you, for
57 
// example, loss of properties, data, money, profits,
58 
// life, or business etc. By adopting this source,
59 
// the user assumes all responsibility for its use.
60 
//======================================================
61 
 
62 
`include "timescale.v"
63 
`include "defines.v"
64 
 
65 
//======================================================
66 
// UART : Asynchronous Serial Interface
67 
//
68 
// [UARTREG] 32bit Register
69 
//
70 
// 2'h0 : UARTBG0 Baud Rate Generator Div0 (read/write)
71 
//  31    30    29    28    27    26    25    24
72 
//   7     6     5     4     3     2     1     0
73 
// -----------------------------------------------
74 
//| B07 | B06 | B05 | B04 | B03 | B02 | B01 | B00 |
75 
// -----------------------------------------------
76 
//
77 
// 2'h1 : UARTBG1 Baud Rate Generator Div1 (read/write)
78 
//  23    22    21    20    19    18    17    16
79 
//   7     6     5     4     3     2     1     0
80 
// -----------------------------------------------
81 
//| B17 | B16 | B15 | B14 | B13 | B12 | B11 | B10 |
82 
// -----------------------------------------------
83 
//
84 
// 2'h2 : UARTCON (TXE=~full_o, RXF=~empty_o) (read only)
85 
//  15    14    13    12    11    10       9          8
86 
//   7     6     5     4     3     2       1          0
87 
// --------------------------------------------------------
88 
//|     |     |     |     |     |     | TX_full | RX_empty |
89 
// --------------------------------------------------------
90 
//
91 
// 2'h3 : UARTTXD(Write)/UARTRXD(Read)
92 
//   7     6     5     4     3     2     1     0
93 
//   7     6     5     4     3     2     1     0
94 
// -----------------------------------------------
95 
//| TR7 | TR6 | TR5 | TR4 | TR3 | TR2 | TR1 | TR0 |
96 
// -----------------------------------------------
97 
 
98 
//*************************************************
99 
// Module Definition
100 
//*************************************************
101 
module uart (
102 
               CLK, RST,
103 
               CE, WE, SEL,
104 
               DATI, DATO,
105 
               RXD, TXD, CTS, RTS
106 
           );
107 
 
108 
//-------------------
109 
// Module I/O Signals
110 
//-------------------
111 
    input  CLK;          // clock
112 
    input  RST;          // reset
113 
    input  CE;           // chip enable
114 
    input  WE;           // write enable (read = 0, write = 1)
115 
    input  [3:0]SEL;     // data valid position
116 
    input  [31:0] DATI;  // write data
117 
    output [31:0] DATO;  // read data
118 
    input  RXD;          // receive data
119 
    output TXD;          // transmit data
120 
    input  CTS;          // clear to send
121 
    output RTS;          // request to send
122 
 
123 
//-----------------
124 
// Internal Signals
125 
//-----------------
126 
    reg    WRTXD,  RDRXD;
127 
    reg    WRTXD1, RDRXD1;
128 
    reg    [31:0] DATO;
129 
 
130 
    wire   RXD, TXD, CTS, RTS;
131 
    wire   sio_ce, sio_ce_x4;
132 
    reg    [7:0] din_i;  // TX_DATA
133 
    wire   [7:0] dout_o; // RX_DATA
134 
    reg    re_i, we_i;
135 
    wire   full_o, empty_o;
136 
    reg    [7:0] div0;
137 
    reg    [7:0] div1;
138 
 
139 
//----------------------
140 
// Register R/W Operation
141 
//----------------------
142 
    always @(posedge CLK or posedge RST) begin
143 
        if (RST == 1'b1)
144 
            div0[7:0] <= 8'h00;
145 
        else if ((CE == 1'b1) && (WE == 1'b1) && (SEL[3] == 1'b1))
146 
            div0[7:0] <= DATI[31:24];
147 
    end
148 
    always @(posedge CLK or posedge RST) begin
149 
        if (RST == 1'b1)
150 
            div1[7:0] <= 8'h00;
151 
        else if ((CE == 1'b1) && (WE == 1'b1) && (SEL[2] == 1'b1))
152 
            div1[7:0] <= DATI[23:16];
153 
    end
154 
    always @(posedge CLK or posedge RST) begin
155 
        if (RST == 1'b1)
156 
            din_i[7:0] <= 8'h00;
157 
        else if (WRTXD)
158 
            din_i[7:0] <= DATI[7:0];
159 
    end
160 
//-----------------------
161 
    always @(CE or div0 or div1 or full_o or empty_o or dout_o)
162 
    begin
163 
        if (CE == 1'b1)
164 
            begin
165 
                DATO[31:24] <= div0[7:0];
166 
                DATO[23:16] <= div1[7:0];
167 
                            DATO[15: 8] <= {6'h00, full_o, empty_o};
168 
                            DATO[ 7: 0] <= dout_o;
169 
            end
170 
        else
171 
            begin
172 
                DATO[31:0] <= 32'h00000000;
173 
            end
174 
    end
175 
//-----------------------
176 
    always @(CE or WE or SEL)
177 
    begin
178 
        if ((CE == 1'b1) && (WE == 1'b1) && (SEL[0] == 1'b1))
179 
               WRTXD <= 1'b1;
180 
        else
181 
               WRTXD <= 1'b0;
182 
    end
183 
    always @(posedge CLK or posedge RST)
184 
    begin
185 
           if (RST)
186 
               WRTXD1 <= 1'b0;
187 
           else
188 
               WRTXD1 <= WRTXD;
189 
    end
190 
    always @(WRTXD or WRTXD1)
191 
    begin
192 
           we_i <= ~WRTXD & WRTXD1; // negate edge of WRTXD
193 
    end
194 
//-----------------------
195 
    always @(CE or WE or SEL)
196 
    begin
197 
        if ((CE == 1'b1) && (WE == 1'b0) && (SEL[0] == 1'b1))
198 
               RDRXD <= 1'b1;
199 
        else
200 
               RDRXD <= 1'b0;
201 
    end
202 
    always @(posedge CLK or posedge RST)
203 
    begin
204 
           if (RST)
205 
               RDRXD1 <= 1'b0;
206 
           else
207 
               RDRXD1 <= RDRXD;
208 
    end
209 
    always @(RDRXD or RDRXD1)
210 
    begin
211 
           re_i <= ~RDRXD & RDRXD1; // negate edge of RDRXD
212 
    end
213 
 
214 
//---------------------
215 
// UART Internal Blocks
216 
//---------------------
217 
 
218 
sasc_top TOP(.clk(CLK), .rst(~RST),
219 
             .rxd_i(RXD), .txd_o(TXD), .cts_i(CTS), .rts_o(RTS),
220 
                   .sio_ce(sio_ce), .sio_ce_x4(sio_ce_x4),
221 
                .din_i(din_i), .dout_o(dout_o), .re_i(re_i), .we_i(we_i),
222 
                   .full_o(full_o), .empty_o(empty_o)
223 
               );
224 
 
225 
sasc_brg BRG(.clk(CLK), .rst(~RST),
226 
           .div0(div0), .div1(div1),
227 
                   .sio_ce(sio_ce), .sio_ce_x4(sio_ce_x4)
228 
            );
229 
 
230 
//======================================================
231 
  endmodule
232 
//======================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.