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<p class="MsoNormal" style="text-align: left" align="left"><b>
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<span lang="EN-US" style="font-size: 18pt; color: #bf0000; font-family: Verdana">
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Project: Aquarius</span></b><span lang="EN-US" style="color: black; font-family: Verdana"><font size="5">
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</font></span></p>
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<p class="MsoNormal" style="text-align: left" align="left"><b>
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<span lang="EN-US" style="font-size: 13.5pt; color: black; font-family: Verdana">
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&nbsp;</span></b></p>
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<p class="MsoNormal" align="left"><font size="4"><b>
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<span style="font-family: Verdana">Introduction</span></b></font></p>
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<p class="MsoBodyText">
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<span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Aquarius is a
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Core IP (Intellectual Property) of pipelined RISC CPU and can execute SuperH-2
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instructions. Follows are <span class="SpellE">SuperH</span> characteristics.</span><!--[if gte vml 1]><v:shapetype id="_x0000_t75"
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<ol>
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  <li>
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  <p class="MsoBodyText"><span class="SpellE">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">SuperH</span></span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  is a very popular CPU core. The software development environments </span>
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">such</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  as C c</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">ompiler
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  have been well prepared. The GNU C compiler for <span class="SpellE">SuperH</span>
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  is very famous and easy to get. The <span class="SpellE">SuperH</span> had
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  been developed by Hitachi, Ltd. Now, semiconductor group of Hitachi has merged
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  with same group of <span class="SpellE">Mitsubish</span> and new semiconductor
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  company &#8220;<span class="SpellE">Renesas</span> Technology Corp.&#8221; has established
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  in April, 2003.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">SuperH-2 is a
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  CPU for MCU (Micro Controller Unit). Then the CPU need not handle complex
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  exception recovering such as</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  memory fault exception from</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  M</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">MU (Mem</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">ory
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  Managing Unit). This means SuperH-2 has simple structure, easiness to design,
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  and it does not consume many logic gates and power.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">All SuperH-2
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  instructions have 16bit length. It also makes the hardware very simple. And
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  most important aspect from 16bit fixed length of instructions is that the
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  object code size compiled from C source programs becomes very small.</span></li>
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</ol>
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<p class="MsoBodyText"><b>
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<span lang="EN-US" style="font-size: 13.5pt; color: black; font-family: Verdana">
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Features</span></b></p>
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<p class="MsoBodyText"><font size="3"><span style="font-family: Verdana">Follows
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are Aquarius features.</span></font></p>
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<ol>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Instruction
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  set is compatible with Super</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">H-2.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Bus interface
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  is compatible with WISHBONE.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Aquarius is
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  written in <span class="SpellE">Verilog</span> RTL codes.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Aquarius has
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  verified on a test bench by vector simulation and FPGA implementation with GNU</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  Assemble and C Compiler.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Interrupt</span><span style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">s</span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  and Exception</span><span style="font-size: 12pt; font-family: Verdana">s</span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  are fully supported.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Low Power
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  Mode (SLEEP) is supported.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Some small
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  applications are provided including debugging monitor for a FPGA board.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">A complete
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  Document with over 100 pages, describing</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  Usage of Aqua</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">rius,
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  FPGA Implementation and Inside</span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  Aquarius, is provided.</span></li>
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</ol>
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<p class="MsoBodyText" align="center">
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<span lang="EN-US" style="font-size: 10.5pt; font-family: Century"><!--[if gte vml 1]><v:shape
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src="aquarius.files/image004.gif" v:shapes="_x0000_s1067"><![endif]></span><span style="font-size: 10.5pt; font-family: Century">&nbsp;
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</span></p>
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<p class="MsoBodyText">&nbsp;</p>
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<p class="MsoBodyText"><font size="4"><b><span style="font-family: Verdana">
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Deliverables</span></b></font><span lang="EN-US" style="font-size: 10.5pt; font-family: Century"><!--[if gte vml 1]><v:shape
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</v:shape><![endif]--><![if !vml]><img border=0 width=313 height=238
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src="aquarius.files/image006.gif" align=right v:shapes="_x0000_s1082"><![endif]></span></p>
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<p class="MsoBodyText"><font size="3"><span style="font-family: Verdana">Follows
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are Aquarius features.</span></font></p>
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<ol>
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  <li>
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  <p class="MsoBodyText"><span class="SpellE">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Verilog</span></span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  RTL codes for CPU, and Test Bench including modules comprising MCU</span><font size="3"><span style="font-family: Verdana">,</span></font><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  such as UART, System Controller, Parallel I/O Interface, and Internal Memories
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  (ROM/RAM).</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Verification
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  Resources, such as Converter </span>
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  <span style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">from </span>
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  <span lang="EN-US" style="font-size: 12pt; font-family: Verdana">S-format to
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  <span class="SpellE">Verilog</span> format </span>
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  <span lang="EN-US" style="font-size: 12pt; font-family: Verdana">for ROM
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  coding</span><span style="font-size: 12pt; font-family: Verdana">,</span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  </span><span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">and
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  </span><span style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Assemble Source</span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  Programs</span><span style="font-size: 12pt; font-family: Verdana"> for Vector
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  Simulation</span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">FPGA
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  Resources, such as </span><span style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  Circuit Schematics of</span><span style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">
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  Interface Board, </span>
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  <span lang="EN-US" style="font-size: 12pt; font-family: Verdana">Converter
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  from S-format to </span><span class="SpellE">
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  <span style="font-size: 12pt; font-family: Verdana">Xilinx </span>
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  <span lang="EN-US" style="font-size: 12pt; font-family: Verdana">BlockRAM</span></span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana"><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  INIT statements for RAM initialization</span></span><span style="font-size: 12pt; font-family: Verdana">,</span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">
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  and </span><span style="font-size: 12pt; font-family: Verdana">a sample of
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  </span><span lang="EN-US" style="font-size: 12pt; font-family: Verdana">User
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  Constraints File.</span></li>
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  <li>
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  <p class="MsoBodyText">
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  <span lang="EN-US" style="FONT-SIZE: 12pt; FONT-FAMILY: Verdana">Small
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  Applications including LCD Test Program, Clock using interrupt, and Debugging
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  Monitor.</span><span style="font-size: 10.5pt; font-family: Century"> </span>
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  </li>
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</ol>
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<p class="MsoBodyText"><font size="4">
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<span style="font-family: Verdana; font-weight: 700">Development Status</span></font><span lang="EN-US" style="font-size: 10.5pt; font-family: Century"><!--[if gte vml 1]><v:shape
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 <v:imagedata src="aquarius.files/image007.wmz" o:title=""/>
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</v:shape><![endif]--><![if !vml]><img border=0 width=321 height=338
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src="aquarius.files/image008.gif" align=right v:shapes="_x0000_s1083"><![endif]></span></p>
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<ol>
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  <li>
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  <p class="MsoNormal" style="text-align: left" align="left">
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  <span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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  RTL coding and verifying </span>
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  <span style="font-size: 12pt; color: black; font-family: Verdana">have already
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  been</span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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  finished. </span></li>
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  <li>
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  <p class="MsoNormal" style="text-align: left" align="left">
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  <span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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  FPGA</span><span style="font-size: 12pt; color: black; font-family: Verdana">
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  (Xilinx VirtexE)</span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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  implementation with LCD, Matrix</span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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  Keyboard and RS-232C interfaces has also finished using GNU Assembler and C
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  Compiler.</span></li>
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  <li>
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  <p class="MsoNormal" style="text-align: left" align="left"><font size="3">
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  <span style="font-family: Verdana">Some small Applications using FPGA and its
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  interface board have finished.</span></font></li>
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</ol>
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<p class="MsoNormal" style="text-align: left" align="left"><b>
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<span lang="EN-US" style="font-size: 13.5pt; color: black; font-family: Verdana">
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Download</span></b><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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</span></p>
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<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
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<span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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Document, RTL Source codes and related Tools can be downloaded from the
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<span class="SpellE">OpenCopres</span> CVS under the directory </span>
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<span style="font-size: 12pt; color: black; font-family: Verdana">&quot;</span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">Aquarius</span><span style="font-size: 12pt; color: black; font-family: Verdana">&quot;</span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">.</span></p>
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<p class="MsoNormal" style="text-align: left" align="left"><font size="4">
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<span style="color: black; font-family: Verdana"><b>Performance</b></span></font><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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</span></p>
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<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
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<span style="font-size: 12pt; color: black; font-family: Verdana">Aquarius has
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implemented into FPGA.</span></p>
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<table border="1" cellpadding="0" cellspacing="0" style="border-collapse: collapse" bordercolor="#111111" width="49%" id="AutoNumber1" height="49">
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  <tr>
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    <td width="51%" bgcolor="#FFFF99" height="24">
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    <p class="MsoNormal" style="text-align: left" align="left">
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    <span class="SpellE">
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    <span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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    Xilinx</span></span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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    <span class="SpellE">VirtexE</span> (XCV300E)</span></td>
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    <td width="49%" bgcolor="#CCFFFF" height="24">
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    <p class="MsoNormal" style="text-align: left" align="left">
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    <span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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    2753 slices @21MHz</span></td>
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  </tr>
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  <tr>
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    <td width="51%" bgcolor="#FFFF99" height="24">
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    <p class="MsoNormal" style="text-align: left" align="left">
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    <span class="SpellE">
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    <span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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    Altera</span></span><span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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    <span class="SpellE">Stratix</span> (EP1S10</span><span style="font-size: 12pt; color: black; font-family: Verdana">)</span></td>
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    <td width="49%" bgcolor="#CCFFFF" height="24">
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    <p class="MsoNormal" style="text-align: left" align="left">
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    <span lang="EN-US" style="font-size: 12pt; color: black; font-family: Verdana">
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    7499 cells @31MHz</span></td>
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  </tr>
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</table>
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<p class="MsoNormal" style="text-align: left" align="left">&nbsp;</p>
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<p class="MsoNormal" style="text-align: left" align="left"><font size="4"><b>
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<span style="font-family: Verdana">Project News</span></b></font></p>
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<table border="1" cellpadding="0" cellspacing="0" style="border-collapse: collapse" bordercolor="#111111" width="100%" id="AutoNumber2" height="54">
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  <tr>
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    <td width="27%" height="26" bgcolor="#66FFFF"><b><font face="Verdana">Date</font></b></td>
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    <td width="73%" height="26" bgcolor="#66FFFF"><b><font face="Verdana">News</font></b></td>
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  </tr>
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  <tr>
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    <td width="27%" height="27" bgcolor="#EAEAEA"><font face="Verdana">12/7/2003</font></td>
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    <td width="73%" height="27" bgcolor="#EAEAEA"><font face="Verdana">Project
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    Start and First Release</font></td>
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  </tr>
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</table>
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<p class="MsoNormal" style="text-align: left" align="left">&nbsp;</p>
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<p class="MsoNormal" style="text-align: left" align="left"><font size="4">
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<span style="color: black; font-family: Verdana"><b>Links</b></span></font></p>
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<p class="MsoNormal" style="text-align: left" align="left">&nbsp;</p>
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<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
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<font face="Verdana" size="3">Renesas Technology Corp.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
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<a href="http://www.renesas.com/">http://www.renesas.com/</a></font></p>
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<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
327 
<font face="Verdana" size="3">SuperH Family&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
328 
<a href="http://www.renesas.com/eng/products/mpumcu/32bit/sh/index.html">
329 
http://www.renesas.com/eng/products/mpumcu/32bit/sh/index.html</a></font></p>
330 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
331 
<font face="Verdana" size="3">HuMANDATA Ltd.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
332 
<a href="http://www.hdl.co.jp/home.html">http://www.hdl.co.jp/home.html</a></font></p>
333 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
334 
<font face="Verdana" size="3">Schematic of FPGA Board&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
335 
<a href="http://www.hdl.co.jp/ftpdata/xsp-009/XSP009.sch.pdf">
336 
http://www.hdl.co.jp/ftpdata/xsp-009/XSP009.sch.pdf</a></font></p>
337 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
338 
<font face="Verdana" size="3">SUNLIKE Displays Tech Corp.&nbsp;&nbsp;&nbsp;
339 
<a href="http://www.lcd-modules.com.tw/">http://www.lcd-modules.com.tw/</a></font></p>
340 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
341 
<font face="Verdana" size="3">LCD SC-1602B Datasheet&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
342 
<a href="http://www.lcd-modules.com.tw/data/SC/SC1602B.pdf">
343 
http://www.lcd-modules.com.tw/data/SC/SC1602B.pdf</a></font></p>
344 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
345 
<font face="Verdana" size="3">LCD Timing&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
346 
<a href="http://www.lcd-modules.com.tw/data/SU/P32.pdf">
347 
http://www.lcd-modules.com.tw/data/SU/P32.pdf</a></font></p>
348 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
349 
<font face="Verdana" size="3">LCD Display Commands&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
350 
<a href="http://www.lcd-modules.com.tw/data/SU/P33.pdf">
351 
http://www.lcd-modules.com.tw/data/SU/P33.pdf</a></font></p>
352 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
353 
<font face="Verdana" size="3">LCD Initialization&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
354 
<a href="http://www.lcd-modules.com.tw/data/SU/P34.pdf">
355 
http://www.lcd-modules.com.tw/data/SU/P34.pdf</a></font></p>
356 
<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
357 
<font face="Verdana" size="3">Analog Devices Inc.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
358 
<a href="http://www.analog.com/">http://www.analog.com/</a></font></p>
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<p class="MsoNormal" style="text-align: left; margin-bottom: 12pt" align="left">
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<font face="Verdana" size="3">RS-232C PHY&nbsp;&nbsp;&nbsp;&nbsp;
361 
<a href="http://www.analog.com/UploadedFiles/Data_Sheets/452317841ADM222_32A_42_a.pdf">
362 
http://www.analog.com/UploadedFiles/Data_Sheets/452317841ADM222_32A_42_a.pdf</a></font></p>
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<p class="MsoNormal" style="text-align: left" align="left"><font size="4"><b>
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This web page is maintained by Thorn Aitch </span>
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