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[/] [BasicRSA/] [trunk/] [rtl/] [vhdl/] [rsacypher.vhd] - Blame information for rev 4

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----------------------------------------------------------------------
----                                                                                                                                                                    ----
---- Basic RSA Public Key Cryptography IP Core                                                  ----
----                                                                                                                                                                    ----
---- Implementation of BasicRSA IP core according to                                    ----
---- BasicRSA IP core specification document.                                                   ----
----                                                                                                                                                                    ----
---- To Do:                                                                                                                                             ----
---- -                                                                                                                                                          ----
----                                                                                                                                                                    ----
---- Author(s):                                                                                                                                         ----
---- - Steven R. McQueen, srmcqueen@opencores.org                                               ----
----                                                                                                                                                                    ----
----------------------------------------------------------------------
----                                                                                                                                                                    ----
---- Copyright (C) 2001 Authors and OPENCORES.ORG                                               ----
----                                                                                                                                                                    ----
---- This source file may be used and distributed without                       ----
---- restriction provided that this copyright statement is not  ----
---- removed from the file and that any derivative work contains        ----
---- the original copyright notice and the associated disclaimer. ----
----                                                                                                                                                                    ----
---- This source file is free software; you can redistribute it         ----
---- and/or modify it under the terms of the GNU Lesser General         ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any         ----
---- later version.                                                                                                                             ----
----                                                                                                                                                                    ----
---- This source is distributed in the hope that it will be             ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
---- PURPOSE. See the GNU Lesser General Public License for more        ----
---- details.                                                                                                                                           ----
----                                                                                                                                                                    ----
---- You should have received a copy of the GNU Lesser General  ----
---- Public License along with this source; if not, download it         ----
---- from http://www.opencores.org/lgpl.shtml                                                   ----
----                                                                                                                                                                    ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
 
-- This module implements the RSA Public Key Cypher. It expects to receive the data block
-- to be encrypted or decrypted on the indata bus, the exponent to be used on the inExp bus,
-- and the modulus on the inMod bus. The data block must have a value less than the modulus.
-- It may be worth noting that in practice the exponent is not restricted to the size of the
-- modulus, as would be implied by the bus sizes used in this design. This design must
-- therefore be regarded as a demonstration only.
--
-- A Square-and-Multiply algorithm is used in this module. For each bit of the exponent, the
-- message value is squared. For each '1' bit of the exponent, the message value is multiplied
-- by the result of the squaring operation. The operation ends when there are no more '1'
-- bits in the exponent. Unfortunately, the squaring multiplication must be performed whether
-- the corresponding exponent bit is '1' or '0', so very little is gained by skipping the
-- multiplication of the data value. A multiplication is performed for every significant bit
-- in the exponent.
--
-- Comments, questions and suggestions may be directed to the author at srmcqueen@mcqueentech.com.
 
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity RSACypher is
        Generic (KEYSIZE: integer := 32);
    Port (indata: in std_logic_vector(KEYSIZE-1 downto 0);
                         inExp: in std_logic_vector(KEYSIZE-1 downto 0);
                         inMod: in std_logic_vector(KEYSIZE-1 downto 0);
                         cypher: out std_logic_vector(KEYSIZE-1 downto 0);
                         clk: in std_logic;
                         ds: in std_logic;
                         reset: in std_logic;
                         ready: out std_logic
                         );
end RSACypher;
 
architecture Behavioral of RSACypher is
attribute keep: string;
 
component modmult is
        Generic (MPWID: integer);
    Port ( mpand : in std_logic_vector(MPWID-1 downto 0);
           mplier : in std_logic_vector(MPWID-1 downto 0);
           modulus : in std_logic_vector(MPWID-1 downto 0);
           product : out std_logic_vector(MPWID-1 downto 0);
           clk : in std_logic;
           ds : in std_logic;
                          reset : in std_logic;
                          ready: out std_logic);
end component;
 
signal modreg: std_logic_vector(KEYSIZE-1 downto 0);     -- store the modulus value during operation
signal root: std_logic_vector(KEYSIZE-1 downto 0);       -- value to be squared
signal square: std_logic_vector(KEYSIZE-1 downto 0);     -- result of square operation
signal sqrin: std_logic_vector(KEYSIZE-1 downto 0);      -- 1 or copy of root
signal tempin: std_logic_vector(KEYSIZE-1 downto 0);     -- 1 or copy of square
signal tempout: std_logic_vector(KEYSIZE-1 downto 0);    -- result of multiplication
signal count: std_logic_vector(KEYSIZE-1 downto 0);      -- working copy of exponent
 
signal multrdy, sqrrdy, bothrdy: std_logic;     -- signals to indicate completion of multiplications
signal multgo, sqrgo: std_logic;        -- signals to trigger start of multiplications
signal done: std_logic; -- signal to indicate encryption complete
 
--   The following attributes can be set to make signal tracing easier
 
--attribute keep of multrdy: signal is "true";
--attribute keep of sqrrdy: signal is "true";
--attribute keep of bothrdy: signal is "true";
--attribute keep of multgo: signal is "true";
--attribute keep of sqrgo: signal is "true";
 
 
begin
 
        ready <= done;
        bothrdy <= multrdy and sqrrdy;
 
        -- Modular multiplier to produce products
        modmultiply: modmult
        Generic Map(MPWID => KEYSIZE)
        Port Map(mpand => tempin,
                                mplier => sqrin,
                                modulus => modreg,
                                product => tempout,
                                clk => clk,
                                ds => multgo,
                                reset => reset,
                                ready => multrdy);
 
        -- Modular multiplier to take care of squaring operations
        modsqr: modmult
        Generic Map(MPWID => KEYSIZE)
        Port Map(mpand => root,
                                mplier => root,
                                modulus => modreg,
                                product => square,
                                clk => clk,
                                ds => multgo,
                                reset => reset,
                                ready =>sqrrdy);
 
        --counter manager process tracks counter and enable flags
        mngcount: process (clk, reset, done, ds, count, bothrdy) is
        begin
        -- handles DONE and COUNT signals
 
                if reset = '1' then
                        count <= (others => '0');
                        done <= '1';
                elsif rising_edge(clk) then
                        if done = '1' then
                                if ds = '1' then
-- first time through
                                        count <= '0' & inExp(KEYSIZE-1 downto 1);
                                        done <= '0';
                                end if;
-- after first time
                        elsif count = 0 then
                                if bothrdy = '1' and multgo = '0' then
                                        cypher <= tempout;              -- set output value
                                        done <= '1';
                                end if;
                        elsif bothrdy = '1' then
                                if multgo = '0' then
                                        count <= '0' & count(KEYSIZE-1 downto 1);
                                end if;
                        end if;
                end if;
 
        end process mngcount;
 
        -- This process sets the input values for the squaring multitplier
        setupsqr: process (clk, reset, done, ds) is
        begin
 
                if reset = '1' then
                        root <= (others => '0');
                        modreg <= (others => '0');
                elsif rising_edge(clk) then
                        if done = '1' then
                                if ds = '1' then
                -- first time through, input is sampled only once
                                        modreg <= inMod;
                                        root <= indata;
                                end if;
                -- after first time, square result is fed back to multiplier
                        else
                                root <= square;
                        end if;
                end if;
 
        end process setupsqr;
 
        -- This process sets input values for the product multiplier
        setupmult: process (clk, reset, done, ds) is
        begin
 
                if reset = '1' then
                        tempin <= (others => '0');
                        sqrin <= (others => '0');
                        modreg <= (others => '0');
                elsif rising_edge(clk) then
                        if done = '1' then
                                if ds = '1' then
                -- first time through, input is sampled only once
                -- if the least significant bit of the exponent is '1' then we seed the
                --              multiplier with the message value. Otherwise, we seed it with 1.
                --    The square is set to 1, so the result of the first multiplication will be
                --    either 1 or the initial message value
                                        if inExp(0) = '1' then
                                                tempin <= indata;
                                        else
                                                tempin(KEYSIZE-1 downto 1) <= (others => '0');
                                                tempin(0) <= '1';
                                        end if;
                                        modreg <= inMod;
                                        sqrin(KEYSIZE-1 downto 1) <= (others => '0');
                                        sqrin(0) <= '1';
                                end if;
                -- after first time, the multiplication and square results are fed back through the multiplier.
                -- The counter (exponent) has been shifted one bit to the right
                -- If the least significant bit of the exponent is '1' the result of the most recent
                --              squaring operation is fed to the multiplier.
                --      Otherwise, the square value is set to 1 to indicate no multiplication.
                        else
                                tempin <= tempout;
                                if count(0) = '1' then
                                        sqrin <= square;
                                else
                                        sqrin(KEYSIZE-1 downto 1) <= (others => '0');
                                        sqrin(0) <= '1';
                                end if;
                        end if;
                end if;
 
        end process setupmult;
 
        -- this process enables the multipliers when it is safe to do so
        crypto: process (clk, reset, done, ds, count, bothrdy) is
        begin
 
                if reset = '1' then
                        multgo <= '0';
                elsif rising_edge(clk) then
                        if done = '1' then
                                if ds = '1' then
                -- first time through - automatically trigger first multiplier cycle
                                        multgo <= '1';
                                end if;
                -- after first time, trigger multipliers when both operations are complete
                        elsif count /= 0 then
                                if bothrdy = '1' then
                                        multgo <= '1';
                                end if;
                        end if;
                -- when multipliers have been started, disable multiplier inputs
                                if multgo = '1' then
                                        multgo <= '0';
                                end if;
                end if;
 
        end process crypto;
 
end Behavioral;

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[/] [BasicRSA/] [trunk/] [rtl/] [vhdl/] [rsacypher.vhd] - Blame information for rev 4

Line No.	Rev	Author	Line
1	2	srmcqueen	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- Basic RSA Public Key Cryptography IP Core ----`
4			`---- ----`
5			`---- Implementation of BasicRSA IP core according to ----`
6			`---- BasicRSA IP core specification document. ----`
7			`---- ----`
8			`---- To Do: ----`
9			`---- - ----`
10			`---- ----`
11			`---- Author(s): ----`
12			`---- - Steven R. McQueen, srmcqueen@opencores.org ----`
13			`---- ----`
14			`----------------------------------------------------------------------`
15			`---- ----`
16			`---- Copyright (C) 2001 Authors and OPENCORES.ORG ----`
17			`---- ----`
18			`---- This source file may be used and distributed without ----`
19			`---- restriction provided that this copyright statement is not ----`
20			`---- removed from the file and that any derivative work contains ----`
21			`---- the original copyright notice and the associated disclaimer. ----`
22			`---- ----`
23			`---- This source file is free software; you can redistribute it ----`
24			`---- and/or modify it under the terms of the GNU Lesser General ----`
25			`---- Public License as published by the Free Software Foundation; ----`
26			`---- either version 2.1 of the License, or (at your option) any ----`
27			`---- later version. ----`
28			`---- ----`
29			`---- This source is distributed in the hope that it will be ----`
30			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
31			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
32			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
33			`---- details. ----`
34			`---- ----`
35			`---- You should have received a copy of the GNU Lesser General ----`
36			`---- Public License along with this source; if not, download it ----`
37			`---- from http://www.opencores.org/lgpl.shtml ----`
38			`---- ----`
39			`----------------------------------------------------------------------`
40			`--`
41			`-- CVS Revision History`
42			`--`
43			`-- $Log: not supported by cvs2svn $`
44			`--`
45
46			`-- This module implements the RSA Public Key Cypher. It expects to receive the data block`
47			`-- to be encrypted or decrypted on the indata bus, the exponent to be used on the inExp bus,`
48			`-- and the modulus on the inMod bus. The data block must have a value less than the modulus.`
49			`-- It may be worth noting that in practice the exponent is not restricted to the size of the`
50			`-- modulus, as would be implied by the bus sizes used in this design. This design must`
51			`-- therefore be regarded as a demonstration only.`
52			`--`
53			`-- A Square-and-Multiply algorithm is used in this module. For each bit of the exponent, the`
54			`-- message value is squared. For each '1' bit of the exponent, the message value is multiplied`
55			`-- by the result of the squaring operation. The operation ends when there are no more '1'`
56			`-- bits in the exponent. Unfortunately, the squaring multiplication must be performed whether`
57			`-- the corresponding exponent bit is '1' or '0', so very little is gained by skipping the`
58			`-- multiplication of the data value. A multiplication is performed for every significant bit`
59			`-- in the exponent.`
60			`--`
61			`-- Comments, questions and suggestions may be directed to the author at srmcqueen@mcqueentech.com.`
62
63
64			`library IEEE;`
65			`use IEEE.STD_LOGIC_1164.ALL;`
66			`use IEEE.STD_LOGIC_ARITH.ALL;`
67			`use IEEE.STD_LOGIC_UNSIGNED.ALL;`
68
69			`-- Uncomment the following lines to use the declarations that are`
70			`-- provided for instantiating Xilinx primitive components.`
71			`--library UNISIM;`
72			`--use UNISIM.VComponents.all;`
73
74			`entity RSACypher is`
75			`Generic (KEYSIZE: integer := 32);`
76			`Port (indata: in std_logic_vector(KEYSIZE-1 downto 0);`
77			`inExp: in std_logic_vector(KEYSIZE-1 downto 0);`
78			`inMod: in std_logic_vector(KEYSIZE-1 downto 0);`
79			`cypher: out std_logic_vector(KEYSIZE-1 downto 0);`
80			`clk: in std_logic;`
81			`ds: in std_logic;`
82			`reset: in std_logic;`
83			`ready: out std_logic`
84			`);`
85			`end RSACypher;`
86
87			`architecture Behavioral of RSACypher is`
88			`attribute keep: string;`
89
90			`component modmult is`
91			`Generic (MPWID: integer);`
92			`Port ( mpand : in std_logic_vector(MPWID-1 downto 0);`
93			`mplier : in std_logic_vector(MPWID-1 downto 0);`
94			`modulus : in std_logic_vector(MPWID-1 downto 0);`
95			`product : out std_logic_vector(MPWID-1 downto 0);`
96			`clk : in std_logic;`
97			`ds : in std_logic;`
98			`reset : in std_logic;`
99			`ready: out std_logic);`
100			`end component;`
101
102			`signal modreg: std_logic_vector(KEYSIZE-1 downto 0); -- store the modulus value during operation`
103			`signal root: std_logic_vector(KEYSIZE-1 downto 0); -- value to be squared`
104			`signal square: std_logic_vector(KEYSIZE-1 downto 0); -- result of square operation`
105			`signal sqrin: std_logic_vector(KEYSIZE-1 downto 0); -- 1 or copy of root`
106			`signal tempin: std_logic_vector(KEYSIZE-1 downto 0); -- 1 or copy of square`
107			`signal tempout: std_logic_vector(KEYSIZE-1 downto 0); -- result of multiplication`
108			`signal count: std_logic_vector(KEYSIZE-1 downto 0); -- working copy of exponent`
109
110			`signal multrdy, sqrrdy, bothrdy: std_logic; -- signals to indicate completion of multiplications`
111			`signal multgo, sqrgo: std_logic; -- signals to trigger start of multiplications`
112			`signal done: std_logic; -- signal to indicate encryption complete`
113
114			`-- The following attributes can be set to make signal tracing easier`
115
116			`--attribute keep of multrdy: signal is "true";`
117			`--attribute keep of sqrrdy: signal is "true";`
118			`--attribute keep of bothrdy: signal is "true";`
119			`--attribute keep of multgo: signal is "true";`
120			`--attribute keep of sqrgo: signal is "true";`
121
122
123			`begin`
124
125			`ready <= done;`
126			`bothrdy <= multrdy and sqrrdy;`
127
128			`-- Modular multiplier to produce products`
129			`modmultiply: modmult`
130			`Generic Map(MPWID => KEYSIZE)`
131			`Port Map(mpand => tempin,`
132			`mplier => sqrin,`
133			`modulus => modreg,`
134			`product => tempout,`
135			`clk => clk,`
136			`ds => multgo,`
137			`reset => reset,`
138			`ready => multrdy);`
139
140			`-- Modular multiplier to take care of squaring operations`
141			`modsqr: modmult`
142			`Generic Map(MPWID => KEYSIZE)`
143			`Port Map(mpand => root,`
144			`mplier => root,`
145			`modulus => modreg,`
146			`product => square,`
147			`clk => clk,`
148			`ds => multgo,`
149			`reset => reset,`
150			`ready =>sqrrdy);`
151
152			`--counter manager process tracks counter and enable flags`
153			`mngcount: process (clk, reset, done, ds, count, bothrdy) is`
154			`begin`
155			`-- handles DONE and COUNT signals`
156
157			`if reset = '1' then`
158			`count <= (others => '0');`
159			`done <= '1';`
160			`elsif rising_edge(clk) then`
161			`if done = '1' then`
162			`if ds = '1' then`
163			`-- first time through`
164			`count <= '0' & inExp(KEYSIZE-1 downto 1);`
165			`done <= '0';`
166			`end if;`
167			`-- after first time`
168			`elsif count = 0 then`
169			`if bothrdy = '1' and multgo = '0' then`
170			`cypher <= tempout; -- set output value`
171			`done <= '1';`
172			`end if;`
173			`elsif bothrdy = '1' then`
174			`if multgo = '0' then`
175			`count <= '0' & count(KEYSIZE-1 downto 1);`
176			`end if;`
177			`end if;`
178			`end if;`
179
180			`end process mngcount;`
181
182			`-- This process sets the input values for the squaring multitplier`
183			`setupsqr: process (clk, reset, done, ds) is`
184			`begin`
185
186			`if reset = '1' then`
187			`root <= (others => '0');`
188			`modreg <= (others => '0');`
189			`elsif rising_edge(clk) then`
190			`if done = '1' then`
191			`if ds = '1' then`
192			`-- first time through, input is sampled only once`
193			`modreg <= inMod;`
194			`root <= indata;`
195			`end if;`
196			`-- after first time, square result is fed back to multiplier`
197			`else`
198			`root <= square;`
199			`end if;`
200			`end if;`
201
202			`end process setupsqr;`
203
204			`-- This process sets input values for the product multiplier`
205			`setupmult: process (clk, reset, done, ds) is`
206			`begin`
207
208			`if reset = '1' then`
209			`tempin <= (others => '0');`
210			`sqrin <= (others => '0');`
211			`modreg <= (others => '0');`
212			`elsif rising_edge(clk) then`
213			`if done = '1' then`
214			`if ds = '1' then`
215			`-- first time through, input is sampled only once`
216			`-- if the least significant bit of the exponent is '1' then we seed the`
217			`-- multiplier with the message value. Otherwise, we seed it with 1.`
218			`-- The square is set to 1, so the result of the first multiplication will be`
219			`-- either 1 or the initial message value`
220			`if inExp(0) = '1' then`
221			`tempin <= indata;`
222			`else`
223			`tempin(KEYSIZE-1 downto 1) <= (others => '0');`
224			`tempin(0) <= '1';`
225			`end if;`
226			`modreg <= inMod;`
227			`sqrin(KEYSIZE-1 downto 1) <= (others => '0');`
228			`sqrin(0) <= '1';`
229			`end if;`
230			`-- after first time, the multiplication and square results are fed back through the multiplier.`
231			`-- The counter (exponent) has been shifted one bit to the right`
232			`-- If the least significant bit of the exponent is '1' the result of the most recent`
233			`-- squaring operation is fed to the multiplier.`
234			`-- Otherwise, the square value is set to 1 to indicate no multiplication.`
235			`else`
236			`tempin <= tempout;`
237			`if count(0) = '1' then`
238			`sqrin <= square;`
239			`else`
240			`sqrin(KEYSIZE-1 downto 1) <= (others => '0');`
241			`sqrin(0) <= '1';`
242			`end if;`
243			`end if;`
244			`end if;`
245
246			`end process setupmult;`
247
248			`-- this process enables the multipliers when it is safe to do so`
249			`crypto: process (clk, reset, done, ds, count, bothrdy) is`
250			`begin`
251
252			`if reset = '1' then`
253			`multgo <= '0';`
254			`elsif rising_edge(clk) then`
255			`if done = '1' then`
256			`if ds = '1' then`
257			`-- first time through - automatically trigger first multiplier cycle`
258			`multgo <= '1';`
259			`end if;`
260			`-- after first time, trigger multipliers when both operations are complete`
261			`elsif count /= 0 then`
262			`if bothrdy = '1' then`
263			`multgo <= '1';`
264			`end if;`
265			`end if;`
266			`-- when multipliers have been started, disable multiplier inputs`
267			`if multgo = '1' then`
268			`multgo <= '0';`
269			`end if;`
270			`end if;`
271
272			`end process crypto;`
273
274			`end Behavioral;`