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# FPz8 - An open-source VHDL implementation of the Zilog Z8 encore
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FPz8 mk1 v0.99
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Version: 0.99 Nov, 24th, 2016 (changed LDWX instruction, interrupts, condition code function, debugger command processor)
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Version: 0.91 Nov, 15th, 2016
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Version: 0.9 Nov, 11th, 2016
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FPz8 is a softcore almost 100% object-code compatible with the Z8 encore microcontroller line. Current implementation includes
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2kb of file registers (RAM), 16kb of program memory (using FPGA RAM), 8 vectored interrupts with programmable priority,
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full-featured onchip debugger 100% compatible with Zilog's OCD and ZDS-II IDE.
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It was designed to work as a SoC and everything (except the USB chip) fits inside a single FPGA (I have used an Altera
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Cyclone IV EP4CE6 device). The debugger connection makes use of a serial-to-USB chip (it is part of the low-cost FPGA
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board used on the project).
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In a near future I plan to add some more features to the device (such as a timer and maybe other peripherals).
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The idea behind the FPz8 was to learn more on VHDL and FPGAs (this is my second design using these technologies). I also
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believe FPz8 can be a very interesting tool for learning/teaching VHDL, computing and microprocessors/microcontrollers
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programming.
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You are free to use and to modify FPz8 to fit your needs, except for comercial use (I don't expect anyone would do that anyway).
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If you want to contribute to the project, contact me and share your thoughts.
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Don't forget to credit the author!
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Note: currently there are only a few SFRs physically implemented, they are:
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0xFC0 - IRQ0
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0xFC1 - IRQ0ENH
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0xFC2 - IRQ0ENL
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0xFCF - IRQCTL
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0xFD2 - PAIN
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0xFD3 - PAOUT
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0xFF8 - FCTL
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0xFFC - FLAGS
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0xFFD - RP
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0xFFE - SPH
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0xFFF - SPL
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What else is missing from the original architecture?
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A: no watchdog (WDT instruction runs as a NOP), no LDE and LDEI instructions (data memory related), no option bytes,
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no data memory related debug commands, no CRC debug command, no ID bytes
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FPz8 was tested on an EP4CE6 mini board (50MHz clock)
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http://www.ebay.com/itm/EP4CE6-Mini-Board-USB-Blaster-Altera-Cyclone-IV-FPGA-CPLD-Nano-Size-
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fabiop |
This work is licensed under the Creative Commons Attribution 4.0 International License.
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To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/.
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