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[/] [RISCMCU/] [trunk/] [vhdl/] [v_extint.vhd] - Blame information for rev 28

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1 8 yapzihe
----------------------------------------------------------------------------
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----                                                                    ----
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---- WISHBONE RISCMCU IP Core                                           ----
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----                                                                    ----
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---- This file is part of the RISCMCU project                           ----
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---- http://www.opencores.org/projects/riscmcu/                         ----
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----                                                                    ----
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---- Description                                                        ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR        ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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----                                                                    ----
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---- Author(s):                                                         ----
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----    - Yap Zi He, yapzihe@hotmail.com                                ----
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----                                                                    ----
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----------------------------------------------------------------------------
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----                                                                    ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG                       ----
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----                                                                    ----
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---- This source file may be used and distributed without               ----
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---- restriction provided that this copyright statement is not          ----
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---- removed from the file and that any derivative work contains        ----
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---- the original copyright notice and the associated disclaimer.       ----
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----                                                                    ----
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---- This source file is free software; you can redistribute it         ----
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---- and/or modify it under the terms of the GNU Lesser General         ----
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---- Public License as published by the Free Software Foundation;       ----
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---- either version 2.1 of the License, or (at your option) any         ----
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---- later version.                                                     ----
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----                                                                    ----
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---- This source is distributed in the hope that it will be             ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
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---- PURPOSE. See the GNU Lesser General Public License for more        ----
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---- details.                                                           ----
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----                                                                    ----
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---- You should have received a copy of the GNU Lesser General          ----
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---- Public License along with this source; if not, download it         ----
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---- from http://www.opencores.org/lgpl.shtml                           ----
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----                                                                    ----
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity v_extint is
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 port(  clk, clrn, extpin, clr_intf : in std_logic;
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                rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic;
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                extirq  : out std_logic;
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                c : inout std_logic_vector(7 downto 0));
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end v_extint;
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architecture extint of v_extint is
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signal int0, flag, currentstate, laststate : std_logic;
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signal isc0 : integer range 0 to 3;
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begin
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c <= "000000" & conv_std_logic_vector(isc0,2)   when rd_mcucr = '1' else
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         '0' & int0 & "000000"                                           when rd_gimsk = '1' else
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         "ZZZZZZZZ";
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extirq <=       int0 and not extpin when isc0 = 0 else
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                        int0 and flag;
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process(clk, clrn)
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begin
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        if clrn = '0' then
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                int0 <= '0';
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                isc0 <= 0;
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                currentstate <= '0';
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                laststate <= '0';
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        elsif clk'event and clk = '1' then
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                if wr_gimsk = '1' then
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                        int0 <= c(6);
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                end if;
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                if wr_mcucr = '1' then
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                        isc0 <= conv_integer(c(1 downto 0));
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                end if;
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                currentstate <= extpin;
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                laststate <= currentstate;
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        end if;
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end process;
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process(clrn, clr_intf, clk, isc0, currentstate)
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begin
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        if clrn = '0' or clr_intf = '1' then
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                flag <= '0';
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        elsif clk'event and clk = '1' then
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                if isc0 = 2 then
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                        if currentstate = '0' and laststate = '1' then
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                                flag <= '1';
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                        end if;
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                elsif isc0 = 3 then
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                        if currentstate = '1' and laststate = '0' then
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                                flag <= '1';
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                        end if;
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                end if;
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        end if;
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end process;
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end extint;

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