| 1 |
8 |
yapzihe |
----------------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- WISHBONE RISCMCU IP Core ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the RISCMCU project ----
|
| 6 |
|
|
---- http://www.opencores.org/projects/riscmcu/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description ----
|
| 9 |
|
|
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
|
| 10 |
|
|
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
|
| 11 |
|
|
---- ----
|
| 12 |
|
|
---- Author(s): ----
|
| 13 |
|
|
---- - Yap Zi He, yapzihe@hotmail.com ----
|
| 14 |
|
|
---- ----
|
| 15 |
|
|
----------------------------------------------------------------------------
|
| 16 |
|
|
---- ----
|
| 17 |
|
|
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
|
| 18 |
|
|
---- ----
|
| 19 |
|
|
---- This source file may be used and distributed without ----
|
| 20 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 21 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 22 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 23 |
|
|
---- ----
|
| 24 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 25 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 26 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 27 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 28 |
|
|
---- later version. ----
|
| 29 |
|
|
---- ----
|
| 30 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 31 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 32 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 33 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 34 |
|
|
---- details. ----
|
| 35 |
|
|
---- ----
|
| 36 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 37 |
|
|
---- Public License along with this source; if not, download it ----
|
| 38 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 39 |
|
|
---- ----
|
| 40 |
|
|
----------------------------------------------------------------------------
|
| 41 |
|
|
|
| 42 |
|
|
library ieee;
|
| 43 |
|
|
use ieee.std_logic_1164.all;
|
| 44 |
|
|
use ieee.std_logic_arith.all;
|
| 45 |
|
|
use ieee.std_logic_unsigned.all;
|
| 46 |
|
|
|
| 47 |
|
|
entity v_extint is
|
| 48 |
|
|
port( clk, clrn, extpin, clr_intf : in std_logic;
|
| 49 |
|
|
rd_mcucr, wr_mcucr, rd_gimsk, wr_gimsk : in std_logic;
|
| 50 |
|
|
extirq : out std_logic;
|
| 51 |
|
|
c : inout std_logic_vector(7 downto 0));
|
| 52 |
|
|
end v_extint;
|
| 53 |
|
|
|
| 54 |
|
|
architecture extint of v_extint is
|
| 55 |
|
|
|
| 56 |
|
|
signal int0, flag, currentstate, laststate : std_logic;
|
| 57 |
|
|
signal isc0 : integer range 0 to 3;
|
| 58 |
|
|
|
| 59 |
|
|
begin
|
| 60 |
|
|
|
| 61 |
|
|
c <= "000000" & conv_std_logic_vector(isc0,2) when rd_mcucr = '1' else
|
| 62 |
|
|
'0' & int0 & "000000" when rd_gimsk = '1' else
|
| 63 |
|
|
"ZZZZZZZZ";
|
| 64 |
|
|
|
| 65 |
|
|
extirq <= int0 and not extpin when isc0 = 0 else
|
| 66 |
|
|
int0 and flag;
|
| 67 |
|
|
|
| 68 |
|
|
process(clk, clrn)
|
| 69 |
|
|
begin
|
| 70 |
|
|
if clrn = '0' then
|
| 71 |
|
|
int0 <= '0';
|
| 72 |
|
|
isc0 <= 0;
|
| 73 |
|
|
currentstate <= '0';
|
| 74 |
|
|
laststate <= '0';
|
| 75 |
|
|
elsif clk'event and clk = '1' then
|
| 76 |
|
|
if wr_gimsk = '1' then
|
| 77 |
|
|
int0 <= c(6);
|
| 78 |
|
|
end if;
|
| 79 |
|
|
if wr_mcucr = '1' then
|
| 80 |
|
|
isc0 <= conv_integer(c(1 downto 0));
|
| 81 |
|
|
end if;
|
| 82 |
|
|
currentstate <= extpin;
|
| 83 |
|
|
laststate <= currentstate;
|
| 84 |
|
|
end if;
|
| 85 |
|
|
end process;
|
| 86 |
|
|
|
| 87 |
|
|
process(clrn, clr_intf, clk, isc0, currentstate)
|
| 88 |
|
|
begin
|
| 89 |
|
|
if clrn = '0' or clr_intf = '1' then
|
| 90 |
|
|
flag <= '0';
|
| 91 |
|
|
elsif clk'event and clk = '1' then
|
| 92 |
|
|
if isc0 = 2 then
|
| 93 |
|
|
if currentstate = '0' and laststate = '1' then
|
| 94 |
|
|
flag <= '1';
|
| 95 |
|
|
end if;
|
| 96 |
|
|
elsif isc0 = 3 then
|
| 97 |
|
|
if currentstate = '1' and laststate = '0' then
|
| 98 |
|
|
flag <= '1';
|
| 99 |
|
|
end if;
|
| 100 |
|
|
end if;
|
| 101 |
|
|
end if;
|
| 102 |
|
|
end process;
|
| 103 |
|
|
|
| 104 |
|
|
end extint;
|
