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[/] [RISCMCU/] [trunk/] [vhdl/] [v_iodecoder.vhd] - Blame information for rev 28

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1 8 yapzihe
----------------------------------------------------------------------------
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----                                                                    ----
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---- WISHBONE RISCMCU IP Core                                           ----
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----                                                                    ----
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---- This file is part of the RISCMCU project                           ----
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---- http://www.opencores.org/projects/riscmcu/                         ----
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----                                                                    ----
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---- Description                                                        ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR        ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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----                                                                    ----
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---- Author(s):                                                         ----
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----    - Yap Zi He, yapzihe@hotmail.com                                ----
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----                                                                    ----
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----------------------------------------------------------------------------
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----                                                                    ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG                       ----
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----                                                                    ----
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---- This source file may be used and distributed without               ----
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---- restriction provided that this copyright statement is not          ----
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---- removed from the file and that any derivative work contains        ----
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---- the original copyright notice and the associated disclaimer.       ----
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----                                                                    ----
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---- This source file is free software; you can redistribute it         ----
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---- and/or modify it under the terms of the GNU Lesser General         ----
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---- Public License as published by the Free Software Foundation;       ----
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---- either version 2.1 of the License, or (at your option) any         ----
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---- later version.                                                     ----
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----                                                                    ----
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---- This source is distributed in the hope that it will be             ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied         ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR            ----
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---- PURPOSE. See the GNU Lesser General Public License for more        ----
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---- details.                                                           ----
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----                                                                    ----
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---- You should have received a copy of the GNU Lesser General          ----
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---- Public License along with this source; if not, download it         ----
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---- from http://www.opencores.org/lgpl.shtml                           ----
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----                                                                    ----
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity v_iodecoder is
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 port(  ioaddr : in integer range 0 to 16#3f#;
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                rd_io, wr_io : in std_logic;
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                rd_sreg, wr_sreg : out std_logic;
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                rd_gimsk, wr_gimsk, rd_timsk, wr_timsk, rd_tifr,wr_tifr : out std_logic;
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                rd_mcucr,wr_mcucr, rd_tccr0, wr_tccr0, rd_tcnt0,wr_tcnt0 : out std_logic;
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                rd_portb, wr_portb, rd_ddrb, wr_ddrb, rd_pinb : out std_logic;
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                rd_portc, wr_portc, rd_ddrc, wr_ddrc, rd_pinc : out std_logic;
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                rd_portd, wr_portd, rd_ddrd, wr_ddrd, rd_pind : out std_logic
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 );
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end v_iodecoder;
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architecture iodecoder of v_iodecoder is
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begin
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process(rd_io, ioaddr)
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begin
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 rd_sreg <= '0';
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 rd_gimsk <= '0';
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 rd_timsk <= '0';
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 rd_tifr <= '0';
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 rd_mcucr <= '0';
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 rd_tccr0 <= '0';
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 rd_tcnt0 <= '0';
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 rd_portb <= '0';
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 rd_ddrb <= '0';
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 rd_pinb <= '0';
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 rd_portc <= '0';
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 rd_ddrc <= '0';
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 rd_pinc <= '0';
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 rd_portd <= '0';
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 rd_ddrd <= '0';
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 rd_pind <= '0';
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 if rd_io = '1' then
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        case ioaddr is
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                when 16#3f# => rd_sreg  <= '1';
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                when 16#3b# => rd_gimsk <= '1';
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                when 16#39# => rd_timsk <= '1';
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                when 16#38# => rd_tifr  <= '1';
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                when 16#35# => rd_mcucr <= '1';
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                when 16#33# => rd_tccr0 <= '1';
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                when 16#32# => rd_tcnt0 <= '1';
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                when 16#18# => rd_portb <= '1';
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                when 16#17# => rd_ddrb  <= '1';
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                when 16#16# => rd_pinb  <= '1';
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                when 16#15# => rd_portc <= '1';
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                when 16#14# => rd_ddrc  <= '1';
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                when 16#13# => rd_pinc  <= '1';
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                when 16#12# => rd_portd <= '1';
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                when 16#11# => rd_ddrd  <= '1';
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                when 16#10# => rd_pind  <= '1';
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                when others =>
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        end case;
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 end if;
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end process;
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process(wr_io, ioaddr)
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begin
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 wr_sreg <= '0';
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 wr_gimsk <= '0';
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 wr_timsk <= '0';
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 wr_tifr <= '0';
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 wr_mcucr <= '0';
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 wr_tccr0 <= '0';
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 wr_tcnt0 <= '0';
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 wr_portb <= '0';
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 wr_ddrb <= '0';
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 wr_portc <= '0';
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 wr_ddrc <= '0';
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 wr_portd <= '0';
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 wr_ddrd <= '0';
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 if wr_io = '1' then
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        case ioaddr is
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                when 16#3f# => wr_sreg  <= '1';
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                when 16#3b# => wr_gimsk <= '1';
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                when 16#39# => wr_timsk <= '1';
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                when 16#38# => wr_tifr  <= '1';
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                when 16#35# => wr_mcucr <= '1';
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                when 16#33# => wr_tccr0 <= '1';
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                when 16#32# => wr_tcnt0 <= '1';
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                when 16#18# => wr_portb <= '1';
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                when 16#17# => wr_ddrb  <= '1';
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                when 16#15# => wr_portc <= '1';
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                when 16#14# => wr_ddrc  <= '1';
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                when 16#12# => wr_portd <= '1';
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                when 16#11# => wr_ddrd  <= '1';
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                when others =>
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        end case;
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 end if;
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end process;
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end iodecoder;

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