| 1 |
8 |
yapzihe |
----------------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- WISHBONE RISCMCU IP Core ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the RISCMCU project ----
|
| 6 |
|
|
---- http://www.opencores.org/projects/riscmcu/ ----
|
| 7 |
|
|
---- ----
|
| 8 |
|
|
---- Description ----
|
| 9 |
|
|
---- Implementation of a RISC Microcontroller based on Atmel AVR ----
|
| 10 |
|
|
---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
|
| 11 |
|
|
---- ----
|
| 12 |
|
|
---- Author(s): ----
|
| 13 |
|
|
---- - Yap Zi He, yapzihe@hotmail.com ----
|
| 14 |
|
|
---- ----
|
| 15 |
|
|
----------------------------------------------------------------------------
|
| 16 |
|
|
---- ----
|
| 17 |
|
|
---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
|
| 18 |
|
|
---- ----
|
| 19 |
|
|
---- This source file may be used and distributed without ----
|
| 20 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 21 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 22 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 23 |
|
|
---- ----
|
| 24 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 25 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 26 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 27 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 28 |
|
|
---- later version. ----
|
| 29 |
|
|
---- ----
|
| 30 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 31 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 32 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 33 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 34 |
|
|
---- details. ----
|
| 35 |
|
|
---- ----
|
| 36 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 37 |
|
|
---- Public License along with this source; if not, download it ----
|
| 38 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 39 |
|
|
---- ----
|
| 40 |
|
|
----------------------------------------------------------------------------
|
| 41 |
|
|
|
| 42 |
|
|
library ieee;
|
| 43 |
|
|
use ieee.std_logic_1164.all;
|
| 44 |
|
|
|
| 45 |
|
|
entity v_port is
|
| 46 |
|
|
port( rd_port, wr_port, rd_ddr, wr_ddr, rd_pin : in std_logic;
|
| 47 |
|
|
clk, clrn : in std_logic;
|
| 48 |
|
|
c : inout std_logic_vector(7 downto 0);
|
| 49 |
|
|
pin : inout std_logic_vector(7 downto 0)
|
| 50 |
|
|
);
|
| 51 |
|
|
end v_port;
|
| 52 |
|
|
|
| 53 |
|
|
architecture ioport of v_port is
|
| 54 |
|
|
|
| 55 |
|
|
component v_port_bit
|
| 56 |
|
|
port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic;
|
| 57 |
|
|
clk,clrn : in std_logic;
|
| 58 |
|
|
c : inout std_logic;
|
| 59 |
|
|
pin : inout std_logic
|
| 60 |
|
|
);
|
| 61 |
|
|
end component;
|
| 62 |
|
|
|
| 63 |
|
|
begin
|
| 64 |
|
|
|
| 65 |
|
|
g1:
|
| 66 |
|
|
for i in 0 to 7 generate
|
| 67 |
|
|
u1 : v_port_bit
|
| 68 |
|
|
port map (rd_port, wr_port, rd_ddr, wr_ddr, rd_pin, clk, clrn, c(i), pin(i));
|
| 69 |
|
|
end generate;
|
| 70 |
|
|
|
| 71 |
|
|
end ioport;
|
