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yapzihe |
----------------------------------------------------------------------------
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---- ----
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---- WISHBONE RISCMCU IP Core ----
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---- ----
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---- This file is part of the RISCMCU project ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- ----
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---- Description ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- ----
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---- Author(s): ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity v_port_bit is
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port( rd_port,wr_port,rd_ddr,wr_ddr,rd_pin : in std_logic;
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clk,clrn : in std_logic;
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c : inout std_logic;
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pin : inout std_logic
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);
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end v_port_bit;
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architecture port_bit of v_port_bit is
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signal datareg, ddr : std_logic;
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begin
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c <= datareg when rd_port = '1' else
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ddr when rd_ddr = '1' else
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pin when rd_pin = '1' else
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'Z';
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pin <= datareg when ddr = '1' else
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'Z';
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process(clrn, clk)
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begin
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if clrn = '0' then
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datareg <= '0';
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ddr <= '0';
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elsif clk'event and clk = '1' then
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if wr_port = '1' then
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datareg <= c;
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end if;
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if wr_ddr = '1' then
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ddr <= c;
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end if;
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end if;
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end process;
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end port_bit;
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