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yapzihe |
----------------------------------------------------------------------------
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---- ----
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---- WISHBONE RISCMCU IP Core ----
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---- ----
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---- This file is part of the RISCMCU project ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- ----
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---- Description ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- ----
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---- Author(s): ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity v_ram is
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port( addrbus : in std_logic_vector(7 downto 0);
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rd_ram, wr_ram, ld_mar, ld_mbr : in std_logic;
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clk, clrn : in std_logic;
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c : inout std_logic_vector(7 downto 0)
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);
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end entity;
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architecture ram of v_ram is
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component lpm_ram_dq
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generic( lpm_width: positive := 8;
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lpm_widthad: positive := 8;
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lpm_numwords: natural := 256;
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lpm_file: string := "ram.mif";
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lpm_indata: string := "unregistered";
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lpm_address_control: string := "unregistered";
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lpm_outdata: string := "unregistered"
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);
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port( data: in std_logic_vector(lpm_width-1 downto 0);
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address: in std_logic_vector(lpm_widthad-1 downto 0);
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we: in std_logic;
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inclock: in std_logic := '0';
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outclock: in std_logic := '0';
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q: out std_logic_vector(lpm_width-1 downto 0)
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);
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end component;
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signal mar, mbr, ram_out : std_logic_vector(7 downto 0);
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begin
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sram: lpm_ram_dq
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port map(data => mbr, address => mar, we => wr_ram, q => ram_out);
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c <= ram_out when rd_ram = '1' else
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"ZZZZZZZZ";
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process(clk,clrn)
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begin
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if clrn = '0' then
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mar <= "00000000";
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mbr <= "00000000";
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elsif clk'event and clk = '1' then
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if ld_mbr = '1' then
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mbr <= c;
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end if;
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if ld_mar = '1' then
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mar <= addrbus;
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end if;
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end if;
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end process;
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end ram;
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