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yapzihe |
----------------------------------------------------------------------------
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---- ----
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---- WISHBONE RISCMCU IP Core ----
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---- ----
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---- This file is part of the RISCMCU project ----
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---- http://www.opencores.org/projects/riscmcu/ ----
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---- ----
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---- Description ----
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---- Implementation of a RISC Microcontroller based on Atmel AVR ----
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---- AT90S1200 instruction set and features with Altera Flex10k20 FPGA. ----
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---- ----
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---- Author(s): ----
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---- - Yap Zi He, yapzihe@hotmail.com ----
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---- ----
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----------------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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entity v_timer is
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port( extpin, clr_tov0 : in std_logic;
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rd_timsk, wr_timsk, rd_tifr, wr_tifr : in std_logic;
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rd_tccr0, wr_tccr0, rd_tcnt0, wr_tcnt0 : in std_logic;
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clk, clrn : in std_logic;
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c : inout std_logic_vector(7 downto 0);
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timerirq : out std_logic
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);
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end v_timer;
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architecture timer of v_timer is
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signal toie0, tov0 : std_logic;
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signal cs : integer range 0 to 7;
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signal tcnt0 : std_logic_vector(7 downto 0);
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signal div1, div2, div4, div8, div16, div32, div64, div128, div256, div512, div1024 : std_logic;
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signal timerclk, inc_tcnt0, currentstate, laststate : std_logic;
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begin
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-- Timer Interrupt Request
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timerirq <= toie0 and tov0;
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-- Read 4 Registers
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c <= "000000" & toie0 & "0" when rd_timsk = '1' else
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"000000" & tov0 & "0" when rd_tifr = '1' else
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conv_std_logic_vector(cs,8) when rd_tccr0 = '1' else
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tcnt0 when rd_tcnt0 = '1' else
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"ZZZZZZZZ";
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-- Select Clock Source
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with cs select
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timerclk <= '0' when 0,
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clk when 1,
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div8 when 2,
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div64 when 3,
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div256 when 4,
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div1024 when 5,
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not extpin when 6,
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extpin when 7;
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-- Timer : clear/write 4 registers, increment timer, set overflow flag, sample clock source
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process(clrn, clr_tov0, wr_tifr, c, clk)
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begin
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if clrn = '0' then
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toie0 <= '0';
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cs <= 0;
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tcnt0 <= "00000000";
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tov0 <= '0';
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currentstate <= '0';
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laststate <= '0';
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elsif clr_tov0 = '1' or (wr_tifr = '1' and c(1) = '1') then
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tov0 <= '0';
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elsif clk'event and clk = '1' then
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if wr_tcnt0 = '1' then
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tcnt0 <= c;
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elsif inc_tcnt0 = '1' then
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tcnt0 <= tcnt0 + 1;
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if tcnt0 = "11111111" then
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tov0 <= '1';
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end if;
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end if;
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if wr_timsk = '1' then
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toie0 <= c(1);
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end if;
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if wr_tccr0 = '1' then
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cs <= conv_integer(c(2 downto 0));
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end if;
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currentstate <= timerclk;
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laststate <= currentstate;
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end if;
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end process;
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-- Detect rising edge
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inc_tcnt0 <= '1' when (laststate ='0' and currentstate = '1') or cs = 1 else
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'0';
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-- 10 bit prescaler
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process(clk, clrn)
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begin
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if clrn = '0' then
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div2 <= '0';
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div4 <= '0';
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div8 <= '0';
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div16 <= '0';
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div32 <= '0';
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div64 <= '0';
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div128 <= '0';
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div256 <= '0';
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div512 <= '0';
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div1024 <= '0';
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elsif clk'event and clk = '1' then
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div2 <= not div2;
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if div2 = '1' then
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div4 <= not div4;
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if div4 = '1' then
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div8 <= not div8;
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if div8 = '1' then
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div16 <= not div16;
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if div16 = '1' then
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div32 <= not div32;
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if div32 = '1' then
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div64 <= not div64;
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if div64 = '1' then
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div128 <= not div128;
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if div128 = '1' then
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div256 <= not div256;
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if div256 = '1' then
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div512 <= not div512;
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if div512 = '1' then
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div1024 <= not div1024;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end timer;
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