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[/] [System09/] [branches/] [mkfiles_rev1/] [rtl/] [VHDL/] [ACIA_TX.vhd] - Blame information for rev 19

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1 19 dilbert57
--===========================================================================--
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--
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--  S Y N T H E Z I A B L E    ACIA 6850   C O R E
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--
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--  www.OpenCores.Org - January 2007
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--  This core adheres to the GNU public license  
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--
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-- Design units   : 6850 ACIA core for the System68/09
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--
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-- File name      : ACIA_TX.vhd
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--
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-- Purpose        : Implements an ACIA device for communication purposes 
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--                  between the FPGA processor and the Host computer through
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--                  a RS-232 communication protocol.
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--                  
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-- Dependencies   : ieee.std_logic_1164
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--                  ieee.numeric_std
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--                  ieee.std_logic_unsigned
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--
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--===========================================================================--
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-------------------------------------------------------------------------------
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-- Revision list
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-- Version  Author        Date                        Changes
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--
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-- 0.1      Ovidiu Lupas  15 January 2000    New model
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-- 2.0      Ovidiu Lupas  17 April   2000    unnecessary variable removed
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--
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-- 3.0      John Kent      5 January 2003    added 6850 word format control
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-- 3.1      John Kent     12 January 2003    Rearranged state machine code
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-- 3.2      John Kent     30 March 2003      Revamped State machine
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-- 3.3      John Kent     16 January 2004    Major re-write - added baud rate gen
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--      4.0      John Kent      3 February 2007   renamed txunit to ACIA_TX
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-- 4.1      John Kent      4 February 2007   Cleaned up transmiter
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-- 4.2      John Kent     25 Februauy 2007   Modify sensitivity lists and
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--                                           split Tx Baud Clock select
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--                                           and edge detection.
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--  dilbert57@opencores.org
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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-------------------------------------------------------------------------------
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-- Entity for the ACIA Transmitter
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-------------------------------------------------------------------------------
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entity ACIA_TX is
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  port (
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     Clk    : in  Std_Logic;                    -- CPU Clock signal
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     TxRst  : in  Std_Logic;                    -- Reset input
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     TxWr   : in  Std_Logic;                    -- Load transmit data
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     TxDin  : in  Std_Logic_Vector(7 downto 0);  -- Transmit data input.
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     WdFmt  : in  Std_Logic_Vector(2 downto 0); -- word format
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     BdFmt  : in  Std_Logic_Vector(1 downto 0); -- baud format
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     TxClk  : in  Std_Logic;                    -- Enable input
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     TxDat  : out Std_Logic;                    -- RS-232 data bit output
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     TxEmp  : out Std_Logic );                  -- Tx buffer empty
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end ACIA_TX; --================== End of entity ==============================--
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-------------------------------------------------------------------------------
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-- Architecture for  ACIA_TX
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-------------------------------------------------------------------------------
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architecture rtl of ACIA_TX is
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  type TxStateType is ( Tx1Stop_State, TxStart_State,
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                        TxData_State, TxParity_State, Tx2Stop_State );
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  -----------------------------------------------------------------------------
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  -- Signals
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  -----------------------------------------------------------------------------
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  signal TxClkDel   : Std_Logic := '0';             -- Delayed Tx Input Clock
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  signal TxClkEdge  : Std_Logic := '0';             -- Tx Input Clock Edge pulse
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  signal TxClkCnt   : Std_Logic_Vector(5 downto 0) := (others => '0'); -- Tx Baud Clock Counter
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  signal TxBdDel    : Std_Logic := '0';             -- Delayed Tx Baud Clock
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  signal TxBdEdge   : Std_Logic := '0';             -- Tx Baud Clock Edge pulse
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  signal TxBdClk    : Std_Logic := '0';             -- Tx Baud Clock
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  signal TxShiftReg : Std_Logic_Vector(7 downto 0) := (others => '0'); -- Transmit shift register
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  signal TxParity   : Std_logic := '0';             -- Parity Bit
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  signal TxBitCount : Std_Logic_Vector(2 downto 0) := (others => '0'); -- Data Bit Counter
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  signal TxReq      : Std_Logic := '0';             -- Request Transmit
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  signal TxAck      : Std_Logic := '0';             -- Transmit Commenced
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  signal TxState    : TxStateType;                                               -- Transmitter state
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begin
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  ---------------------------------------------------------------------
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  -- Transmit Clock Edge Detection
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  -- A falling edge will produce a one clock cycle pulse
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  ---------------------------------------------------------------------
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--  acia_tx_clock_edge : process(Clk, TxRst, TxClk, TxClkDel )
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  acia_tx_clock_edge : process( TxRst, Clk )
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  begin
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    if TxRst = '1' then
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           TxClkDel  <= '0';
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                TxClkEdge <= '0';
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         elsif Clk'event and Clk = '0' then
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           TxClkDel  <= TxClk;
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                TxClkEdge <= TxClkDel and (not TxClk);
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         end if;
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  end process;
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  ---------------------------------------------------------------------
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  -- Transmit Clock Divider
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  -- Advance the count only on an input clock pulse
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  ---------------------------------------------------------------------
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--  acia_tx_clock_divide : process( Clk, TxRst, TxClkEdge, TxClkCnt )
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  acia_tx_clock_divide : process( TxRst, Clk )
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  begin
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    if TxRst = '1' then
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           TxClkCnt <= "000000";
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         elsif Clk'event and Clk = '0' then
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           if TxClkEdge = '1' then
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                  TxClkCnt <= TxClkCnt + "000001";
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      end if; -- TxClkEdge
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         end if;        -- reset / clk
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  end process;
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  ---------------------------------------------------------------------
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  -- Transmit Baud Clock Selector
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  ---------------------------------------------------------------------
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  acia_tx_baud_clock_select : process( BdFmt, TxClk, TxClkCnt )
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  begin
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  -- BdFmt
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  -- 0 0     - Baud Clk divide by 1
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  -- 0 1     - Baud Clk divide by 16
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  -- 1 0     - Baud Clk divide by 64
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  -- 1 1     - reset
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    case BdFmt is
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         when "00" =>     -- Div by 1
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           TxBdClk <= TxClk;
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         when "01" =>     -- Div by 16
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           TxBdClk <= TxClkCnt(3);
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         when "10" =>     -- Div by 64
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           TxBdClk <= TxClkCnt(5);
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         when others =>  -- reset
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           TxBdClk <= '0';
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    end case;
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  end process;
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146
  ---------------------------------------------------------------------
147
  -- Transmit Baud Clock Edge Detector
148
  ---------------------------------------------------------------------
149
  --
150
  -- Generate one clock pulse strobe on falling edge of Tx Baud Clock
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  --
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--  acia_tx_baud_clock_edge : process(Clk, TxRst, TxBdClk, TxBdDel )
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  acia_tx_baud_clock_edge : process( TxRst, Clk )
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  begin
155
    if TxRst = '1' then
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           TxBdDel  <= '0';
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                TxBdEdge <= '0';
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         elsif Clk'event and Clk = '0' then
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           TxBdDel  <= TxBdClk;
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                TxBdEdge <= (not TxBdClk) and TxBdDel;
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         end if;
162
  end process;
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  ---------------------------------------------------------------------
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  -- Transmitter activation process
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  ---------------------------------------------------------------------
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--  acia_tx_write : process(Clk, TxRst, TxWr, TxReq, TxAck )
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  acia_tx_write : process( TxRst, Clk )
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  begin
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     if TxRst = '1' then
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       TxReq <= '0';
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       TxEmp <= '1';
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     elsif Clk'event and Clk = '0' then
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                 if TxWr = '1' then
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         -- Write requests transmit
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                        -- and clears the Empty Flag 
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                        TxReq <= '1';
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              TxEmp <= '0';
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            else
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         if (TxReq = '1') and (TxAck = '1') then
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                          -- Once the transmitter is started 
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                          -- We can clear request.
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           TxReq <= '0';
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                   elsif (TxReq = '0') and (TxAck = '0') then
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                          -- When the transmitter is finished
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                          -- We can flag transmit empty
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                          TxEmp <= '1';
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                   end if;
190
                end if;
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    end if; -- clk / reset
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  end process;
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  -----------------------------------------------------------------------------
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  -- Implements the Tx unit
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  -----------------------------------------------------------------------------
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  -- WdFmt - Bits[4..2]
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  -- 0 0 0   - 7 data, even parity, 2 stop
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  -- 0 0 1   - 7 data, odd  parity, 2 stop
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  -- 0 1 0   - 7 data, even parity, 1 stop
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  -- 0 1 1   - 7 data, odd  parity, 1 stop
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  -- 1 0 0   - 8 data, no   parity, 2 stop
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  -- 1 0 1   - 8 data, no   parity, 1 stop
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  -- 1 1 0   - 8 data, even parity, 1 stop
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  -- 1 1 1   - 8 data, odd  parity, 1 stop
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--  acia_tx_transmit :  process(TxRst, Clk, TxState, TxDin, WdFmt,  
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--                              TxShiftReg, TxBdEdge, TxParity, TxBitCount,
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--                                   TxReq, TxAck )
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  acia_tx_transmit :  process( TxRst, Clk )
210
  begin
211
         if TxRst = '1' then
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          TxDat      <= '1';
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               TxShiftReg <= "00000000";
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                    TxParity   <= '0';
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                    TxBitCount <= "000";
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          TxAck      <= '0';
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                    TxState    <= Tx1Stop_State;
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    elsif Clk'event and Clk = '0' then
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      if TxBdEdge = '1' then
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        case TxState is
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        when Tx1Stop_State =>           -- Last Stop bit state
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          TxDat <= '1';
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          TxAck <= '0';                                 -- Transmitter halted
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                    if TxReq = '1' then
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             TxState <= TxStart_State;
226
                    end if;
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228
        when TxStart_State =>
229
          TxDat      <= '0';            -- Start bit
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               TxShiftReg <= TxDin;                 -- Load Shift reg with Tx Data
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                    TxParity   <= '0';
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                    if WdFmt(2) = '0' then
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                      TxBitCount <= "110";       -- 7 data + parity
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               else
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            TxBitCount <= "111";       -- 8 data
236
               end if;
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          TxAck      <= '1';                             -- Flag transmit started
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          TxState    <= TxData_State;
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        when TxData_State =>
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          TxDat       <= TxShiftReg(0);
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          TxShiftReg  <= '1' & TxShiftReg(7 downto 1);
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          TxParity    <= TxParity xor TxShiftReg(0);
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                    TxBitCount  <= TxBitCount - "001";
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                    if TxBitCount = "000" then
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                 if (WdFmt(2) = '1') and (WdFmt(1) = '0') then
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                             if WdFmt(0) = '0' then          -- 8 data bits
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                TxState <= Tx2Stop_State;     -- 2 stops
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                             else
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                                    TxState <= Tx1Stop_State;     -- 1 stop
251
                        end if;
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                      else
253
                             TxState <= TxParity_State;      -- parity
254
                      end if;
255
                    end if;
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        when TxParity_State =>                -- 7/8 data + parity bit
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               if WdFmt(0) = '0' then
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                            TxDat <= not( TxParity );        -- even parity
260
                    else
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                            TxDat <= TxParity;               -- odd parity
262
               end if;
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                    if WdFmt(1) = '0' then
264
                           TxState <= Tx2Stop_State;         -- 2 stops
265
                    else
266
                           TxState <= Tx1Stop_State;         -- 1 stop
267
                    end if;
268
 
269
        when Tx2Stop_State =>                 -- first of two stop bits
270
          TxDat   <= '1';
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                    TxState <= Tx1Stop_State;
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273
        when others =>  -- Undefined
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          TxDat   <= '1';
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          TxState <= Tx1Stop_State;
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277
        end case; -- TxState
278
 
279
                end if; -- TxBdEdge
280
         end if;         -- clk / reset
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282
  end process;
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end rtl; --=================== End of architecture ====================--

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