OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [branches/] [mkfiles_rev1/] [rtl/] [VHDL/] [BaudClock.vhd] - Blame information for rev 95

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57
-----------------------------------------------------------------
2
--
3
-- ACIA Clock Divider for System09
4
--
5
-----------------------------------------------------------------
6
library ieee;
7
   use ieee.std_logic_1164.all;
8
   use IEEE.STD_LOGIC_ARITH.ALL;
9
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
10
   use ieee.numeric_std.all;
11
library unisim;
12
        use unisim.vcomponents.all;
13
 
14
entity ACIA_Clock is
15
  generic (
16
     SYS_Clock_Frequency  : integer;
17
          BAUD_Clock_Frequency : integer
18
  );
19
  port(
20
    clk      : in  Std_Logic;  -- System Clock input
21
         ACIA_Clk : out Std_Logic   -- ACIA Clock output
22
  );
23
end ACIA_Clock;
24
 
25
-------------------------------------------------------------------------------
26
-- Architecture for ACIA_Clock
27
-------------------------------------------------------------------------------
28
architecture rtl of ACIA_Clock is
29
 
30
constant full_cycle : integer :=  (SYS_Clock_Frequency / BAUD_Clock_Frequency) - 1;
31
constant half_cycle : integer :=  (full_cycle / 2) - 1;
32
--
33
-- Baud Rate Clock Divider
34
--
35
-- 25MHz / 27  = 926,000 KHz = 57,870Bd * 16
36
-- 50MHz / 54  = 926,000 KHz = 57,870Bd * 16
37
--
38
my_baud_clock: process( SysClk )
39
begin
40
    if(SysClk'event and SysClk = '0') then
41
                if( BaudCount = 53 )    then
42
                        baudclk <= '0';
43
                   BaudCount <= "000000";
44
                else
45
                   if( BaudCount = 26 ) then
46
                                baudclk <='1';
47
                        else
48
                                baudclk <=baudclk;
49
                        end if;
50
                   BaudCount <= BaudCount + 1;
51
                end if;
52
    end if;
53
end process;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.