OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [branches/] [mkfiles_rev1/] [rtl/] [VHDL/] [cpu09.vhd] - Blame information for rev 162

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 22 dilbert57
-- $Id: cpu09.vhd,v 1.2 2008-03-14 15:52:46 dilbert57 Exp $
2 19 dilbert57
--===========================================================================----
3
--
4
--  S Y N T H E Z I A B L E    CPU09 - 6809 compatible CPU Core
5
--
6
--  www.OpenCores.Org - September 2003
7
--  This core adheres to the GNU public license  
8
--
9
-- File name      : cpu09.vhd
10
--
11
-- Purpose        : 6809 CPU core
12
--
13
-- Dependencies   : ieee.Std_Logic_1164
14
--                  ieee.std_logic_unsigned
15
--
16
-- Uses           : None
17
--
18
-- Author         : John E. Kent
19
--                  dilbert57@opencores.org      
20
--
21
--===========================================================================----
22
--
23
-- Revision History:
24
--===========================================================================--
25
--
26
-- Version 0.1 - 26 June 2003 - John Kent
27
-- Added extra level in state stack
28
-- fixed some calls to the extended addressing state
29
--
30
-- Version 0.2 - 5 Sept 2003 - John Kent
31
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
32
-- Added/Fixed STY and STS instructions.
33
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
34
-- CMPX Loaded ACCA and ACCB - Now fixed 
35
--
36
-- Version 1.0 - 6 Sep 2003 - John Kent 
37
-- Initial release to Open Cores
38
-- reversed clock edge
39
--
40
-- Version 1.1 - 29 November 2003 John kent
41
--      ACCA and ACCB indexed offsets are 2's complement.
42
-- ALU Right Mux now sign extends ACCA & ACCB offsets
43
-- Absolute Indirect addressing performed a read on the
44
-- second byte of the address rather than a fetch
45
-- so it formed an incorrect address. Now fixed. 
46
--
47
-- Version 1.2 - 29 November 2003 John Kent
48
-- LEAX and LEAY affect the Z bit only
49
--      LEAS and LEAU do not affect any condition codes
50
-- added an extra ALU control for LEA.
51
--
52
-- Version 1.3 - 12 December 2003 John Kent
53
-- CWAI did not work, was missed a PUSH_ST on calling
54
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
55
-- finding this fault.
56
--
57
-- Version 1.4 - 12 December 2003 John Kent
58
-- Missing cc_ctrl assignment in otherwise case of 
59
-- lea_state resulted in cc_ctrl being latched in
60
-- that state.  
61
-- The otherwise statement should never be reached,
62
-- and has been fixed simply to resolve synthesis warnings.
63
--
64
-- Version 1.5 - 17 january 2004 John kent
65
-- The clear instruction used "alu_ld8" to control the ALU
66
-- rather than "alu_clr". This mean the Carry was not being
67
-- cleared correctly.
68
--
69
-- Version 1.6 - 24 January 2004 John Kent
70
-- Fixed problems in PSHU instruction
71
--
72
-- Version 1.7 - 25 January 2004 John Kent
73
-- removed redundant "alu_inx" and "alu_dex'
74
-- Removed "test_alu" and "test_cc"
75
-- STD instruction did not set condition codes
76
-- JMP direct was not decoded properly
77
-- CLR direct performed an unwanted read cycle
78
-- Bogus "latch_md" in Page2 indexed addressing
79
--
80
-- Version 1.8 - 27 January 2004 John Kent
81
-- CWAI in decode1_state should increment the PC.
82
-- ABX is supposed to be an unsigned addition.
83
-- Added extra ALU function
84
-- ASR8 slightly changed in the ALU.
85
--
86
--      Version 1.9 - 20 August 2005
87
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
88
-- rather than LSR16. There was a problem with single 
89
-- operand instructions using the MD register which is
90
-- sign extended on the first 8 bit fetch.
91
--
92
-- Version 1.10 - 13 September 2005
93
-- TFR & EXG instructions did not work for the Condition Code Register
94
-- An extra case has been added to the ALU for the alu_tfr control 
95
-- to assign the left ALU input (alu_left) to the condition code
96
-- outputs (cc_out). 
97
--
98
-- Version 1.11 - 16 September 2005
99
-- JSR ,X should not predecrement S before calculating the jump address.
100
-- The reason is that JSR [0,S] needs S to point to the top of the stack
101
-- to fetch a valid vector address. The solution is to have the addressing
102
-- mode microcode called before decrementing S and then decrementing S in
103
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
104
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
105
-- pushed on the stack. This adds one extra bus cycle, but resolves the
106
-- addressing conflict. I've also removed the pre-decement S in 
107
-- JSR EXTENDED as it also calls JSR_STATE.
108
--
109
-- Version 1.12 - 6th June 2006
110
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
111
-- This is different to the 6800. CLR should reset the V bit.
112
--
113
-- Version 1.13 - 7th July 2006
114
-- Disable NMI on reset until S Stack pointer has been loaded.
115
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
116
--
117
-- Version 1.14 - 11th July 2006
118
-- 1. Added new state to RTI called rti_entire_state.
119
-- This state tests the CC register after it has been loaded
120
-- from the stack. Previously the current CC was tested which
121
-- was incorrect. The Entire Flag should be set before the
122
-- interrupt stacks the CC.
123
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
124
-- which was an enumerated state, but not defined anywhere.
125
-- rti_state has been changed to rti_cc_state so that bogus interrupt
126
-- will perform an RTI after entering that state.
127
-- 3. Sync should generate an interrupt if the interrupt masks
128
-- are cleared. If the interrupt masks are set, then an interrupt
129
-- will cause the the PC to advance to the next instruction.
130
-- Note that I don't wait for an interrupt to be asserted for
131
-- three clock cycles.
132
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
133
-- the Multiply instruction replacing "alu_add16". This is similar 
134
-- to "alu_add16" except it sets the Carry bit to B7 of the result
135
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
136
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
137
-- flags. The logic was re-arranged so that it adds md or zero so 
138
-- that the Carry condition code is set on zero multiplicands.
139
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
140
-- and Zero Flags. It will also affect the Overflow (V) flag although
141
-- the operation is undefined. It's anyones guess what DAA does to V.
142
--
143
-- Version 1.15 - 25th Feb 2007 - John Kent
144
-- line 9672 changed "if Halt <= '1' then" to "if Halt = '1' then"
145
-- Changed sensitivity lists.
146
--
147 22 dilbert57
-- Version 1.16 - 5th February 2008 - John Kent
148
-- FIRQ interrupts should take priority over IRQ Interrupts.
149
-- This presumably means they should be tested for before IRQ
150
-- when they happen concurrently.
151
--
152
-- Version 1.17 - 18th February 2008 - John Kent
153
-- NMI in CWAI should mask IRQ and FIRQ interrupts
154
--
155
-- Version 1.18 - 21st February 2008 - John Kent
156
-- Removed default register settings in each case statement
157
-- and placed them at the beginning of the state sequencer.
158
-- Modified the SYNC instruction so that the interrupt vector(iv)
159
-- is not set unless an unmasked FIRQ or IRQ is received.
160
--
161
-- Version 1.19 - 25th February 2008 - John Kent
162
-- Enumerated separate states for FIRQ/FAST and NMIIRQ/ENTIRE
163
-- Enumerated separate states for MASKI and MASKIF states
164
-- Removed code on BSR/JSR in fetch cycle
165
--
166 19 dilbert57
library ieee;
167
use ieee.std_logic_1164.all;
168
use ieee.std_logic_unsigned.all;
169
 
170
entity cpu09 is
171
        port (
172
                clk:        in  std_logic;
173
                rst:        in  std_logic;
174
                rw:         out std_logic;
175
                vma:        out std_logic;
176
                address:         out std_logic_vector(15 downto 0);
177
           data_in:      in  std_logic_vector(7 downto 0);
178
           data_out: out std_logic_vector(7 downto 0);
179
                halt:     in  std_logic;
180
                hold:     in  std_logic;
181
                irq:      in  std_logic;
182
                firq:     in  std_logic;
183
                nmi:      in  std_logic
184
                );
185
end cpu09;
186
 
187
architecture rtl of cpu09 is
188
 
189
  constant EBIT : integer := 7;
190
  constant FBIT : integer := 6;
191
  constant HBIT : integer := 5;
192
  constant IBIT : integer := 4;
193
  constant NBIT : integer := 3;
194
  constant ZBIT : integer := 2;
195
  constant VBIT : integer := 1;
196
  constant CBIT : integer := 0;
197
 
198
  --
199
  -- Interrupt vector modifiers
200
  --
201
  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
202
  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
203
  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
204
  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
205
  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
206
  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
207
  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
208
  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
209
 
210
        type state_type is (-- Start off in Reset
211
                            reset_state,
212
                                                          -- Fetch Interrupt Vectors (including reset)
213
                                                          vect_lo_state, vect_hi_state,
214
                       -- Fetch Instruction Cycle
215
                       fetch_state,
216
                                                          -- Decode Instruction Cycles
217
                       decode1_state, decode2_state, decode3_state,
218
                                                          -- Calculate Effective Address
219
                                                     imm16_state,
220
                                 indexed_state, index8_state, index16_state, index16_2_state,
221
                                                          pcrel8_state, pcrel16_state, pcrel16_2_state,
222
                                                          indexaddr_state, indexaddr2_state,
223
                                                     postincr1_state, postincr2_state,
224
                                                          indirect_state, indirect2_state, indirect3_state,
225
                       extended_state,
226
                                                          -- single ops
227
                                                          single_op_read_state,
228
                                                     single_op_exec_state,
229
                            single_op_write_state,
230
                                                          -- Dual op states
231
                                                          dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
232
                                                     dual_op_write8_state, dual_op_write16_state,
233
                       -- 
234
                                                     sync_state, halt_state, error_state,
235
                                                          --
236
                                                          andcc_state, orcc_state,
237
                                                          tfr_state, exg_state, exg1_state,
238
                                                          lea_state,
239
                                                          -- Multiplication
240
                                                     mul_state, mulea_state, muld_state,
241
                                                     mul0_state, mul1_state, mul2_state, mul3_state,
242
                                                     mul4_state, mul5_state, mul6_state, mul7_state,
243
                                                          --  Branches
244
                                                          lbranch_state, sbranch_state,
245
                                                          -- Jumps, Subroutine Calls and Returns
246
                       jsr_state, jmp_state,
247
                       push_return_hi_state, push_return_lo_state,
248
                       pull_return_hi_state, pull_return_lo_state,
249
                                                          -- Interrupt cycles
250 22 dilbert57
                                                          int_nmiirq_state, int_firq_state,
251
                                                          int_entire_state, int_fast_state,
252 19 dilbert57
                                                          int_pcl_state,  int_pch_state,
253
                                                     int_upl_state,  int_uph_state,
254
                                                     int_iyl_state,  int_iyh_state,
255
                                                     int_ixl_state,  int_ixh_state,
256 22 dilbert57
                                                     int_dp_state,
257
                                           int_accb_state, int_acca_state,
258 19 dilbert57
                                                     int_cc_state,
259 22 dilbert57
                                                     int_cwai_state,
260
                                                          int_maski_state, int_maskif_state,
261 19 dilbert57
                                                          -- Return From Interrupt
262
                                                     rti_cc_state,   rti_entire_state,
263
                                                          rti_acca_state, rti_accb_state,
264
                                                     rti_dp_state,
265
                                                     rti_ixl_state,  rti_ixh_state,
266
                                                     rti_iyl_state,  rti_iyh_state,
267
                                                     rti_upl_state,  rti_uph_state,
268
                                                     rti_pcl_state,  rti_pch_state,
269
                                                          -- Push Registers using SP
270
                                                          pshs_state,
271
                                                     pshs_pcl_state,  pshs_pch_state,
272
                                                     pshs_upl_state,  pshs_uph_state,
273
                                                     pshs_iyl_state,  pshs_iyh_state,
274
                                                     pshs_ixl_state,  pshs_ixh_state,
275
                                                     pshs_dp_state,
276
                                                     pshs_acca_state, pshs_accb_state,
277
                                                     pshs_cc_state,
278
                                                          -- Pull Registers using SP
279
                                                          puls_state,
280
                                                          puls_cc_state,
281
                                                          puls_acca_state, puls_accb_state,
282
                                                          puls_dp_state,
283
                                                     puls_ixl_state,  puls_ixh_state,
284
                                                     puls_iyl_state,  puls_iyh_state,
285
                                                     puls_upl_state,  puls_uph_state,
286
                                                     puls_pcl_state,  puls_pch_state,
287
                                                          -- Push Registers using UP
288
                                                          pshu_state,
289
                                                     pshu_pcl_state,  pshu_pch_state,
290
                                                     pshu_spl_state,  pshu_sph_state,
291
                                                     pshu_iyl_state,  pshu_iyh_state,
292
                                                     pshu_ixl_state,  pshu_ixh_state,
293
                                                     pshu_dp_state,
294
                                                     pshu_acca_state, pshu_accb_state,
295
                                                     pshu_cc_state,
296
                                                          -- Pull Registers using UP
297
                                                          pulu_state,
298
                                                          pulu_cc_state,
299
                                                          pulu_acca_state, pulu_accb_state,
300
                                                          pulu_dp_state,
301
                                                     pulu_ixl_state,  pulu_ixh_state,
302
                                                     pulu_iyl_state,  pulu_iyh_state,
303
                                                     pulu_spl_state,  pulu_sph_state,
304
                                                     pulu_pcl_state,  pulu_pch_state );
305
 
306
        type stack_type is array(2 downto 0) of state_type;
307
        type st_type    is (idle_st, push_st, pull_st );
308
        type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad );
309
        type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
310
                       ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
311
                       up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
312
                       pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout );
313
   type op_type    is (reset_op, fetch_op, latch_op );
314
   type pre_type   is (reset_pre, fetch_pre, latch_pre );
315
   type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc );
316
   type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca );
317
   type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb );
318
   type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp );
319
        type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix );
320
        type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy );
321
        type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp );
322
        type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up );
323
        type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc );
324
   type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md );
325
   type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea );
326 22 dilbert57
        type iv_type    is (latch_iv, reset_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
327 19 dilbert57
        type nmi_type   is (reset_nmi, set_nmi, latch_nmi );
328
        type left_type  is (cc_left, acca_left, accb_left, dp_left,
329
                                                          ix_left, iy_left, up_left, sp_left,
330
                       accd_left, md_left, pc_left, ea_left );
331
        type right_type is (ea_right, zero_right, one_right, two_right,
332
                       acca_right, accb_right, accd_right,
333
                                                          md_right, md_sign5_right, md_sign8_right );
334
   type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
335
                       alu_and, alu_ora, alu_eor,
336
                       alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
337
                                                     alu_lsr16, alu_lsl16,
338
                                                     alu_ror8, alu_rol8, alu_mul,
339
                                                     alu_asr8, alu_asl8, alu_lsr8,
340
                                                     alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
341
                                                          alu_seif, alu_sei, alu_see, alu_cle,
342
                                                     alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa );
343
 
344
        signal op_code:     std_logic_vector(7 downto 0);
345
        signal pre_code:    std_logic_vector(7 downto 0);
346
        signal acca:        std_logic_vector(7 downto 0);
347
        signal accb:        std_logic_vector(7 downto 0);
348
   signal cc:          std_logic_vector(7 downto 0);
349
        signal cc_out:      std_logic_vector(7 downto 0);
350
        signal dp:          std_logic_vector(7 downto 0);
351
        signal xreg:        std_logic_vector(15 downto 0);
352
        signal yreg:        std_logic_vector(15 downto 0);
353
        signal sp:          std_logic_vector(15 downto 0);
354
        signal up:          std_logic_vector(15 downto 0);
355
        signal ea:          std_logic_vector(15 downto 0);
356
        signal pc:              std_logic_vector(15 downto 0);
357
        signal md:          std_logic_vector(15 downto 0);
358
   signal left:        std_logic_vector(15 downto 0);
359
   signal right:       std_logic_vector(15 downto 0);
360
        signal out_alu:     std_logic_vector(15 downto 0);
361
        signal iv:          std_logic_vector(2 downto 0);
362
        signal nmi_req:     std_logic;
363
        signal nmi_ack:     std_logic;
364
        signal nmi_enable:  std_logic;
365
 
366
        signal state:        state_type;
367
        signal next_state:   state_type;
368
        signal saved_state:  state_type;
369
        signal return_state: state_type;
370
        signal state_stack:  stack_type;
371
        signal st_ctrl:      st_type;
372
   signal pc_ctrl:      pc_type;
373
   signal ea_ctrl:      ea_type;
374
   signal op_ctrl:      op_type;
375
        signal pre_ctrl:     pre_type;
376
        signal md_ctrl:      md_type;
377
        signal acca_ctrl:    acca_type;
378
        signal accb_ctrl:    accb_type;
379
        signal ix_ctrl:      ix_type;
380
        signal iy_ctrl:      iy_type;
381
        signal cc_ctrl:      cc_type;
382
        signal dp_ctrl:      dp_type;
383
        signal sp_ctrl:      sp_type;
384
        signal up_ctrl:      up_type;
385
        signal iv_ctrl:      iv_type;
386
        signal left_ctrl:    left_type;
387
        signal right_ctrl:   right_type;
388
   signal alu_ctrl:     alu_type;
389
   signal addr_ctrl:    addr_type;
390
   signal dout_ctrl:    dout_type;
391
   signal nmi_ctrl:     nmi_type;
392
 
393
 
394
begin
395
 
396
----------------------------------
397
--
398
-- State machine stack
399
--
400
----------------------------------
401
--state_stack_proc: process( clk, hold, state_stack, st_ctrl, 
402
--                           return_state, fetch_state  )
403
state_stack_proc: process( clk, state_stack )
404
begin
405
  if clk'event and clk = '0' then
406
    if hold= '1' then
407
           state_stack(0) <= state_stack(0);
408
           state_stack(1) <= state_stack(1);
409
           state_stack(2) <= state_stack(2);
410
         else
411
           case st_ctrl is
412
                when idle_st =>
413
                  state_stack(0) <= state_stack(0);
414
             state_stack(1) <= state_stack(1);
415
             state_stack(2) <= state_stack(2);
416
      when push_st =>
417
                  state_stack(0) <= return_state;
418
             state_stack(1) <= state_stack(0);
419
             state_stack(2) <= state_stack(1);
420
      when pull_st =>
421
                  state_stack(0) <= state_stack(1);
422
             state_stack(1) <= state_stack(2);
423
             state_stack(2) <= fetch_state;
424
                when others =>
425
                  state_stack(0) <= state_stack(0);
426
             state_stack(1) <= state_stack(1);
427
             state_stack(2) <= state_stack(2);
428
           end case;
429
    end if;
430
  end if;
431
  saved_state <= state_stack(0);
432
end process;
433
 
434
----------------------------------
435
--
436
-- Program Counter Control
437
--
438
----------------------------------
439
 
440
--pc_reg: process( clk, pc_ctrl, hold, pc, out_alu, data_in )
441
pc_reg: process( clk )
442
begin
443
  if clk'event and clk = '0' then
444
    if hold= '1' then
445
           pc <= pc;
446
         else
447
    case pc_ctrl is
448
         when reset_pc =>
449
           pc <= "0000000000000000";
450
         when load_pc =>
451
           pc <= out_alu(15 downto 0);
452
         when pull_lo_pc =>
453
           pc(7 downto 0) <= data_in;
454
         when pull_hi_pc =>
455
           pc(15 downto 8) <= data_in;
456
         when incr_pc =>
457
           pc <= pc + 1;
458
         when others =>
459
--       when latch_pc =>
460
      pc <= pc;
461
    end case;
462
         end if;
463
  end if;
464
end process;
465
 
466
----------------------------------
467
--
468
-- Effective Address  Control
469
--
470
----------------------------------
471
 
472
--ea_reg: process( clk, ea_ctrl, hold, ea, out_alu, data_in, dp )
473
ea_reg: process( clk )
474
begin
475
 
476
  if clk'event and clk = '0' then
477
    if hold= '1' then
478
           ea <= ea;
479
         else
480
    case ea_ctrl is
481
         when reset_ea =>
482
           ea <= "0000000000000000";
483
         when fetch_first_ea =>
484
           ea(7 downto 0) <= data_in;
485
      ea(15 downto 8) <= dp;
486
         when fetch_next_ea =>
487
           ea(15 downto 8) <= ea(7 downto 0);
488
      ea(7 downto 0)  <= data_in;
489
         when load_ea =>
490
           ea <= out_alu(15 downto 0);
491
         when others =>
492
--       when latch_ea =>
493
      ea <= ea;
494
    end case;
495
         end if;
496
  end if;
497
end process;
498
 
499
--------------------------------
500
--
501
-- Accumulator A
502
--
503
--------------------------------
504
--acca_reg : process( clk, acca_ctrl, hold, out_alu, acca, data_in )
505
acca_reg : process( clk )
506
begin
507
  if clk'event and clk = '0' then
508
    if hold= '1' then
509
           acca <= acca;
510
         else
511
    case acca_ctrl is
512
    when reset_acca =>
513
           acca <= "00000000";
514
         when load_acca =>
515
           acca <= out_alu(7 downto 0);
516
         when load_hi_acca =>
517
           acca <= out_alu(15 downto 8);
518
         when pull_acca =>
519
           acca <= data_in;
520
         when others =>
521
--       when latch_acca =>
522
           acca <= acca;
523
    end case;
524
         end if;
525
  end if;
526
end process;
527
 
528
--------------------------------
529
--
530
-- Accumulator B
531
--
532
--------------------------------
533
--accb_reg : process( clk, accb_ctrl, hold, out_alu, accb, data_in )
534
accb_reg : process( clk )
535
begin
536
  if clk'event and clk = '0' then
537
    if hold= '1' then
538
           accb <= accb;
539
         else
540
    case accb_ctrl is
541
    when reset_accb =>
542
           accb <= "00000000";
543
         when load_accb =>
544
           accb <= out_alu(7 downto 0);
545
         when pull_accb =>
546
           accb <= data_in;
547
         when others =>
548
--       when latch_accb =>
549
           accb <= accb;
550
    end case;
551
         end if;
552
  end if;
553
end process;
554
 
555
--------------------------------
556
--
557
-- X Index register
558
--
559
--------------------------------
560
--ix_reg : process( clk, ix_ctrl, hold, out_alu, xreg, data_in )
561
ix_reg : process( clk )
562
begin
563
  if clk'event and clk = '0' then
564
    if hold= '1' then
565
           xreg <= xreg;
566
         else
567
    case ix_ctrl is
568
    when reset_ix =>
569
           xreg <= "0000000000000000";
570
         when load_ix =>
571
           xreg <= out_alu(15 downto 0);
572
         when pull_hi_ix =>
573
           xreg(15 downto 8) <= data_in;
574
         when pull_lo_ix =>
575
           xreg(7 downto 0) <= data_in;
576
         when others =>
577
--       when latch_ix =>
578
           xreg <= xreg;
579
    end case;
580
         end if;
581
  end if;
582
end process;
583
 
584
--------------------------------
585
--
586
-- Y Index register
587
--
588
--------------------------------
589
--iy_reg : process( clk, iy_ctrl, hold, out_alu, yreg, data_in )
590
iy_reg : process( clk )
591
begin
592
  if clk'event and clk = '0' then
593
    if hold= '1' then
594
           yreg <= yreg;
595
         else
596
    case iy_ctrl is
597
    when reset_iy =>
598
           yreg <= "0000000000000000";
599
         when load_iy =>
600
           yreg <= out_alu(15 downto 0);
601
         when pull_hi_iy =>
602
           yreg(15 downto 8) <= data_in;
603
         when pull_lo_iy =>
604
           yreg(7 downto 0) <= data_in;
605
         when others =>
606
--       when latch_iy =>
607
           yreg <= yreg;
608
    end case;
609
         end if;
610
  end if;
611
end process;
612
 
613
--------------------------------
614
--
615
-- S stack pointer
616
--
617
--------------------------------
618
--sp_reg : process( clk, sp_ctrl, hold, sp, out_alu, data_in, nmi_enable )
619
sp_reg : process( clk )
620
begin
621
  if clk'event and clk = '0' then
622
    if hold= '1' then
623
           sp <= sp;
624
                nmi_enable <= nmi_enable;
625
         else
626
    case sp_ctrl is
627
    when reset_sp =>
628
           sp <= "0000000000000000";
629
                nmi_enable <= '0';
630
         when load_sp =>
631
           sp <= out_alu(15 downto 0);
632
                nmi_enable <= '1';
633
         when pull_hi_sp =>
634
           sp(15 downto 8) <= data_in;
635
                nmi_enable <= nmi_enable;
636
         when pull_lo_sp =>
637
           sp(7 downto 0) <= data_in;
638
                nmi_enable <= '1';
639
         when others =>
640
--       when latch_sp =>
641
           sp <= sp;
642
                nmi_enable <= nmi_enable;
643
    end case;
644
         end if;
645
  end if;
646
end process;
647
 
648
--------------------------------
649
--
650
-- U stack pointer
651
--
652
--------------------------------
653
--up_reg : process( clk, up_ctrl, hold, up, out_alu, data_in )
654
up_reg : process( clk )
655
begin
656
  if clk'event and clk = '0' then
657
    if hold= '1' then
658
           up <= up;
659
         else
660
    case up_ctrl is
661
    when reset_up =>
662
           up <= "0000000000000000";
663
         when load_up =>
664
           up <= out_alu(15 downto 0);
665
         when pull_hi_up =>
666
           up(15 downto 8) <= data_in;
667
         when pull_lo_up =>
668
           up(7 downto 0) <= data_in;
669
         when others =>
670
--       when latch_up =>
671
           up <= up;
672
    end case;
673
         end if;
674
  end if;
675
end process;
676
 
677
--------------------------------
678
--
679
-- Memory Data
680
--
681
--------------------------------
682
--md_reg : process( clk, md_ctrl, hold, out_alu, data_in, md )
683
md_reg : process( clk )
684
begin
685
  if clk'event and clk = '0' then
686
    if hold= '1' then
687
           md <= md;
688
         else
689
    case md_ctrl is
690
    when reset_md =>
691
           md <= "0000000000000000";
692
         when load_md =>
693
           md <= out_alu(15 downto 0);
694
         when fetch_first_md => -- sign extend md for branches
695
           md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
696
                              data_in(7) & data_in(7) & data_in(7) & data_in(7) ;
697
           md(7 downto 0) <= data_in;
698
         when fetch_next_md =>
699
           md(15 downto 8) <= md(7 downto 0);
700
                md(7 downto 0) <= data_in;
701
         when shiftl_md =>
702
           md(15 downto 1) <= md(14 downto 0);
703
                md(0) <= '0';
704
         when others =>
705
--       when latch_md =>
706
           md <= md;
707
    end case;
708
         end if;
709
  end if;
710
end process;
711
 
712
 
713
----------------------------------
714
--
715
-- Condition Codes
716
--
717
----------------------------------
718
 
719
--cc_reg: process( clk, cc_ctrl, hold, cc_out, cc, data_in )
720
cc_reg: process( clk )
721
begin
722
  if clk'event and clk = '0' then
723
    if hold= '1' then
724
           cc <= cc;
725
         else
726
    case cc_ctrl is
727
         when reset_cc =>
728
           cc <= "11010000"; -- set EBIT, FBIT & IBIT
729
         when load_cc =>
730
           cc <= cc_out;
731
         when pull_cc =>
732
      cc <= data_in;
733
         when others =>
734
--  when latch_cc =>
735
      cc <= cc;
736
    end case;
737
         end if;
738
  end if;
739
end process;
740
 
741
----------------------------------
742
--
743
-- Direct Page register
744
--
745
----------------------------------
746
 
747
--dp_reg: process( clk, dp_ctrl, hold, out_alu, dp, data_in )
748
dp_reg: process( clk )
749
begin
750
  if clk'event and clk = '0' then
751
    if hold= '1' then
752
           dp <= dp;
753
         else
754
    case dp_ctrl is
755
         when reset_dp =>
756
           dp <= "00000000";
757
         when load_dp =>
758
           dp <= out_alu(7 downto 0);
759
         when pull_dp =>
760
      dp <= data_in;
761
         when others =>
762
--  when latch_dp =>
763
      dp <= dp;
764
    end case;
765
         end if;
766
  end if;
767
end process;
768
 
769
----------------------------------
770
--
771
-- interrupt vector
772
--
773
----------------------------------
774
 
775
--iv_mux: process( clk, iv_ctrl, hold, iv )
776
iv_mux: process( clk )
777
begin
778
  if clk'event and clk = '0' then
779
    if hold= '1' then
780
           iv <= iv;
781
         else
782
    case iv_ctrl is
783
         when reset_iv =>
784
           iv <= RST_VEC;
785
         when nmi_iv =>
786
      iv <= NMI_VEC;
787
         when swi_iv =>
788
      iv <= SWI_VEC;
789
         when irq_iv =>
790
      iv <= IRQ_VEC;
791
         when firq_iv =>
792
           iv <= FIRQ_VEC;
793
         when swi2_iv =>
794
      iv <= SWI2_VEC;
795
         when swi3_iv =>
796
      iv <= SWI3_VEC;
797
         when resv_iv =>
798
      iv <= RESV_VEC;
799
         when others =>
800
           iv <= iv;
801
    end case;
802
         end if;
803
  end if;
804
end process;
805
 
806
 
807
----------------------------------
808
--
809
-- op code register
810
--
811
----------------------------------
812
 
813
--op_reg: process( clk, op_ctrl, hold, op_code, data_in )
814
op_reg: process( clk )
815
begin
816
  if clk'event and clk = '0' then
817
    if hold= '1' then
818
           op_code <= op_code;
819
         else
820
    case op_ctrl is
821
         when reset_op =>
822
           op_code <= "00010010";
823
         when fetch_op =>
824
      op_code <= data_in;
825
         when others =>
826
--       when latch_op =>
827
           op_code <= op_code;
828
    end case;
829
         end if;
830
  end if;
831
end process;
832
 
833
 
834
----------------------------------
835
--
836
-- pre byte op code register
837
--
838
----------------------------------
839
 
840
--pre_reg: process( clk, pre_ctrl, hold, pre_code, data_in )
841
pre_reg: process( clk )
842
begin
843
  if clk'event and clk = '0' then
844
    if hold= '1' then
845
           pre_code <= pre_code;
846
         else
847
    case pre_ctrl is
848
         when reset_pre =>
849
           pre_code <= "00000000";
850
         when fetch_pre =>
851
      pre_code <= data_in;
852
         when others =>
853
--       when latch_pre =>
854
           pre_code <= pre_code;
855
    end case;
856
         end if;
857
  end if;
858
end process;
859
 
860
--------------------------------
861
--
862
-- state machine
863
--
864
--------------------------------
865
 
866
--change_state: process( clk, rst, state, hold, next_state )
867
change_state: process( clk )
868
begin
869
  if clk'event and clk = '0' then
870
    if rst = '1' then
871
           state <= reset_state;
872
    else
873
           if hold = '1' then
874
                  state <= state;
875
                else
876
        state <= next_state;
877
                end if;
878
         end if;
879
  end if;
880
end process;
881
        -- output
882
 
883
------------------------------------
884
--
885
-- Nmi register
886
--
887
------------------------------------
888
 
889
--nmi_reg: process( clk, nmi_ctrl, hold, nmi_ack )
890
nmi_reg: process( clk )
891
begin
892
  if clk'event and clk='0' then
893
    if hold = '1' then
894
      nmi_ack <= nmi_ack;
895
    else
896
    case nmi_ctrl is
897
         when set_nmi =>
898
      nmi_ack <= '1';
899
         when reset_nmi =>
900
           nmi_ack <= '0';
901
         when others =>
902
--  when latch_nmi =>
903
           nmi_ack <= nmi_ack;
904
         end case;
905
         end if;
906
  end if;
907
end process;
908
 
909
------------------------------------
910
--
911
-- Detect Edge of NMI interrupt
912
--
913
------------------------------------
914
 
915
--nmi_handler : process( clk, rst, nmi, nmi_ack, nmi_req, nmi_enable )
916
nmi_handler : process( clk )
917
begin
918
  if clk'event and clk='0' then
919
    if rst='1' then
920
           nmi_req <= '0';
921
    else
922
           if (nmi='1') and (nmi_ack='0') and (nmi_enable='1') then
923
             nmi_req <= '1';
924
           else
925
                  if (nmi='0') and (nmi_ack='1') then
926
               nmi_req <= '0';
927
             else
928
               nmi_req <= nmi_req;
929
                  end if;
930
                end if;
931
         end if;
932
  end if;
933
end process;
934
 
935
 
936
----------------------------------
937
--
938
-- Address output multiplexer
939
--
940
----------------------------------
941
 
942
addr_mux: process( addr_ctrl, pc, ea, up, sp, iv )
943
begin
944
  case addr_ctrl is
945
    when idle_ad =>
946
           address <= "1111111111111111";
947
                vma     <= '0';
948
                rw      <= '1';
949
    when fetch_ad =>
950
           address <= pc;
951
                vma     <= '1';
952
                rw      <= '1';
953
         when read_ad =>
954
           address <= ea;
955
                vma     <= '1';
956
                rw      <= '1';
957
    when write_ad =>
958
           address <= ea;
959
                vma     <= '1';
960
                rw      <= '0';
961
         when pushs_ad =>
962
           address <= sp;
963
                vma     <= '1';
964
                rw      <= '0';
965
    when pulls_ad =>
966
           address <= sp;
967
                vma     <= '1';
968
                rw      <= '1';
969
         when pushu_ad =>
970
           address <= up;
971
                vma     <= '1';
972
                rw      <= '0';
973
    when pullu_ad =>
974
           address <= up;
975
                vma     <= '1';
976
                rw      <= '1';
977
         when int_hi_ad =>
978
           address <= "111111111111" & iv & "0";
979
                vma     <= '1';
980
                rw      <= '1';
981
    when int_lo_ad =>
982
           address <= "111111111111" & iv & "1";
983
                vma     <= '1';
984
                rw      <= '1';
985
         when others =>
986
           address <= "1111111111111111";
987
                vma     <= '0';
988
                rw      <= '1';
989
  end case;
990
end process;
991
 
992
--------------------------------
993
--
994
-- Data Bus output
995
--
996
--------------------------------
997
dout_mux : process( dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc )
998
begin
999
    case dout_ctrl is
1000 22 dilbert57
         when cc_dout => -- condition code register
1001
           data_out <= cc;
1002 19 dilbert57
         when acca_dout => -- accumulator a
1003
           data_out <= acca;
1004
         when accb_dout => -- accumulator b
1005
           data_out <= accb;
1006 22 dilbert57
         when dp_dout => -- direct page register
1007
           data_out <= dp;
1008
         when ix_lo_dout => -- X index reg
1009 19 dilbert57
           data_out <= xreg(7 downto 0);
1010 22 dilbert57
         when ix_hi_dout => -- X index reg
1011 19 dilbert57
           data_out <= xreg(15 downto 8);
1012 22 dilbert57
         when iy_lo_dout => -- Y index reg
1013 19 dilbert57
           data_out <= yreg(7 downto 0);
1014 22 dilbert57
         when iy_hi_dout => -- Y index reg
1015 19 dilbert57
           data_out <= yreg(15 downto 8);
1016 22 dilbert57
         when up_lo_dout => -- U stack pointer
1017
           data_out <= up(7 downto 0);
1018
         when up_hi_dout => -- U stack pointer
1019
           data_out <= up(15 downto 8);
1020
         when sp_lo_dout => -- S stack pointer
1021 19 dilbert57
           data_out <= sp(7 downto 0);
1022 22 dilbert57
         when sp_hi_dout => -- S stack pointer
1023 19 dilbert57
           data_out <= sp(15 downto 8);
1024 22 dilbert57
         when md_lo_dout => -- alu output
1025
           data_out <= md(7 downto 0);
1026
         when md_hi_dout => -- alu output
1027
           data_out <= md(15 downto 8);
1028 19 dilbert57
         when pc_lo_dout => -- low order pc
1029
           data_out <= pc(7 downto 0);
1030
         when pc_hi_dout => -- high order pc
1031
           data_out <= pc(15 downto 8);
1032
         when others =>
1033
           data_out <= "00000000";
1034
    end case;
1035
end process;
1036
 
1037
----------------------------------
1038
--
1039
-- Left Mux
1040
--
1041
----------------------------------
1042
 
1043
left_mux: process( left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md )
1044
begin
1045
  case left_ctrl is
1046
         when cc_left =>
1047
           left(15 downto 8) <= "00000000";
1048
                left(7 downto 0)  <= cc;
1049
         when acca_left =>
1050
           left(15 downto 8) <= "00000000";
1051
                left(7 downto 0)  <= acca;
1052
         when accb_left =>
1053
           left(15 downto 8) <= "00000000";
1054
                left(7 downto 0)  <= accb;
1055
         when dp_left =>
1056
           left(15 downto 8) <= "00000000";
1057
                left(7 downto 0)  <= dp;
1058
         when accd_left =>
1059
           left(15 downto 8) <= acca;
1060
                left(7 downto 0)  <= accb;
1061
         when md_left =>
1062
           left <= md;
1063
         when ix_left =>
1064
           left <= xreg;
1065
         when iy_left =>
1066
           left <= yreg;
1067
         when sp_left =>
1068
           left <= sp;
1069
         when up_left =>
1070
           left <= up;
1071
         when pc_left =>
1072
           left <= pc;
1073
         when others =>
1074
--       when ea_left =>
1075
           left <= ea;
1076
    end case;
1077
end process;
1078
 
1079
----------------------------------
1080
--
1081
-- Right Mux
1082
--
1083
----------------------------------
1084
 
1085
right_mux: process( right_ctrl, md, acca, accb, ea )
1086
begin
1087
  case right_ctrl is
1088
         when ea_right =>
1089
           right <= ea;
1090
         when zero_right =>
1091
           right <= "0000000000000000";
1092
         when one_right =>
1093
           right <= "0000000000000001";
1094
         when two_right =>
1095
           right <= "0000000000000010";
1096
         when acca_right =>
1097
           if acca(7) = '0' then
1098
             right <= "00000000" & acca(7 downto 0);
1099
                else
1100
                  right <= "11111111" & acca(7 downto 0);
1101
                end if;
1102
         when accb_right =>
1103
           if accb(7) = '0' then
1104
             right <= "00000000" & accb(7 downto 0);
1105
                else
1106
                  right <= "11111111" & accb(7 downto 0);
1107
                end if;
1108
         when accd_right =>
1109
           right <= acca & accb;
1110
         when md_sign5_right =>
1111
           if md(4) = '0' then
1112
             right <= "00000000000" & md(4 downto 0);
1113
                else
1114
                  right <= "11111111111" & md(4 downto 0);
1115
                end if;
1116
         when md_sign8_right =>
1117
           if md(7) = '0' then
1118
             right <= "00000000" & md(7 downto 0);
1119
                else
1120
                  right <= "11111111" & md(7 downto 0);
1121
                end if;
1122
         when others =>
1123
--       when md_right =>
1124
           right <= md;
1125
    end case;
1126
end process;
1127
 
1128
----------------------------------
1129
--
1130
-- Arithmetic Logic Unit
1131
--
1132
----------------------------------
1133
 
1134
alu: process( alu_ctrl, cc, left, right, out_alu, cc_out )
1135
variable valid_lo, valid_hi : boolean;
1136
variable carry_in : std_logic;
1137
variable daa_reg : std_logic_vector(7 downto 0);
1138
begin
1139
 
1140
  case alu_ctrl is
1141
         when alu_adc | alu_sbc |
1142
              alu_rol8 | alu_ror8 =>
1143
           carry_in := cc(CBIT);
1144
    when alu_asr8 =>
1145
           carry_in := left(7);
1146
         when others =>
1147
           carry_in := '0';
1148
  end case;
1149
 
1150
  valid_lo := left(3 downto 0) <= 9;
1151
  valid_hi := left(7 downto 4) <= 9;
1152
 
1153
  if (cc(CBIT) = '0') then
1154
    if( cc(HBIT) = '1' ) then
1155
                if valid_hi then
1156
                  daa_reg := "00000110";
1157
                else
1158
                  daa_reg := "01100110";
1159
           end if;
1160
    else
1161
                if valid_lo then
1162
                  if valid_hi then
1163
                    daa_reg := "00000000";
1164
                  else
1165
                    daa_reg := "01100000";
1166
                  end if;
1167
                else
1168
             if( left(7 downto 4) <= 8 ) then
1169
                    daa_reg := "00000110";
1170
                  else
1171
                         daa_reg := "01100110";
1172
                  end if;
1173
                end if;
1174
         end if;
1175
  else
1176
    if ( cc(HBIT) = '1' )then
1177
                daa_reg := "01100110";
1178
         else
1179
                if valid_lo then
1180
                  daa_reg := "01100000";
1181
           else
1182
                  daa_reg := "01100110";
1183
                end if;
1184
         end if;
1185
  end if;
1186
 
1187
  case alu_ctrl is
1188
         when alu_add8 | alu_inc |
1189
              alu_add16 | alu_adc | alu_mul =>
1190
                out_alu <= left + right + ("000000000000000" & carry_in);
1191
         when alu_sub8 | alu_dec |
1192
              alu_sub16 | alu_sbc =>
1193
           out_alu <= left - right - ("000000000000000" & carry_in);
1194
    when alu_abx =>
1195
           out_alu <= left + ("00000000" & right(7 downto 0)) ;
1196
         when alu_and =>
1197
           out_alu   <= left and right;         -- and/bit
1198
         when alu_ora =>
1199
           out_alu   <= left or right;  -- or
1200
         when alu_eor =>
1201
           out_alu   <= left xor right;         -- eor/xor
1202
         when alu_lsl16 | alu_asl8 | alu_rol8 =>
1203
           out_alu   <= left(14 downto 0) & carry_in;    -- rol8/asl8/lsl16
1204
         when alu_lsr16 =>
1205
           out_alu   <= carry_in & left(15 downto 1);   -- lsr16
1206
         when alu_lsr8 | alu_asr8 | alu_ror8 =>
1207
           out_alu   <= "00000000" & carry_in & left(7 downto 1);       -- ror8/asr8/lsr8
1208
         when alu_neg =>
1209
           out_alu   <= right - left;   -- neg (right=0)
1210
         when alu_com =>
1211
           out_alu   <= not left;
1212
         when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
1213
           out_alu   <= right;           -- clr, ld
1214
         when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
1215
           out_alu   <= left;
1216
         when alu_daa =>
1217
           out_alu   <= left + ("00000000" & daa_reg);
1218
         when alu_sex =>
1219
           if left(7) = '0' then
1220
              out_alu <= "00000000" & left(7 downto 0);
1221
                else
1222
                   out_alu <= "11111111" & left(7 downto 0);
1223
                end if;
1224
         when others =>
1225
           out_alu   <= left; -- nop
1226
    end case;
1227
 
1228
         --
1229
         -- carry bit
1230
         --
1231
    case alu_ctrl is
1232
         when alu_add8 | alu_adc  =>
1233
      cc_out(CBIT) <= (left(7) and right(7)) or
1234
                                (left(7) and not out_alu(7)) or
1235
                                                   (right(7) and not out_alu(7));
1236
         when alu_sub8 | alu_sbc =>
1237
      cc_out(CBIT) <= ((not left(7)) and right(7)) or
1238
                                ((not left(7)) and out_alu(7)) or
1239
                                                         (right(7) and out_alu(7));
1240
         when alu_add16  =>
1241
      cc_out(CBIT) <= (left(15) and right(15)) or
1242
                                (left(15) and not out_alu(15)) or
1243
                                                   (right(15) and not out_alu(15));
1244
         when alu_sub16 =>
1245
      cc_out(CBIT) <= ((not left(15)) and right(15)) or
1246
                                ((not left(15)) and out_alu(15)) or
1247
                                                         (right(15) and out_alu(15));
1248
         when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
1249
           cc_out(CBIT) <= left(0);
1250
         when alu_rol8 | alu_asl8 =>
1251
           cc_out(CBIT) <= left(7);
1252
         when alu_lsl16 =>
1253
           cc_out(CBIT) <= left(15);
1254
         when alu_com =>
1255
           cc_out(CBIT) <= '1';
1256
         when alu_neg | alu_clr =>
1257
           cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1258
                                out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
1259
    when alu_mul =>
1260
                cc_out(CBIT) <= out_alu(7);
1261
    when alu_daa =>
1262
           if ( daa_reg(7 downto 4) = "0110" ) then
1263
                  cc_out(CBIT) <= '1';
1264
                else
1265
                  cc_out(CBIT) <= '0';
1266
           end if;
1267
         when alu_andcc =>
1268
      cc_out(CBIT) <= left(CBIT) and cc(CBIT);
1269
         when alu_orcc =>
1270
      cc_out(CBIT) <= left(CBIT) or cc(CBIT);
1271
         when alu_tfr =>
1272
      cc_out(CBIT) <= left(CBIT);
1273
         when others =>
1274
      cc_out(CBIT) <= cc(CBIT);
1275
    end case;
1276
         --
1277
         -- Zero flag
1278
         --
1279
    case alu_ctrl is
1280
         when alu_add8 | alu_sub8 |
1281
              alu_adc | alu_sbc |
1282
              alu_and | alu_ora | alu_eor |
1283
              alu_inc | alu_dec |
1284
                        alu_neg | alu_com | alu_clr |
1285
                        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1286
                   alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1287
      cc_out(ZBIT) <= not( out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1288
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1289
         when alu_add16 | alu_sub16 | alu_mul |
1290
              alu_lsl16 | alu_lsr16 |
1291
                   alu_ld16  | alu_st16 | alu_lea =>
1292
      cc_out(ZBIT) <= not( out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
1293
                                out_alu(11) or out_alu(10) or out_alu(9)  or out_alu(8)  or
1294
                                out_alu(7)  or out_alu(6)  or out_alu(5)  or out_alu(4)  or
1295
                                out_alu(3)  or out_alu(2)  or out_alu(1)  or out_alu(0) );
1296
         when alu_andcc =>
1297
      cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
1298
         when alu_orcc =>
1299
      cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
1300
         when alu_tfr =>
1301
      cc_out(ZBIT) <= left(ZBIT);
1302
         when others =>
1303
      cc_out(ZBIT) <= cc(ZBIT);
1304
    end case;
1305
 
1306
    --
1307
         -- negative flag
1308
         --
1309
    case alu_ctrl is
1310
         when alu_add8 | alu_sub8 |
1311
              alu_adc | alu_sbc |
1312
              alu_and | alu_ora | alu_eor |
1313
              alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1314
              alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
1315
                        alu_ld8  | alu_st8 | alu_sex | alu_daa =>
1316
      cc_out(NBIT) <= out_alu(7);
1317
         when alu_add16 | alu_sub16 |
1318
              alu_lsl16 | alu_lsr16 |
1319
                        alu_ld16 | alu_st16 =>
1320
                cc_out(NBIT) <= out_alu(15);
1321
         when alu_andcc =>
1322
      cc_out(NBIT) <= left(NBIT) and cc(NBIT);
1323
         when alu_orcc =>
1324
      cc_out(NBIT) <= left(NBIT) or cc(NBIT);
1325
         when alu_tfr =>
1326
      cc_out(NBIT) <= left(NBIT);
1327
         when others =>
1328
      cc_out(NBIT) <= cc(NBIT);
1329
    end case;
1330
 
1331
    --
1332
         -- Interrupt mask flag
1333
    --
1334
    case alu_ctrl is
1335
         when alu_andcc =>
1336
      cc_out(IBIT) <= left(IBIT) and cc(IBIT);
1337
         when alu_orcc =>
1338
      cc_out(IBIT) <= left(IBIT) or cc(IBIT);
1339
         when alu_tfr =>
1340
      cc_out(IBIT) <= left(IBIT);
1341
    when alu_seif | alu_sei =>
1342
           cc_out(IBIT) <= '1';
1343
         when others =>
1344
                cc_out(IBIT) <= cc(IBIT);             -- interrupt mask
1345
    end case;
1346
 
1347
    --
1348
    -- Half Carry flag
1349
         --
1350
    case alu_ctrl is
1351
         when alu_add8 | alu_adc =>
1352
      cc_out(HBIT) <= (left(3) and right(3)) or
1353
                     (right(3) and not out_alu(3)) or
1354
                      (left(3) and not out_alu(3));
1355
         when alu_andcc =>
1356
      cc_out(HBIT) <= left(HBIT) and cc(HBIT);
1357
         when alu_orcc =>
1358
      cc_out(HBIT) <= left(HBIT) or cc(HBIT);
1359
         when alu_tfr =>
1360
      cc_out(HBIT) <= left(HBIT);
1361
         when others =>
1362
                cc_out(HBIT) <= cc(HBIT);
1363
    end case;
1364
 
1365
    --
1366
    -- Overflow flag
1367
         --
1368
    case alu_ctrl is
1369
         when alu_add8 | alu_adc =>
1370
      cc_out(VBIT) <= (left(7)  and      right(7)  and (not out_alu(7))) or
1371
                 ((not left(7)) and (not right(7)) and      out_alu(7));
1372
         when alu_sub8 | alu_sbc =>
1373
      cc_out(VBIT) <= (left(7)  and (not right(7)) and (not out_alu(7))) or
1374
                 ((not left(7)) and      right(7)  and      out_alu(7));
1375
         when alu_add16 =>
1376
      cc_out(VBIT) <= (left(15)  and      right(15)  and (not out_alu(15))) or
1377
                 ((not left(15)) and (not right(15)) and      out_alu(15));
1378
         when alu_sub16 =>
1379
      cc_out(VBIT) <= (left(15)  and (not right(15)) and (not out_alu(15))) or
1380
                 ((not left(15)) and      right(15) and       out_alu(15));
1381
         when alu_inc =>
1382
           cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
1383
                                      left(3)  and left(2) and left(1) and left(0));
1384
         when alu_dec | alu_neg =>
1385
           cc_out(VBIT) <= (left(7)  and (not left(6)) and (not left(5)) and (not left(4)) and
1386
                            (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
1387
-- 6809 Programming reference manual says
1388
-- V not affected by ASR, LSR and ROR
1389
-- This is different to the 6800
1390
-- John Kent 6th June 2006
1391
--       when alu_asr8 =>
1392
--         cc_out(VBIT) <= left(0) xor left(7);
1393
--       when alu_lsr8 | alu_lsr16 =>
1394
--         cc_out(VBIT) <= left(0);
1395
--       when alu_ror8 =>
1396
--      cc_out(VBIT) <= left(0) xor cc(CBIT);
1397
    when alu_lsl16 =>
1398
      cc_out(VBIT) <= left(15) xor left(14);
1399
         when alu_rol8 | alu_asl8 =>
1400
      cc_out(VBIT) <= left(7) xor left(6);
1401
--
1402
-- 11th July 2006 - John Kent
1403
-- What DAA does with V is anyones guess
1404
-- It is undefined in the 6809 programming manual
1405
--
1406
         when alu_daa =>
1407
      cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
1408
-- CLR resets V Bit
1409
-- John Kent 6th June 2006
1410
         when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
1411
              alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
1412
      cc_out(VBIT) <= '0';
1413
         when alu_andcc =>
1414
      cc_out(VBIT) <= left(VBIT) and cc(VBIT);
1415
         when alu_orcc =>
1416
      cc_out(VBIT) <= left(VBIT) or cc(VBIT);
1417
         when alu_tfr =>
1418
      cc_out(VBIT) <= left(VBIT);
1419
         when others =>
1420
                cc_out(VBIT) <= cc(VBIT);
1421
    end case;
1422
 
1423
         case alu_ctrl is
1424
         when alu_andcc =>
1425
      cc_out(FBIT) <= left(FBIT) and cc(FBIT);
1426
         when alu_orcc =>
1427
      cc_out(FBIT) <= left(FBIT) or cc(FBIT);
1428
         when alu_tfr =>
1429
      cc_out(FBIT) <= left(FBIT);
1430
    when alu_seif =>
1431
           cc_out(FBIT) <= '1';
1432
         when others =>
1433
      cc_out(FBIT) <= cc(FBIT);
1434
         end case;
1435
 
1436
         case alu_ctrl is
1437
         when alu_andcc =>
1438
      cc_out(EBIT) <= left(EBIT) and cc(EBIT);
1439
         when alu_orcc =>
1440
      cc_out(EBIT) <= left(EBIT) or cc(EBIT);
1441
         when alu_tfr =>
1442
      cc_out(EBIT) <= left(EBIT);
1443
    when alu_see =>
1444
           cc_out(EBIT) <= '1';
1445
    when alu_cle =>
1446
           cc_out(EBIT) <= '0';
1447
         when others =>
1448
           cc_out(EBIT) <= cc(EBIT);
1449
         end case;
1450
end process;
1451
 
1452
------------------------------------
1453
--
1454
-- state sequencer
1455
--
1456
------------------------------------
1457
process( state, saved_state,
1458
         op_code, pre_code,
1459
                        cc, ea, md, iv,
1460
                        irq, firq, nmi_req, nmi_ack, halt )
1461
variable cond_true : boolean;  -- variable used to evaluate coditional branches
1462
begin
1463 22 dilbert57
        -- Registers preserved
1464
        cc_ctrl    <= latch_cc;
1465
        acca_ctrl  <= latch_acca;
1466
        accb_ctrl  <= latch_accb;
1467
        dp_ctrl    <= latch_dp;
1468
        ix_ctrl    <= latch_ix;
1469
        iy_ctrl    <= latch_iy;
1470
        up_ctrl    <= latch_up;
1471
        sp_ctrl    <= latch_sp;
1472
        pc_ctrl    <= latch_pc;
1473
        md_ctrl    <= latch_md;
1474
        ea_ctrl    <= latch_ea;
1475
        iv_ctrl    <= latch_iv;
1476
        op_ctrl    <= latch_op;
1477
        pre_ctrl   <= latch_pre;
1478
        nmi_ctrl   <= latch_nmi;
1479
                  -- ALU Idle
1480
        left_ctrl  <= pc_left;
1481
        right_ctrl <= zero_right;
1482
        alu_ctrl   <= alu_nop;
1483
                  -- Bus idle
1484
        addr_ctrl  <= idle_ad;
1485
        dout_ctrl  <= cc_dout;
1486
                  -- Next State Fetch
1487
        st_ctrl      <= idle_st;
1488
        return_state <= fetch_state;
1489
        next_state   <= fetch_state;
1490
 
1491 19 dilbert57
                  case state is
1492
          when reset_state =>        --  released from reset
1493
                            -- reset the registers
1494
             op_ctrl    <= reset_op;
1495
             pre_ctrl   <= reset_pre;
1496 22 dilbert57
             cc_ctrl    <= reset_cc;
1497 19 dilbert57
                                 acca_ctrl  <= reset_acca;
1498
                                 accb_ctrl  <= reset_accb;
1499 22 dilbert57
             dp_ctrl    <= reset_dp;
1500 19 dilbert57
                                 ix_ctrl    <= reset_ix;
1501
                                 iy_ctrl    <= reset_iy;
1502 22 dilbert57
                       up_ctrl    <= reset_up;
1503 19 dilbert57
                       sp_ctrl    <= reset_sp;
1504
                       pc_ctrl    <= reset_pc;
1505
                            ea_ctrl    <= reset_ea;
1506
                                 md_ctrl    <= reset_md;
1507
                                 iv_ctrl    <= reset_iv;
1508
                                 nmi_ctrl   <= reset_nmi;
1509
                       next_state <= vect_hi_state;
1510
 
1511
                         --
1512
                         -- Jump via interrupt vector
1513
                         -- iv holds interrupt type
1514
                         -- fetch PC hi from vector location
1515
                         --
1516
          when vect_hi_state =>
1517
                                 -- fetch pc low interrupt vector
1518
                       pc_ctrl    <= pull_hi_pc;
1519
             addr_ctrl  <= int_hi_ad;
1520
                       next_state <= vect_lo_state;
1521
                         --
1522
                         -- jump via interrupt vector
1523
                         -- iv holds vector type
1524
                         -- fetch PC lo from vector location
1525
                         --
1526
          when vect_lo_state =>
1527
                                 -- fetch the vector low byte
1528
                       pc_ctrl    <= pull_lo_pc;
1529
             addr_ctrl  <= int_lo_ad;
1530
                       next_state <= fetch_state;
1531
                         --
1532
                         -- Here to fetch an instruction
1533
                         -- PC points to opcode
1534
                         -- Should service interrupt requests at this point
1535
                         -- either from the timer
1536
                         -- or from the external input.
1537
                         --
1538
          when fetch_state =>
1539
                                   -- fetch the op code
1540
                              op_ctrl    <= fetch_op;
1541
               pre_ctrl   <= fetch_pre;
1542
               ea_ctrl    <= reset_ea;
1543
                                   -- Fetch op code
1544
               addr_ctrl  <= fetch_ad;
1545
                                   --
1546
                                        case op_code(7 downto 6) is
1547
                                        when "10" => -- acca
1548
                                     case op_code(3 downto 0) is
1549
                                          when "0000" => -- suba
1550
                                            left_ctrl  <= acca_left;
1551
                                            right_ctrl <= md_right;
1552
                                            alu_ctrl   <= alu_sub8;
1553
                                                 cc_ctrl    <= load_cc;
1554
                                            acca_ctrl  <= load_acca;
1555
                                          when "0001" => -- cmpa
1556
                                            left_ctrl   <= acca_left;
1557
                                            right_ctrl  <= md_right;
1558
                                            alu_ctrl    <= alu_sub8;
1559
                                                 cc_ctrl     <= load_cc;
1560
                                          when "0010" => -- sbca
1561
                                            left_ctrl   <= acca_left;
1562
                                            right_ctrl  <= md_right;
1563
                                            alu_ctrl    <= alu_sbc;
1564
                                                 cc_ctrl     <= load_cc;
1565
                                            acca_ctrl   <= load_acca;
1566
                                          when "0011" =>
1567
                                            case pre_code is
1568
                                                 when "00010000" => -- page 2 -- cmpd
1569
                                              left_ctrl   <= accd_left;
1570
                                              right_ctrl  <= md_right;
1571
                                              alu_ctrl    <= alu_sub16;
1572
                                                   cc_ctrl     <= load_cc;
1573
                                                 when "00010001" => -- page 3 -- cmpu
1574
                                              left_ctrl   <= up_left;
1575
                                              right_ctrl  <= md_right;
1576
                                              alu_ctrl    <= alu_sub16;
1577
                                                   cc_ctrl     <= load_cc;
1578
                                                 when others => -- page 1 -- subd
1579
                                              left_ctrl   <= accd_left;
1580
                                              right_ctrl  <= md_right;
1581
                                              alu_ctrl    <= alu_sub16;
1582
                                                   cc_ctrl     <= load_cc;
1583
                                              acca_ctrl   <= load_hi_acca;
1584
                                                   accb_ctrl   <= load_accb;
1585
                                                 end case;
1586
                                          when "0100" => -- anda
1587
                                            left_ctrl   <= acca_left;
1588
                                            right_ctrl  <= md_right;
1589
                                            alu_ctrl    <= alu_and;
1590
                                                 cc_ctrl     <= load_cc;
1591
                                            acca_ctrl   <= load_acca;
1592
                                          when "0101" => -- bita
1593
                                            left_ctrl   <= acca_left;
1594
                                            right_ctrl  <= md_right;
1595
                                            alu_ctrl    <= alu_and;
1596
                                                 cc_ctrl     <= load_cc;
1597
                                          when "0110" => -- ldaa
1598
                                            left_ctrl   <= acca_left;
1599
                                            right_ctrl  <= md_right;
1600
                                            alu_ctrl    <= alu_ld8;
1601
                                                 cc_ctrl     <= load_cc;
1602
                                            acca_ctrl   <= load_acca;
1603
                                          when "0111" => -- staa
1604
                                            left_ctrl   <= acca_left;
1605
                                            right_ctrl  <= md_right;
1606
                                            alu_ctrl    <= alu_st8;
1607
                                                 cc_ctrl     <= load_cc;
1608
                                          when "1000" => -- eora
1609
                                            left_ctrl   <= acca_left;
1610
                                            right_ctrl  <= md_right;
1611
                                            alu_ctrl    <= alu_eor;
1612
                                                 cc_ctrl     <= load_cc;
1613
                                            acca_ctrl   <= load_acca;
1614
                                          when "1001" => -- adca
1615
                                            left_ctrl   <= acca_left;
1616
                                            right_ctrl  <= md_right;
1617
                                            alu_ctrl    <= alu_adc;
1618
                                                 cc_ctrl     <= load_cc;
1619
                                            acca_ctrl   <= load_acca;
1620
                                          when "1010" => -- oraa
1621
                                            left_ctrl   <= acca_left;
1622
                                            right_ctrl  <= md_right;
1623
                                            alu_ctrl    <= alu_ora;
1624
                                                 cc_ctrl     <= load_cc;
1625
                                            acca_ctrl   <= load_acca;
1626
                                          when "1011" => -- adda
1627
                                            left_ctrl   <= acca_left;
1628
                                            right_ctrl  <= md_right;
1629
                                            alu_ctrl    <= alu_add8;
1630
                                                 cc_ctrl     <= load_cc;
1631
                                            acca_ctrl   <= load_acca;
1632
                                          when "1100" =>
1633
                                            case pre_code is
1634
                                                 when "00010000" => -- page 2 -- cmpy
1635
                                              left_ctrl   <= iy_left;
1636
                                              right_ctrl  <= md_right;
1637
                                              alu_ctrl    <= alu_sub16;
1638
                                                   cc_ctrl     <= load_cc;
1639
                                                 when "00010001" => -- page 3 -- cmps
1640
                                              left_ctrl   <= sp_left;
1641
                                              right_ctrl  <= md_right;
1642
                                              alu_ctrl    <= alu_sub16;
1643
                                                   cc_ctrl     <= load_cc;
1644
                                                 when others => -- page 1 -- cmpx
1645
                                              left_ctrl   <= ix_left;
1646
                                              right_ctrl  <= md_right;
1647
                                              alu_ctrl    <= alu_sub16;
1648
                                                   cc_ctrl     <= load_cc;
1649
                                                 end case;
1650
                                          when "1101" => -- bsr / jsr
1651 22 dilbert57
                                            null;
1652 19 dilbert57
                                          when "1110" => -- ldx
1653
                                            case pre_code is
1654
                                                 when "00010000" => -- page 2 -- ldy
1655
                                              left_ctrl   <= iy_left;
1656
                                              right_ctrl  <= md_right;
1657
                                              alu_ctrl    <= alu_ld16;
1658
                                                   cc_ctrl     <= load_cc;
1659
                     iy_ctrl     <= load_iy;
1660
                                                 when others =>   -- page 1 -- ldx
1661
                                              left_ctrl   <= ix_left;
1662
                                              right_ctrl  <= md_right;
1663
                                              alu_ctrl    <= alu_ld16;
1664
                                                   cc_ctrl     <= load_cc;
1665
                     ix_ctrl     <= load_ix;
1666
                                                 end case;
1667
                                          when "1111" => -- stx
1668
                                            case pre_code is
1669
                                                 when "00010000" => -- page 2 -- sty
1670
                                              left_ctrl   <= iy_left;
1671
                                              right_ctrl  <= md_right;
1672
                                              alu_ctrl    <= alu_st16;
1673
                                                   cc_ctrl     <= load_cc;
1674
                                                 when others =>     -- page 1 -- stx
1675
                                              left_ctrl   <= ix_left;
1676
                                              right_ctrl  <= md_right;
1677
                                              alu_ctrl    <= alu_st16;
1678
                                                   cc_ctrl     <= load_cc;
1679
                                                 end case;
1680
                                          when others =>
1681
                                            null;
1682
                                          end case;
1683
                                        when "11" => -- accb dual op
1684
                                     case op_code(3 downto 0) is
1685
                                          when "0000" => -- subb
1686
                                            left_ctrl   <= accb_left;
1687
                                            right_ctrl  <= md_right;
1688
                                            alu_ctrl    <= alu_sub8;
1689
                                                 cc_ctrl     <= load_cc;
1690
                   accb_ctrl   <= load_accb;
1691
                                          when "0001" => -- cmpb
1692
                                            left_ctrl   <= accb_left;
1693
                                            right_ctrl  <= md_right;
1694
                                            alu_ctrl    <= alu_sub8;
1695
                                                 cc_ctrl     <= load_cc;
1696
                                          when "0010" => -- sbcb
1697
                                            left_ctrl   <= accb_left;
1698
                                            right_ctrl  <= md_right;
1699
                                            alu_ctrl    <= alu_sbc;
1700
                                                 cc_ctrl     <= load_cc;
1701
                   accb_ctrl   <= load_accb;
1702
                                          when "0011" => -- addd
1703
                                            left_ctrl   <= accd_left;
1704
                                            right_ctrl  <= md_right;
1705
                                            alu_ctrl    <= alu_add16;
1706
                                                 cc_ctrl     <= load_cc;
1707
                                            acca_ctrl   <= load_hi_acca;
1708
                                                 accb_ctrl   <= load_accb;
1709
                                          when "0100" => -- andb
1710
                                            left_ctrl   <= accb_left;
1711
                                            right_ctrl  <= md_right;
1712
                                            alu_ctrl    <= alu_and;
1713
                                                 cc_ctrl     <= load_cc;
1714
                   accb_ctrl   <= load_accb;
1715
                                          when "0101" => -- bitb
1716
                                            left_ctrl   <= accb_left;
1717
                                            right_ctrl  <= md_right;
1718
                                            alu_ctrl    <= alu_and;
1719
                                                 cc_ctrl     <= load_cc;
1720
                                          when "0110" => -- ldab
1721
                                            left_ctrl   <= accb_left;
1722
                                            right_ctrl  <= md_right;
1723
                                            alu_ctrl    <= alu_ld8;
1724
                                                 cc_ctrl     <= load_cc;
1725
                   accb_ctrl   <= load_accb;
1726
                                          when "0111" => -- stab
1727
                                            left_ctrl   <= accb_left;
1728
                                            right_ctrl  <= md_right;
1729
                                            alu_ctrl    <= alu_st8;
1730
                                                 cc_ctrl     <= load_cc;
1731
                                          when "1000" => -- eorb
1732
                                            left_ctrl   <= accb_left;
1733
                                            right_ctrl  <= md_right;
1734
                                            alu_ctrl    <= alu_eor;
1735
                                                 cc_ctrl     <= load_cc;
1736
                   accb_ctrl   <= load_accb;
1737
                                          when "1001" => -- adcb
1738
                                            left_ctrl   <= accb_left;
1739
                                            right_ctrl  <= md_right;
1740
                                            alu_ctrl    <= alu_adc;
1741
                                                 cc_ctrl     <= load_cc;
1742
                   accb_ctrl   <= load_accb;
1743
                                          when "1010" => -- orab
1744
                                            left_ctrl   <= accb_left;
1745
                                            right_ctrl  <= md_right;
1746
                                            alu_ctrl    <= alu_ora;
1747
                                                 cc_ctrl     <= load_cc;
1748
                   accb_ctrl   <= load_accb;
1749
                                          when "1011" => -- addb
1750
                                            left_ctrl   <= accb_left;
1751
                                            right_ctrl  <= md_right;
1752
                                            alu_ctrl    <= alu_add8;
1753
                                                 cc_ctrl     <= load_cc;
1754
                   accb_ctrl   <= load_accb;
1755
                                          when "1100" => -- ldd
1756
                                            left_ctrl   <= accd_left;
1757
                                            right_ctrl  <= md_right;
1758
                                            alu_ctrl    <= alu_ld16;
1759
                                                 cc_ctrl     <= load_cc;
1760
                                            acca_ctrl   <= load_hi_acca;
1761
                   accb_ctrl   <= load_accb;
1762
                                          when "1101" => -- std
1763
                                            left_ctrl   <= accd_left;
1764
                                            right_ctrl  <= md_right;
1765
                                            alu_ctrl    <= alu_st16;
1766
                                                 cc_ctrl     <= load_cc;
1767
                                          when "1110" => -- ldu
1768
                                            case pre_code is
1769
                                                 when "00010000" => -- page 2 -- lds
1770
                                              left_ctrl   <= sp_left;
1771
                                              right_ctrl  <= md_right;
1772
                                              alu_ctrl    <= alu_ld16;
1773
                                                   cc_ctrl     <= load_cc;
1774
                                                   sp_ctrl     <= load_sp;
1775
                                                 when others => -- page 1 -- ldu
1776
                                              left_ctrl   <= up_left;
1777
                                              right_ctrl  <= md_right;
1778
                                              alu_ctrl    <= alu_ld16;
1779
                                                   cc_ctrl     <= load_cc;
1780
                     up_ctrl     <= load_up;
1781
                                                 end case;
1782
                                          when "1111" =>
1783
                                            case pre_code is
1784
                                                 when "00010000" => -- page 2 -- sts
1785
                                              left_ctrl   <= sp_left;
1786
                                              right_ctrl  <= md_right;
1787
                                              alu_ctrl    <= alu_st16;
1788
                                                   cc_ctrl     <= load_cc;
1789
                                                 when others =>     -- page 1 -- stu
1790
                                              left_ctrl   <= up_left;
1791
                                              right_ctrl  <= md_right;
1792
                                              alu_ctrl    <= alu_st16;
1793
                                                   cc_ctrl     <= load_cc;
1794
                                                 end case;
1795
                                          when others =>
1796
                                            null;
1797
                                          end case;
1798
                                        when others =>
1799 22 dilbert57
                                          null;
1800 19 dilbert57
                                        end case;
1801
                                 if halt = '1' then
1802
                              iv_ctrl    <= reset_iv;
1803
                              next_state <= halt_state;
1804
                                 -- service non maskable interrupts
1805
                            elsif (nmi_req = '1') and (nmi_ack = '0') then
1806
                              iv_ctrl    <= nmi_iv;
1807
                                   nmi_ctrl   <= set_nmi;
1808 22 dilbert57
                              next_state <= int_nmiirq_state;
1809 19 dilbert57
                                 -- service maskable interrupts
1810
                            else
1811
                                   --
1812
                                        -- nmi request is not cleared until nmi input goes low
1813
                                        --
1814
                                   if(nmi_req = '0') and (nmi_ack='1') then
1815
                                     nmi_ctrl <= reset_nmi;
1816
                                        end if;
1817
                                        --
1818 22 dilbert57
                                        -- FIRQ & IRQ are level sensitive
1819 19 dilbert57
                                        --
1820 22 dilbert57
               if (firq = '1') and (cc(FBIT) = '0') then
1821
                                iv_ctrl    <= firq_iv;
1822
                                next_state <= int_firq_state;
1823
                                   elsif (irq = '1') and (cc(IBIT) = '0') then
1824 19 dilbert57
                                iv_ctrl    <= irq_iv;
1825 22 dilbert57
                                next_state <= int_nmiirq_state;
1826 19 dilbert57
               else
1827 22 dilbert57
                                     -- Advance the PC to fetch next instruction byte
1828 19 dilbert57
                                iv_ctrl    <= reset_iv; -- default to reset
1829
                 pc_ctrl    <= incr_pc;
1830
                                next_state <= decode1_state;
1831
               end if;
1832
                                 end if;
1833
                         --
1834
                         -- Here to decode instruction
1835
                         -- and fetch next byte of intruction
1836
                         -- whether it be necessary or not
1837
                         --
1838
          when decode1_state =>
1839
                                 -- fetch first byte of address or immediate data
1840
             ea_ctrl    <= fetch_first_ea;
1841
                                 md_ctrl    <= fetch_first_md;
1842
             addr_ctrl  <= fetch_ad;
1843
                            case op_code(7 downto 4) is
1844
                                 --
1845
                                 -- direct single op (2 bytes)
1846
                                 -- 6809 => 6 cycles
1847
                                 -- cpu09 => 5 cycles
1848
                            -- 1 op=(pc) / pc=pc+1
1849
                                 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1850
                                 -- 3 md_lo=(ea) / pc=pc
1851
                                 -- 4 alu_left=md / md=alu_out / pc=pc
1852
                                 -- 5 (ea)=md_lo / pc=pc
1853
                                 --
1854
                                 -- Exception is JMP
1855
                            -- 6809 => 3 cycles
1856
                                 -- cpu09 => 3 cycles
1857
                                 -- 1 op=(pc) / pc=pc+1
1858
                                 -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
1859
                                 -- 3 pc=ea
1860
                                 --
1861
                  when "0000" =>
1862
                                        -- advance the PC
1863
               pc_ctrl    <= incr_pc;
1864
                                        case op_code(3 downto 0) is
1865
                                   when "1110" => -- jmp
1866
                                     next_state <= jmp_state;
1867
                                        when "1111" => -- clr
1868
                                     next_state <= single_op_exec_state;
1869
                                        when others =>
1870
                                     next_state <= single_op_read_state;
1871
                                        end case;
1872
 
1873
                                 -- acca / accb inherent instructions
1874
                  when "0001" =>
1875
                    case op_code(3 downto 0) is
1876
                                        --
1877
                                        -- Page2 pre byte
1878
                                        -- pre=(pc) / pc=pc+1
1879
                                        -- op=(pc) / pc=pc+1
1880
                                        --
1881
                         when "0000" => -- page2
1882
                                op_ctrl    <= fetch_op;
1883
                                          -- advance pc
1884
                 pc_ctrl    <= incr_pc;
1885 22 dilbert57
                                          next_state <= decode2_state;
1886 19 dilbert57
 
1887
                                        --
1888
                                        -- Page3 pre byte
1889
                                        -- pre=(pc) / pc=pc+1
1890
                                        -- op=(pc) / pc=pc+1
1891
                                        --
1892
                         when "0001" => -- page3
1893
                                op_ctrl    <= fetch_op;
1894
                                          -- advance pc
1895
                 pc_ctrl    <= incr_pc;
1896 22 dilbert57
                                          next_state <= decode3_state;
1897 19 dilbert57
 
1898
                                        --
1899
                                        -- nop - No operation ( 1 byte )
1900
                                        -- 6809 => 2 cycles
1901
                                        -- cpu09 => 2 cycles
1902
                                        -- 1 op=(pc) / pc=pc+1
1903
                                        -- 2 decode
1904
                                        -- 
1905
                         when "0010" => -- nop
1906
                                          next_state   <= fetch_state;
1907
 
1908
                                        --
1909
                                        -- sync - halt execution until an interrupt is received
1910
                                        -- interrupt may be NMI, IRQ or FIRQ
1911
                                        -- program execution continues if the 
1912
                                        -- interrupt is asserted for 3 clock cycles
1913
                                        -- note that registers are not pushed onto the stack
1914
                                        -- CPU09 => Interrupts need only be asserted for one clock cycle
1915
                                        --
1916
                         when "0011" => -- sync
1917
                                          next_state   <= sync_state;
1918
 
1919
                                        --
1920
                                        -- lbra -- long branch (3 bytes)
1921
                                        -- 6809 => 5 cycles
1922
                                        -- cpu09 => 4 cycles
1923
                                        -- 1 op=(pc) / pc=pc+1
1924
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
1925
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1926
                                        -- 4 pc=pc+md
1927
                                        --
1928
                         when "0110" =>
1929
                                          -- increment the pc
1930
                 pc_ctrl    <= incr_pc;
1931 22 dilbert57
                                          next_state <= lbranch_state;
1932 19 dilbert57
 
1933
                                        --
1934
                                        -- lbsr - long branch to subroutine (3 bytes)
1935
                                        -- 6809 => 9 cycles
1936
                                        -- cpu09 => 6 cycles
1937
                                        -- 1 op=(pc) /pc=pc+1
1938
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
1939
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
1940
                                        -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
1941
                                        -- 5 (sp)=pc_hi / pc=pc
1942
                                        -- 6 pc=pc+md
1943
                                        --
1944
                         when "0111" =>
1945
                                          -- pre decrement sp
1946
                 left_ctrl  <= sp_left;
1947
                 right_ctrl <= one_right;
1948
                 alu_ctrl   <= alu_sub16;
1949
                 sp_ctrl    <= load_sp;
1950
                                          -- increment the pc
1951
                 pc_ctrl    <= incr_pc;
1952 22 dilbert57
                                          next_state <= lbranch_state;
1953 19 dilbert57
 
1954
                         when "1001" => -- daa
1955
                                          left_ctrl  <= acca_left;
1956
                      right_ctrl <= accb_right;
1957
                                          alu_ctrl   <= alu_daa;
1958
                 cc_ctrl    <= load_cc;
1959
                                          acca_ctrl  <= load_acca;
1960 22 dilbert57
                                          next_state <= fetch_state;
1961 19 dilbert57
 
1962
                         when "1010" => -- orcc
1963
                                          -- increment the pc
1964 22 dilbert57
                 pc_ctrl      <= incr_pc;
1965 19 dilbert57
                                     st_ctrl      <= push_st;
1966
                                     return_state <= fetch_state;
1967
                                          next_state   <= orcc_state;
1968
 
1969
                         when "1100" => -- andcc
1970
                                          -- increment the pc
1971 22 dilbert57
                 pc_ctrl      <= incr_pc;
1972 19 dilbert57
                                     st_ctrl      <= push_st;
1973
                                     return_state <= fetch_state;
1974
                                          next_state   <= andcc_state;
1975
 
1976
                         when "1101" => -- sex
1977
                                          -- have sex
1978
                 left_ctrl  <= accb_left;
1979
                 right_ctrl <= zero_right;
1980
                 alu_ctrl   <= alu_sex;
1981
                                          cc_ctrl    <= load_cc;
1982
                                          acca_ctrl  <= load_hi_acca;
1983 22 dilbert57
                                          next_state <= fetch_state;
1984 19 dilbert57
 
1985
                         when "1110" => -- exg
1986
                                          -- increment the pc
1987
                 pc_ctrl    <= incr_pc;
1988 22 dilbert57
                                          next_state <= exg_state;
1989 19 dilbert57
 
1990
                         when "1111" => -- tfr
1991
                                          -- increment the pc
1992 22 dilbert57
                 pc_ctrl      <= incr_pc;
1993 19 dilbert57
                                          -- call transfer as a subroutine
1994
                                     st_ctrl      <= push_st;
1995
                                     return_state <= fetch_state;
1996
                                          next_state   <= tfr_state;
1997
 
1998
                         when others =>
1999
                                          -- increment the pc
2000
                 pc_ctrl    <= incr_pc;
2001 22 dilbert57
                                          next_state <= fetch_state;
2002 19 dilbert57
                         end case;
2003
             --
2004
                                 -- Short branch conditional
2005
                                 -- 6809 => always 3 cycles
2006
                                 -- cpu09 => always = 3 cycles
2007
                                 -- 1 op=(pc) / pc=pc+1
2008
                                 -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
2009
                                 -- 3 if cc tru pc=pc+md else pc=pc
2010
                                 --
2011
                  when "0010" => -- branch conditional
2012
                                        -- increment the pc
2013
               pc_ctrl    <= incr_pc;
2014 22 dilbert57
               next_state <= sbranch_state;
2015 19 dilbert57
                                 --
2016
                                 -- Single byte stack operators
2017
                                 -- Do not advance PC
2018
                                 --
2019
                  when "0011" =>
2020
                                        --
2021
                                        -- lea - load effective address (2+ bytes)
2022
                                        -- 6809 => 4 cycles + addressing mode
2023
                                        -- cpu09 => 4 cycles + addressing mode
2024
                                        -- 1 op=(pc) / pc=pc+1
2025
                                        -- 2 md_lo=(pc) / pc=pc+1
2026
                                        -- 3 calculate ea
2027
                                        -- 4 ix/iy/sp/up = ea
2028
                                        --
2029
                    case op_code(3 downto 0) is
2030
                         when "0000" |  -- leax
2031
                              "0001" |  -- leay
2032
                              "0010" |  -- leas
2033
                              "0011" => -- leau
2034
                                                -- advance PC
2035 22 dilbert57
                  pc_ctrl      <= incr_pc;
2036 19 dilbert57
                                      st_ctrl      <= push_st;
2037
                                      return_state <= lea_state;
2038
                                                next_state   <= indexed_state;
2039
 
2040
                                        --
2041
                                        -- pshs - push registers onto sp stack
2042
                                        -- 6809 => 5 cycles + registers
2043
                                        -- cpu09 => 3 cycles + registers
2044
                                        --  1 op=(pc) / pc=pc+1
2045
                                        --  2 ea_lo=(pc) / pc=pc+1 
2046
                                        --  3 if ea(7 downto 0) != "00000000" then sp=sp-1
2047
                                        --  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
2048
                                        --  5 if ea(7) = 1 (sp)=pch
2049
                                        --    if ea(6 downto 0) != "0000000" then sp=sp-1
2050
                                        --  6 if ea(6) = 1 (sp)=upl, sp=sp-1
2051
                                        --  7 if ea(6) = 1 (sp)=uph
2052
                                        --    if ea(5 downto 0) != "000000" then sp=sp-1
2053
                                        --  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
2054
                                        --  9 if ea(5) = 1 (sp)=iyh
2055
                                        --    if ea(4 downto 0) != "00000" then sp=sp-1
2056
                                        -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
2057
                                        -- 11 if ea(4) = 1 (sp)=ixh
2058
                                        --    if ea(3 downto 0) != "0000" then sp=sp-1
2059
                                        -- 12 if ea(3) = 1 (sp)=dp
2060
                                        --    if ea(2 downto 0) != "000" then sp=sp-1
2061
                                        -- 13 if ea(2) = 1 (sp)=accb
2062
                                        --    if ea(1 downto 0) != "00" then sp=sp-1
2063
                                        -- 14 if ea(1) = 1 (sp)=acca
2064
                                        --    if ea(0 downto 0) != "0" then sp=sp-1
2065
                                        -- 15 if ea(0) = 1 (sp)=cc
2066
                                        --
2067
                         when "0100" => -- pshs
2068
                                                -- advance PC
2069
                  pc_ctrl    <= incr_pc;
2070 22 dilbert57
                                                next_state <= pshs_state;
2071 19 dilbert57
 
2072
                                        --
2073
                                        -- puls - pull registers of sp stack
2074
                                        -- 6809 => 5 cycles + registers
2075
                                        -- cpu09 => 3 cycles + registers
2076
                                        --
2077
                         when "0101" => -- puls
2078
                                                -- advance PC
2079
                  pc_ctrl    <= incr_pc;
2080 22 dilbert57
                                                next_state <= puls_state;
2081 19 dilbert57
 
2082
                                        --
2083
                                        -- pshu - push registers onto up stack
2084
                                        -- 6809 => 5 cycles + registers
2085
                                        -- cpu09 => 3 cycles + registers
2086
                                        --
2087
                         when "0110" => -- pshu
2088
                                                -- advance PC
2089
                  pc_ctrl    <= incr_pc;
2090 22 dilbert57
                                                next_state <= pshu_state;
2091 19 dilbert57
 
2092
                                        --
2093
                                        -- pulu - pull registers of up stack
2094
                                        -- 6809 => 5 cycles + registers
2095
                                        -- cpu09 => 3 cycles + registers
2096
                                        --
2097
                         when "0111" => -- pulu
2098
                                                -- advance PC
2099
                  pc_ctrl    <= incr_pc;
2100
                                                next_state <= pulu_state;
2101
 
2102
                                        --
2103
                                        -- rts - return from subroutine
2104
                                        -- 6809 => 5 cycles
2105
                                        -- cpu09 => 4 cycles 
2106
                                        -- 1 op=(pc) / pc=pc+1
2107
                                        -- 2 decode op
2108
                                        -- 3 pc_hi = (sp) / sp=sp+1
2109
                                        -- 4 pc_lo = (sp) / sp=sp+1
2110
                                        --
2111
                         when "1001" =>
2112 22 dilbert57
                                      st_ctrl      <= push_st;
2113 19 dilbert57
                                      return_state <= fetch_state;
2114 22 dilbert57
                                                next_state   <= pull_return_hi_state;
2115 19 dilbert57
 
2116
                                        --
2117
                                        -- add accb to index register
2118
                                        -- *** Note: this is an unsigned addition.
2119
                                        --           does not affect any condition codes
2120
                                        -- 6809 => 3 cycles
2121
                                        -- cpu09 => 2 cycles
2122
                                        -- 1 op=(pc) / pc=pc+1
2123
                                        -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
2124
                                        --
2125
                         when "1010" => -- abx
2126
                            left_ctrl  <= ix_left;
2127
                            right_ctrl <= accb_right;
2128
                                                alu_ctrl   <= alu_abx;
2129
                                                ix_ctrl    <= load_ix;
2130
                                                next_state <= fetch_state;
2131
 
2132
                         when "1011" => -- rti
2133
                                                next_state <= rti_cc_state;
2134
 
2135
                         when "1100" => -- cwai #$<cc_mask>
2136
                                           -- pre decrement sp
2137 22 dilbert57
                            left_ctrl    <= sp_left;
2138
                            right_ctrl   <= one_right;
2139
                                                alu_ctrl     <= alu_sub16;
2140
                                                sp_ctrl      <= load_sp;
2141
                  iv_ctrl      <= reset_iv;
2142
                                                --      increment pc
2143
                  pc_ctrl      <= incr_pc;
2144
                                      st_ctrl      <= push_st;
2145 19 dilbert57
                                      return_state <= int_entire_state; -- set entire flag
2146 22 dilbert57
                                                next_state   <= andcc_state;
2147 19 dilbert57
 
2148
                         when "1101" => -- mul
2149
                                                next_state <= mul_state;
2150
 
2151
                         when "1111" => -- swi
2152
                                           -- predecrement SP
2153
                            left_ctrl  <= sp_left;
2154
                            right_ctrl <= one_right;
2155
                                                alu_ctrl   <= alu_sub16;
2156
                                                sp_ctrl    <= load_sp;
2157
                  iv_ctrl    <= swi_iv;
2158 22 dilbert57
                                                next_state <= int_entire_state;
2159 19 dilbert57
 
2160
                         when others =>
2161
                                                next_state <= fetch_state;
2162
 
2163
                         end case;
2164
                                 --
2165
                                 -- Accumulator A Single operand
2166
                                 -- source = acca, dest = acca
2167
                                 -- Do not advance PC
2168
                                 -- Typically 2 cycles 1 bytes
2169
                                 -- 1 opcode fetch
2170
                                 -- 2 post byte fetch / instruction decode
2171
                                 -- Note that there is no post byte
2172
                                 -- so do not advance PC in decode cycle
2173
                                 -- Re-run opcode fetch cycle after decode
2174
                                 -- 
2175
                  when "0100" => -- acca single op
2176
                         left_ctrl  <= acca_left;
2177
                    case op_code(3 downto 0) is
2178
                         when "0000" => -- neg
2179
                                          right_ctrl <= zero_right;
2180
                                          alu_ctrl   <= alu_neg;
2181
                                          acca_ctrl  <= load_acca;
2182
                                          cc_ctrl    <= load_cc;
2183
                    when "0011" => -- com
2184
                           right_ctrl <= zero_right;
2185
                                          alu_ctrl   <= alu_com;
2186
                                          acca_ctrl  <= load_acca;
2187
                                          cc_ctrl    <= load_cc;
2188
                         when "0100" => -- lsr
2189
                           right_ctrl <= zero_right;
2190
                                          alu_ctrl   <= alu_lsr8;
2191
                                          acca_ctrl  <= load_acca;
2192
                                          cc_ctrl    <= load_cc;
2193
                         when "0110" => -- ror
2194
                           right_ctrl <= zero_right;
2195
                                          alu_ctrl   <= alu_ror8;
2196
                                          acca_ctrl  <= load_acca;
2197
                                          cc_ctrl    <= load_cc;
2198
                         when "0111" => -- asr
2199
                           right_ctrl <= zero_right;
2200
                                          alu_ctrl   <= alu_asr8;
2201
                                          acca_ctrl  <= load_acca;
2202
                                          cc_ctrl    <= load_cc;
2203
                         when "1000" => -- asl
2204
                           right_ctrl <= zero_right;
2205
                                          alu_ctrl   <= alu_asl8;
2206
                                          acca_ctrl  <= load_acca;
2207
                                          cc_ctrl    <= load_cc;
2208
                         when "1001" => -- rol
2209
                           right_ctrl <= zero_right;
2210
                                          alu_ctrl   <= alu_rol8;
2211
                                          acca_ctrl  <= load_acca;
2212
                                          cc_ctrl    <= load_cc;
2213
                         when "1010" => -- dec
2214
                           right_ctrl <= one_right;
2215
                                          alu_ctrl   <= alu_dec;
2216
                                          acca_ctrl  <= load_acca;
2217
                                          cc_ctrl    <= load_cc;
2218
                         when "1011" => -- undefined
2219
                           right_ctrl <= zero_right;
2220
                                          alu_ctrl   <= alu_nop;
2221
                                          acca_ctrl  <= latch_acca;
2222
                                          cc_ctrl    <= latch_cc;
2223
                         when "1100" => -- inc
2224
                           right_ctrl <= one_right;
2225
                                          alu_ctrl   <= alu_inc;
2226
                                          acca_ctrl  <= load_acca;
2227
                                          cc_ctrl    <= load_cc;
2228
                         when "1101" => -- tst
2229
                           right_ctrl <= zero_right;
2230
                                          alu_ctrl   <= alu_st8;
2231
                                          acca_ctrl  <= latch_acca;
2232
                                          cc_ctrl    <= load_cc;
2233
                         when "1110" => -- jmp (not defined)
2234
                           right_ctrl <= zero_right;
2235
                                          alu_ctrl   <= alu_nop;
2236
                                          acca_ctrl  <= latch_acca;
2237
                                          cc_ctrl    <= latch_cc;
2238
                         when "1111" => -- clr
2239
                           right_ctrl <= zero_right;
2240
                                          alu_ctrl   <= alu_clr;
2241
                                          acca_ctrl  <= load_acca;
2242
                                          cc_ctrl    <= load_cc;
2243
                         when others =>
2244
                           right_ctrl <= zero_right;
2245
                                          alu_ctrl   <= alu_nop;
2246
                                          acca_ctrl  <= latch_acca;
2247
                                          cc_ctrl    <= latch_cc;
2248
                         end case;
2249
                                   next_state <= fetch_state;
2250
                                 --
2251
                                 -- Single Operand accb
2252
                                 -- source = accb, dest = accb
2253
                                 -- Typically 2 cycles 1 bytes
2254
                                 -- 1 opcode fetch
2255
                                 -- 2 post byte fetch / instruction decode
2256
                                 -- Note that there is no post byte
2257
                                 -- so do not advance PC in decode cycle
2258
                                 -- Re-run opcode fetch cycle after decode
2259
                                 --
2260
                  when "0101" =>
2261
                         left_ctrl  <= accb_left;
2262
                    case op_code(3 downto 0) is
2263
                         when "0000" => -- neg
2264
                                          right_ctrl <= zero_right;
2265
                                          alu_ctrl   <= alu_neg;
2266
                                          accb_ctrl  <= load_accb;
2267
                                          cc_ctrl    <= load_cc;
2268
                    when "0011" => -- com
2269
                           right_ctrl <= zero_right;
2270
                                          alu_ctrl   <= alu_com;
2271
                                          accb_ctrl  <= load_accb;
2272
                                          cc_ctrl    <= load_cc;
2273
                         when "0100" => -- lsr
2274
                           right_ctrl <= zero_right;
2275
                                          alu_ctrl   <= alu_lsr8;
2276
                                          accb_ctrl  <= load_accb;
2277
                                          cc_ctrl    <= load_cc;
2278
                         when "0110" => -- ror
2279
                           right_ctrl <= zero_right;
2280
                                          alu_ctrl   <= alu_ror8;
2281
                                          accb_ctrl  <= load_accb;
2282
                                          cc_ctrl    <= load_cc;
2283
                         when "0111" => -- asr
2284
                           right_ctrl <= zero_right;
2285
                                          alu_ctrl   <= alu_asr8;
2286
                                          accb_ctrl  <= load_accb;
2287
                                          cc_ctrl    <= load_cc;
2288
                         when "1000" => -- asl
2289
                           right_ctrl <= zero_right;
2290
                                          alu_ctrl   <= alu_asl8;
2291
                                          accb_ctrl  <= load_accb;
2292
                                          cc_ctrl    <= load_cc;
2293
                         when "1001" => -- rol
2294
                           right_ctrl <= zero_right;
2295
                                          alu_ctrl   <= alu_rol8;
2296
                                          accb_ctrl  <= load_accb;
2297
                                          cc_ctrl    <= load_cc;
2298
                         when "1010" => -- dec
2299
                           right_ctrl <= one_right;
2300
                                          alu_ctrl   <= alu_dec;
2301
                                          accb_ctrl  <= load_accb;
2302
                                          cc_ctrl    <= load_cc;
2303
                         when "1011" => -- undefined
2304
                           right_ctrl <= zero_right;
2305
                                          alu_ctrl   <= alu_nop;
2306
                                          accb_ctrl  <= latch_accb;
2307
                                          cc_ctrl    <= latch_cc;
2308
                         when "1100" => -- inc
2309
                           right_ctrl <= one_right;
2310
                                          alu_ctrl   <= alu_inc;
2311
                                          accb_ctrl  <= load_accb;
2312
                                          cc_ctrl    <= load_cc;
2313
                         when "1101" => -- tst
2314
                           right_ctrl <= zero_right;
2315
                                          alu_ctrl   <= alu_st8;
2316
                                          accb_ctrl  <= latch_accb;
2317
                                          cc_ctrl    <= load_cc;
2318
                         when "1110" => -- jmp (undefined)
2319
                           right_ctrl <= zero_right;
2320
                                          alu_ctrl   <= alu_nop;
2321
                                          accb_ctrl  <= latch_accb;
2322
                                          cc_ctrl    <= latch_cc;
2323
                         when "1111" => -- clr
2324
                           right_ctrl <= zero_right;
2325
                                          alu_ctrl   <= alu_clr;
2326
                                          accb_ctrl  <= load_accb;
2327
                                          cc_ctrl    <= load_cc;
2328
                         when others =>
2329
                           right_ctrl <= zero_right;
2330
                                          alu_ctrl   <= alu_nop;
2331
                                          accb_ctrl  <= latch_accb;
2332
                                          cc_ctrl    <= latch_cc;
2333
                         end case;
2334 22 dilbert57
                                   next_state   <= fetch_state;
2335 19 dilbert57
                                 --
2336
                                 -- Single operand indexed
2337
                                 -- Two byte instruction so advance PC
2338
                                 -- EA should hold index offset
2339
                                 --
2340
                  when "0110" => -- indexed single op
2341
                                        -- increment the pc 
2342
               pc_ctrl    <= incr_pc;
2343 22 dilbert57
                                   st_ctrl    <= push_st;
2344 19 dilbert57
                                        case op_code(3 downto 0) is
2345
                                   when "1110" => -- jmp
2346
                                     return_state <= jmp_state;
2347
                                        when "1111" => -- clr
2348
                                     return_state <= single_op_exec_state;
2349
                                        when others =>
2350
                                     return_state <= single_op_read_state;
2351
                                        end case;
2352
                                   next_state <= indexed_state;
2353
             --
2354
                                 -- Single operand extended addressing
2355
                                 -- three byte instruction so advance the PC
2356
                                 -- Low order EA holds high order address
2357
                                 --
2358
                  when "0111" => -- extended single op
2359
                                        -- increment PC
2360
               pc_ctrl    <= incr_pc;
2361 22 dilbert57
                                   st_ctrl    <= push_st;
2362 19 dilbert57
                                        case op_code(3 downto 0) is
2363
                                   when "1110" => -- jmp
2364
                                     return_state <= jmp_state;
2365
                                        when "1111" => -- clr
2366
                                     return_state <= single_op_exec_state;
2367
                                        when others =>
2368
                                     return_state <= single_op_read_state;
2369
                                        end case;
2370
                                   next_state <= extended_state;
2371
 
2372
                  when "1000" => -- acca immediate
2373
                                   -- increment the pc
2374
               pc_ctrl    <= incr_pc;
2375
                                        case op_code(3 downto 0) is
2376
               when "0011" | -- subd #
2377
                                             "1100" | -- cmpx #
2378
                                             "1110" => -- ldx #
2379
                                     st_ctrl      <= push_st;
2380
                                     return_state <= fetch_state;
2381
                                          next_state   <= imm16_state;
2382
 
2383
                                        --
2384
                                        -- bsr offset - Branch to subroutine (2 bytes)
2385
                                        -- 6809 => 7 cycles
2386
                                        -- cpu09 => 5 cycles
2387
                                        -- 1 op=(pc) / pc=pc+1
2388
                                   -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
2389
                                        -- 3 (sp)=pc_lo / sp=sp-1
2390
                                        -- 4 (sp)=pc_hi
2391
                                        -- 5 pc=pc+md
2392
                                        --
2393
                                        when "1101" => -- bsr
2394
                                          -- pre decrement SP
2395
                 left_ctrl  <= sp_left;
2396
                 right_ctrl <= one_right;
2397
                 alu_ctrl   <= alu_sub16;
2398
                                     sp_ctrl    <= load_sp;
2399
                                          --
2400
                                     st_ctrl      <= push_st;
2401
                                     return_state <= sbranch_state;
2402
                                          next_state   <= push_return_lo_state;
2403
 
2404
                                        when others =>
2405
                                     next_state   <= fetch_state;
2406
               end case;
2407
 
2408
                  when "1001" => -- acca direct
2409
                                        -- increment the pc
2410
               pc_ctrl    <= incr_pc;
2411
                                        case op_code(3 downto 0) is
2412
               when "0011" | -- subd
2413
                                             "1100" | -- cmpx
2414
                                             "1110" => -- ldx
2415
                                     next_state   <= dual_op_read16_state;
2416
 
2417
                                        when "0111" =>  -- sta direct
2418 22 dilbert57
                                     next_state <= dual_op_write8_state;
2419 19 dilbert57
 
2420
                                        when "1111" => -- stx direct
2421
                                          -- idle ALU
2422
                 left_ctrl  <= ix_left;
2423
                 right_ctrl <= zero_right;
2424
                 alu_ctrl   <= alu_nop;
2425
                                          cc_ctrl    <= latch_cc;
2426
                                     sp_ctrl    <= latch_sp;
2427 22 dilbert57
                                     next_state <= dual_op_write16_state;
2428 19 dilbert57
 
2429
                                        --
2430
                                        -- jsr direct - Jump to subroutine in direct page (2 bytes)
2431
                                        -- 6809 => 7 cycles
2432
                                        -- cpu09 => 5 cycles
2433
                                        -- 1 op=(pc) / pc=pc+1
2434
                                   -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
2435
                                        -- 3 (sp)=pc_lo / sp=sp-1
2436
                                        -- 4 (sp)=pc_hi
2437
                                        -- 5 pc=ea
2438
                                        --
2439
                                        when "1101" => -- jsr direct
2440
                                          -- pre decrement sp
2441
                 left_ctrl  <= sp_left;
2442
                 right_ctrl <= one_right;
2443
                 alu_ctrl   <= alu_sub16;
2444
                                     sp_ctrl    <= load_sp;
2445
                                          --
2446
                                     st_ctrl      <= push_st;
2447
                                     return_state <= jmp_state;
2448
                                          next_state   <= push_return_lo_state;
2449
 
2450
                                        when others =>
2451
                                     next_state   <= dual_op_read8_state;
2452
               end case;
2453
 
2454
                  when "1010" => -- acca indexed
2455
                                        -- increment the pc
2456
               pc_ctrl    <= incr_pc;
2457
                                        case op_code(3 downto 0) is
2458
               when "0011" | -- subd
2459
                                             "1100" | -- cmpx
2460
                                             "1110" => -- ldx
2461 22 dilbert57
                                     st_ctrl      <= push_st;
2462 19 dilbert57
                                     return_state <= dual_op_read16_state;
2463 22 dilbert57
                                     next_state   <= indexed_state;
2464 19 dilbert57
 
2465
                                        when "0111" =>  -- staa ,x
2466
                                     st_ctrl      <= push_st;
2467
                                     return_state <= dual_op_write8_state;
2468
                                     next_state   <= indexed_state;
2469
 
2470
                                        when "1111" => -- stx ,x
2471
                                     st_ctrl      <= push_st;
2472
                                     return_state <= dual_op_write16_state;
2473
                                     next_state   <= indexed_state;
2474
 
2475
                                        when "1101" => -- jsr ,x
2476
                                          -- DO NOT pre decrement SP
2477
                                     st_ctrl      <= push_st;
2478
                                     return_state <= jsr_state;
2479
                                          next_state   <= indexed_state;
2480
 
2481
                                        when others =>
2482
                                     st_ctrl      <= push_st;
2483
                                     return_state <= dual_op_read8_state;
2484
                                     next_state   <= indexed_state;
2485
               end case;
2486
 
2487
             when "1011" => -- acca extended
2488
                                        -- increment the pc
2489
               pc_ctrl    <= incr_pc;
2490
                                        case op_code(3 downto 0) is
2491
               when "0011" | -- subd
2492
                                             "1100" | -- cmpx
2493
                                             "1110" => -- ldx
2494 22 dilbert57
                                     st_ctrl      <= push_st;
2495 19 dilbert57
                                     return_state <= dual_op_read16_state;
2496 22 dilbert57
                                     next_state   <= extended_state;
2497 19 dilbert57
 
2498
                                        when "0111" =>  -- staa >
2499
                                     st_ctrl      <= push_st;
2500
                                     return_state <= dual_op_write8_state;
2501
                                     next_state   <= extended_state;
2502
 
2503
                                        when "1111" => -- stx >
2504
                                     st_ctrl      <= push_st;
2505
                                     return_state <= dual_op_write16_state;
2506
                                     next_state   <= extended_state;
2507
 
2508
                                        when "1101" => -- jsr >extended
2509
                                          -- DO NOT pre decrement sp
2510
                                     st_ctrl      <= push_st;
2511
                                     return_state <= jsr_state;
2512
                                          next_state   <= extended_state;
2513
 
2514
                                        when others =>
2515
                                     st_ctrl      <= push_st;
2516
                                     return_state <= dual_op_read8_state;
2517
                                     next_state   <= extended_state;
2518
               end case;
2519
 
2520
                  when "1100" => -- accb immediate
2521
                                        -- increment the pc
2522
               pc_ctrl    <= incr_pc;
2523
                                        case op_code(3 downto 0) is
2524
               when "0011" | -- addd #
2525
                                             "1100" | -- ldd #
2526
                                             "1110" => -- ldu #
2527 22 dilbert57
                                     st_ctrl      <= push_st;
2528 19 dilbert57
                                     return_state <= fetch_state;
2529 22 dilbert57
                                          next_state   <= imm16_state;
2530 19 dilbert57
 
2531
                                        when others =>
2532 22 dilbert57
                                     next_state   <= fetch_state;
2533 19 dilbert57
 
2534
               end case;
2535
 
2536
 
2537
                  when "1101" => -- accb direct
2538
                                        -- increment the pc
2539
               pc_ctrl    <= incr_pc;
2540
                                        case op_code(3 downto 0) is
2541
               when "0011" | -- addd
2542
                                             "1100" | -- ldd
2543
                                             "1110" => -- ldu
2544
                                     next_state   <= dual_op_read16_state;
2545
 
2546
                                        when "0111" =>  -- stab direct
2547
                                     next_state   <= dual_op_write8_state;
2548
 
2549
                                        when "1101" =>  -- std direct
2550
                                     next_state   <= dual_op_write16_state;
2551
 
2552
                                        when "1111" => -- stu direct
2553
                                     next_state   <= dual_op_write16_state;
2554
 
2555
                                        when others =>
2556
                                     next_state   <= dual_op_read8_state;
2557
               end case;
2558
 
2559
                  when "1110" => -- accb indexed
2560
                                        -- increment the pc
2561
               pc_ctrl    <= incr_pc;
2562
                                        case op_code(3 downto 0) is
2563
               when "0011" | -- addd
2564
                                             "1100" | -- ldd
2565
                                             "1110" => -- ldu
2566 22 dilbert57
                                     st_ctrl      <= push_st;
2567 19 dilbert57
                                     return_state <= dual_op_read16_state;
2568 22 dilbert57
                                     next_state   <= indexed_state;
2569 19 dilbert57
 
2570
                                        when "0111" =>  -- stab indexed
2571
                                     st_ctrl      <= push_st;
2572
                                     return_state <= dual_op_write8_state;
2573
                                     next_state   <= indexed_state;
2574
 
2575
                                        when "1101" =>  -- std indexed
2576
                                     st_ctrl      <= push_st;
2577
                                     return_state <= dual_op_write16_state;
2578
                                     next_state   <= indexed_state;
2579
 
2580
                                        when "1111" => -- stu indexed
2581
                                     st_ctrl      <= push_st;
2582
                                     return_state <= dual_op_write16_state;
2583
                                     next_state   <= indexed_state;
2584
 
2585
                                        when others =>
2586
                                     st_ctrl      <= push_st;
2587
                                     return_state <= dual_op_read8_state;
2588
                                     next_state   <= indexed_state;
2589
               end case;
2590
 
2591
             when "1111" => -- accb extended
2592
                                        -- increment the pc
2593
               pc_ctrl    <= incr_pc;
2594
                                        case op_code(3 downto 0) is
2595
               when "0011" | -- addd
2596
                                             "1100" | -- ldd
2597
                                             "1110" => -- ldu
2598
                                     st_ctrl      <= push_st;
2599
                                     return_state <= dual_op_read16_state;
2600
                                     next_state   <= extended_state;
2601
 
2602
                                        when "0111" =>  -- stab extended
2603
                                     st_ctrl      <= push_st;
2604
                                     return_state <= dual_op_write8_state;
2605
                                     next_state   <= extended_state;
2606
 
2607
                                        when "1101" =>  -- std extended
2608
                                     st_ctrl      <= push_st;
2609
                                     return_state <= dual_op_write16_state;
2610
                                     next_state   <= extended_state;
2611
 
2612
                                        when "1111" => -- stu  extended
2613
                                     st_ctrl      <= push_st;
2614
                                     return_state <= dual_op_write16_state;
2615
                                     next_state   <= extended_state;
2616
 
2617
                                        when others =>
2618
                                     st_ctrl      <= push_st;
2619
                                     return_state <= dual_op_read8_state;
2620
                                     next_state   <= extended_state;
2621
               end case;
2622
 
2623
                  when others =>
2624
                                   null;
2625
             end case;
2626
 
2627
                         --
2628
                         -- Here to decode prefix 2 instruction
2629
                         -- and fetch next byte of intruction
2630
                         -- whether it be necessary or not
2631
                         --
2632
          when decode2_state =>
2633
                                 -- fetch first byte of address or immediate data
2634
             ea_ctrl    <= fetch_first_ea;
2635
                                 md_ctrl    <= fetch_first_md;
2636
             addr_ctrl  <= fetch_ad;
2637
                            case op_code(7 downto 4) is
2638
                                 --
2639
                                 -- lbcc -- long branch conditional
2640
                                 -- 6809 => branch 6 cycles, no branch 5 cycles
2641
                                 -- cpu09 => always 5 cycles
2642
                                 -- 1 pre=(pc) / pc=pc+1
2643
                                 -- 2 op=(pc) / pc=pc+1
2644
                                 -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
2645
             -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
2646
                                 -- 5 if cond pc=pc+md else pc=pc
2647
                                 --
2648
                  when "0010" =>
2649
                                        -- increment the pc
2650
               pc_ctrl    <= incr_pc;
2651 22 dilbert57
                                        next_state <= lbranch_state;
2652 19 dilbert57
 
2653
                                 --
2654
                                 -- Single byte stack operators
2655
                                 -- Do not advance PC
2656
                                 --
2657
                  when "0011" =>
2658
                    case op_code(3 downto 0) is
2659
                         when "1111" => -- swi 2
2660
                                           -- predecrement sp
2661
                            left_ctrl  <= sp_left;
2662
                            right_ctrl <= one_right;
2663
                                                alu_ctrl   <= alu_sub16;
2664
                                                sp_ctrl    <= load_sp;
2665
                  iv_ctrl    <= swi2_iv;
2666 22 dilbert57
                                                next_state <= int_entire_state;
2667 19 dilbert57
 
2668
                         when others =>
2669
                                                next_state   <= fetch_state;
2670
                         end case;
2671
 
2672
                  when "1000" => -- acca immediate
2673
                                   -- increment the pc
2674
               pc_ctrl    <= incr_pc;
2675
                                        case op_code(3 downto 0) is
2676
               when "0011" | -- cmpd #
2677
                                             "1100" | -- cmpy #
2678
                                             "1110" => -- ldy #
2679
                                     st_ctrl      <= push_st;
2680
                                     return_state <= fetch_state;
2681
                                          next_state   <= imm16_state;
2682
 
2683
                                        when others =>
2684
                                     next_state   <= fetch_state;
2685
 
2686
               end case;
2687
 
2688
                  when "1001" => -- acca direct
2689
                                        -- increment the pc
2690
               pc_ctrl    <= incr_pc;
2691
                                        case op_code(3 downto 0) is
2692
               when "0011" | -- cmpd <
2693
                                             "1100" | -- cmpy <
2694
                                             "1110" => -- ldy <
2695
                                          next_state   <= dual_op_read16_state;
2696
 
2697
                                        when "1111" => -- sty <
2698
                                     next_state   <= dual_op_write16_state;
2699
 
2700
                                        when others =>
2701
                                     next_state   <= fetch_state;
2702
 
2703
               end case;
2704
 
2705
                  when "1010" => -- acca indexed
2706
                                        -- increment the pc
2707
               pc_ctrl    <= incr_pc;
2708
                                        case op_code(3 downto 0) is
2709
               when "0011" | -- cmpd ,ind
2710
                                             "1100" | -- cmpy ,ind
2711
                                             "1110" => -- ldy ,ind
2712
                                     st_ctrl      <= push_st;
2713
                                     return_state <= dual_op_read16_state;
2714
                                          next_state   <= indexed_state;
2715
 
2716
                                        when "1111" => -- sty ,ind
2717
                                     st_ctrl      <= push_st;
2718
                                     return_state <= dual_op_write16_state;
2719
                                     next_state   <= indexed_state;
2720
 
2721
                                        when others =>
2722
                                     next_state   <= fetch_state;
2723
               end case;
2724
 
2725
             when "1011" => -- acca extended
2726
                                        -- increment the pc
2727
               pc_ctrl    <= incr_pc;
2728
                                        case op_code(3 downto 0) is
2729
               when "0011" | -- cmpd <
2730
                                             "1100" | -- cmpy <
2731
                                             "1110" => -- ldy <
2732
                                     st_ctrl      <= push_st;
2733
                                     return_state <= dual_op_read16_state;
2734
                                          next_state   <= extended_state;
2735
 
2736
                                        when "1111" => -- sty >
2737
                                     st_ctrl      <= push_st;
2738
                                     return_state <= dual_op_write16_state;
2739
                                     next_state   <= extended_state;
2740
 
2741
                                        when others =>
2742
                                     next_state   <= fetch_state;
2743
 
2744
               end case;
2745
 
2746
                  when "1100" => -- accb immediate
2747
                                        -- increment the pc
2748
               pc_ctrl    <= incr_pc;
2749
                                        case op_code(3 downto 0) is
2750
               when "0011" | -- undef #
2751
                                             "1100" | -- undef #
2752
                                             "1110" => -- lds #
2753
                                     st_ctrl      <= push_st;
2754
                                     return_state <= fetch_state;
2755
                                          next_state   <= imm16_state;
2756
 
2757
                                        when others =>
2758
                                     next_state   <= fetch_state;
2759
 
2760
               end case;
2761
 
2762
                  when "1101" => -- accb direct
2763
                                        -- increment the pc
2764
               pc_ctrl    <= incr_pc;
2765
                                        case op_code(3 downto 0) is
2766
               when "0011" | -- undef <
2767
                                             "1100" | -- undef <
2768
                                             "1110" => -- lds <
2769
                                          next_state   <= dual_op_read16_state;
2770
 
2771
                                        when "1111" => -- sts <
2772
                                     next_state   <= dual_op_write16_state;
2773
 
2774
                                        when others =>
2775
                                     next_state   <= fetch_state;
2776
 
2777
               end case;
2778
 
2779
                  when "1110" => -- accb indexed
2780
                                        -- increment the pc
2781
               pc_ctrl    <= incr_pc;
2782
                                        case op_code(3 downto 0) is
2783
               when "0011" | -- undef ,ind
2784
                                             "1100" | -- undef ,ind
2785
                                             "1110" => -- lds ,ind
2786
                                     st_ctrl      <= push_st;
2787
                                     return_state <= dual_op_read16_state;
2788
                                          next_state   <= indexed_state;
2789
 
2790
                                        when "1111" => -- sts ,ind
2791
                                     st_ctrl      <= push_st;
2792
                                     return_state <= dual_op_write16_state;
2793
                                     next_state   <= indexed_state;
2794
 
2795
                                        when others =>
2796
                                     next_state   <= fetch_state;
2797
 
2798
               end case;
2799
 
2800
             when "1111" => -- accb extended
2801
                                        -- increment the pc
2802
               pc_ctrl    <= incr_pc;
2803
                                        case op_code(3 downto 0) is
2804
               when "0011" | -- undef >
2805
                                             "1100" | -- undef >
2806
                                             "1110" => -- lds >
2807
                                     st_ctrl      <= push_st;
2808
                                     return_state <= dual_op_read16_state;
2809
                                          next_state   <= extended_state;
2810
 
2811
                                        when "1111" => -- sts >
2812
                                     st_ctrl      <= push_st;
2813
                                     return_state <= dual_op_write16_state;
2814
                                     next_state   <= extended_state;
2815
 
2816
                                        when others =>
2817
                                     next_state   <= fetch_state;
2818
               end case;
2819
 
2820
                  when others =>
2821
                         next_state   <= fetch_state;
2822
             end case;
2823
                         --
2824
                         -- Here to decode instruction
2825
                         -- and fetch next byte of intruction
2826
                         -- whether it be necessary or not
2827
                         --
2828
          when decode3_state =>
2829
             ea_ctrl    <= fetch_first_ea;
2830
                                 md_ctrl    <= fetch_first_md;
2831
             addr_ctrl  <= fetch_ad;
2832
             dout_ctrl  <= md_lo_dout;
2833
                            case op_code(7 downto 4) is
2834
                                 --
2835
                                 -- Single byte stack operators
2836
                                 -- Do not advance PC
2837
                                 --
2838
                  when "0011" =>
2839
                    case op_code(3 downto 0) is
2840
                         when "1111" => -- swi3
2841
                                           -- predecrement sp
2842
                            left_ctrl  <= sp_left;
2843
                            right_ctrl <= one_right;
2844
                                                alu_ctrl   <= alu_sub16;
2845
                                                sp_ctrl    <= load_sp;
2846
                  iv_ctrl    <= swi3_iv;
2847 22 dilbert57
                                                next_state <= int_entire_state;
2848 19 dilbert57
                         when others =>
2849
                                                next_state   <= fetch_state;
2850
                         end case;
2851
 
2852
                  when "1000" => -- acca immediate
2853
                                   -- increment the pc
2854
               pc_ctrl    <= incr_pc;
2855
                                        case op_code(3 downto 0) is
2856
               when "0011" | -- cmpu #
2857
                                             "1100" | -- cmps #
2858
                                             "1110" => -- undef #
2859
                                     st_ctrl      <= push_st;
2860
                                     return_state <= fetch_state;
2861
                                          next_state   <= imm16_state;
2862
                                        when others =>
2863
                                     next_state   <= fetch_state;
2864
               end case;
2865
 
2866
                  when "1001" => -- acca direct
2867
                                        -- increment the pc
2868
               pc_ctrl    <= incr_pc;
2869
                                        case op_code(3 downto 0) is
2870
               when "0011" | -- cmpu <
2871
                                             "1100" | -- cmps <
2872
                                             "1110" => -- undef <
2873
                                     st_ctrl      <= idle_st;
2874
                                     return_state <= fetch_state;
2875
                                          next_state   <= dual_op_read16_state;
2876
 
2877
                                        when others =>
2878
                                     next_state   <= fetch_state;
2879
 
2880
               end case;
2881
 
2882
                  when "1010" => -- acca indexed
2883
                                        -- increment the pc
2884
               pc_ctrl    <= incr_pc;
2885
                                        case op_code(3 downto 0) is
2886
               when "0011" | -- cmpu ,X
2887
                                             "1100" | -- cmps ,X
2888
                                             "1110" => -- undef ,X
2889
                                     st_ctrl      <= push_st;
2890
                                     return_state <= dual_op_read16_state;
2891
                                          next_state   <= indexed_state;
2892
 
2893
                                        when others =>
2894
                                     next_state   <= fetch_state;
2895
 
2896
               end case;
2897
 
2898
             when "1011" => -- acca extended
2899
                                        -- increment the pc
2900
               pc_ctrl    <= incr_pc;
2901
                                        case op_code(3 downto 0) is
2902
               when "0011" | -- cmpu >
2903
                                             "1100" | -- cmps >
2904
                                             "1110" => -- undef >
2905
                                     st_ctrl      <= push_st;
2906
                                     return_state <= dual_op_read16_state;
2907
                                          next_state   <= extended_state;
2908
                                        when others =>
2909
                                     next_state   <= fetch_state;
2910
               end case;
2911
 
2912
                  when others =>
2913
                         next_state   <= fetch_state;
2914
             end case;
2915
 
2916
           --
2917
                          -- here if ea holds low byte
2918
                          -- Direct
2919
                          -- Extended
2920
                          -- Indexed
2921
                          -- read memory location
2922
                          --
2923
                          when single_op_read_state =>
2924
                                        -- read memory into md
2925
                                   md_ctrl    <= fetch_first_md;
2926
               addr_ctrl  <= read_ad;
2927
                                        dout_ctrl  <= md_lo_dout;
2928
                                        next_state <= single_op_exec_state;
2929
 
2930
                when single_op_exec_state =>
2931
                    case op_code(3 downto 0) is
2932
                         when "0000" => -- neg
2933
                   left_ctrl  <= md_left;
2934
                                            right_ctrl <= zero_right;
2935
                                            alu_ctrl   <= alu_neg;
2936
                                            cc_ctrl    <= load_cc;
2937
                                       md_ctrl    <= load_md;
2938
                                       next_state <= single_op_write_state;
2939
                    when "0011" => -- com
2940
                   left_ctrl  <= md_left;
2941
                             right_ctrl <= zero_right;
2942
                                            alu_ctrl   <= alu_com;
2943
                                            cc_ctrl    <= load_cc;
2944
                                       md_ctrl    <= load_md;
2945
                                       next_state <= single_op_write_state;
2946
                         when "0100" => -- lsr
2947
                   left_ctrl  <= md_left;
2948
                                                 right_ctrl <= zero_right;
2949
                                            alu_ctrl   <= alu_lsr8;
2950
                                            cc_ctrl    <= load_cc;
2951
                                       md_ctrl    <= load_md;
2952
                                       next_state <= single_op_write_state;
2953
                         when "0110" => -- ror
2954
                   left_ctrl  <= md_left;
2955
                                                 right_ctrl <= zero_right;
2956
                                            alu_ctrl   <= alu_ror8;
2957
                                            cc_ctrl    <= load_cc;
2958
                                       md_ctrl    <= load_md;
2959
                                       next_state <= single_op_write_state;
2960
                         when "0111" => -- asr
2961
                   left_ctrl  <= md_left;
2962
                                                 right_ctrl <= zero_right;
2963
                                            alu_ctrl   <= alu_asr8;
2964
                                            cc_ctrl    <= load_cc;
2965
                                       md_ctrl    <= load_md;
2966
                                       next_state <= single_op_write_state;
2967
                         when "1000" => -- asl
2968
                   left_ctrl  <= md_left;
2969
                                                 right_ctrl <= zero_right;
2970
                                            alu_ctrl   <= alu_asl8;
2971
                                            cc_ctrl    <= load_cc;
2972
                                       md_ctrl    <= load_md;
2973
                                       next_state <= single_op_write_state;
2974
                         when "1001" => -- rol
2975
                   left_ctrl  <= md_left;
2976
                                                 right_ctrl <= zero_right;
2977
                                            alu_ctrl   <= alu_rol8;
2978
                                            cc_ctrl    <= load_cc;
2979
                                       md_ctrl    <= load_md;
2980
                                       next_state <= single_op_write_state;
2981
                         when "1010" => -- dec
2982
                   left_ctrl  <= md_left;
2983
                             right_ctrl <= one_right;
2984
                                            alu_ctrl   <= alu_dec;
2985
                                            cc_ctrl    <= load_cc;
2986
                                       md_ctrl    <= load_md;
2987
                                       next_state <= single_op_write_state;
2988
                         when "1011" => -- undefined
2989
                                       next_state <= fetch_state;
2990
                         when "1100" => -- inc
2991
                   left_ctrl  <= md_left;
2992
                             right_ctrl <= one_right;
2993
                                            alu_ctrl   <= alu_inc;
2994
                                            cc_ctrl    <= load_cc;
2995
                                       md_ctrl    <= load_md;
2996
                                       next_state <= single_op_write_state;
2997
                         when "1101" => -- tst
2998
                   left_ctrl  <= md_left;
2999
                             right_ctrl <= zero_right;
3000
                                            alu_ctrl   <= alu_st8;
3001
                                            cc_ctrl    <= load_cc;
3002
                                       next_state <= fetch_state;
3003
                         when "1110" => -- jmp
3004
                   left_ctrl  <= md_left;
3005
                                                 right_ctrl <= zero_right;
3006
                                            alu_ctrl   <= alu_ld16;
3007
                   pc_ctrl    <= load_pc;
3008
                                       next_state <= fetch_state;
3009
                         when "1111" => -- clr
3010
                   left_ctrl  <= md_left;
3011
                                                 right_ctrl <= zero_right;
3012
                                            alu_ctrl   <= alu_clr;
3013
                                            cc_ctrl    <= load_cc;
3014
                                       md_ctrl    <= load_md;
3015
                                       next_state <= single_op_write_state;
3016
                         when others =>
3017
                                       next_state <= fetch_state;
3018
                         end case;
3019
           --
3020
                          -- single operand 8 bit write
3021
                          -- Write low 8 bits of ALU output
3022
                          -- EA holds address
3023
                          -- MD holds data
3024
                          --
3025
                          when single_op_write_state =>
3026
                                 -- write ALU low byte output
3027
             addr_ctrl  <= write_ad;
3028
             dout_ctrl  <= md_lo_dout;
3029
                                 next_state <= fetch_state;
3030
 
3031
           --
3032
                          -- here if ea holds address of low byte
3033
                          -- read memory location
3034
                          --
3035
                          when dual_op_read8_state =>
3036
                                   -- read first data byte from ea
3037
                                   md_ctrl    <= fetch_first_md;
3038
               addr_ctrl  <= read_ad;
3039 22 dilbert57
                                        next_state <= fetch_state;
3040 19 dilbert57
 
3041
                                --
3042
                                -- Here to read a 16 bit value into MD
3043
                                -- pointed to by the EA register
3044
                                -- The first byte is read
3045
                                -- and the EA is incremented
3046
                                --
3047
                           when dual_op_read16_state =>
3048
                                        -- increment the effective address
3049
               left_ctrl  <= ea_left;
3050
               right_ctrl <= one_right;
3051
               alu_ctrl   <= alu_add16;
3052
               ea_ctrl    <= load_ea;
3053 22 dilbert57
                                        -- read the high byte of the 16 bit data
3054 19 dilbert57
                                   md_ctrl    <= fetch_first_md;
3055
               addr_ctrl  <= read_ad;
3056 22 dilbert57
                                        next_state <= dual_op_read16_2_state;
3057 19 dilbert57
 
3058
                                --
3059
                                -- here to read the second byte
3060
                           -- pointed to by EA into MD
3061
                                --
3062
                           when dual_op_read16_2_state =>
3063
                                        -- read the low byte of the 16 bit data
3064
                                   md_ctrl    <= fetch_next_md;
3065
               addr_ctrl  <= read_ad;
3066 22 dilbert57
                                        next_state <= fetch_state;
3067 19 dilbert57
 
3068
           --
3069
                          -- 16 bit Write state
3070
                          -- EA hold address of memory to write to
3071
                          -- Advance the effective address in ALU
3072
                          -- decode op_code to determine which
3073
                          -- register to write
3074
                          --
3075
                          when dual_op_write16_state =>
3076
                                 -- increment the effective address
3077
                                 left_ctrl  <= ea_left;
3078
                                 right_ctrl <= one_right;
3079
                                 alu_ctrl   <= alu_add16;
3080
                            ea_ctrl    <= load_ea;
3081
                                 -- write the ALU hi byte at ea
3082
             addr_ctrl  <= write_ad;
3083
                                 if op_code(6) = '0' then
3084
                                   case op_code(3 downto 0) is
3085 22 dilbert57
                              when "1111" => -- stx / sty
3086 19 dilbert57
                                          case pre_code is
3087
                                          when "00010000" => -- page 2 -- sty
3088
                        dout_ctrl  <= iy_hi_dout;
3089
                                     when others =>     -- page 1 -- stx
3090
                   dout_ctrl  <= ix_hi_dout;
3091
                                          end case;
3092 22 dilbert57
                                   when others =>
3093 19 dilbert57
                 dout_ctrl  <= md_hi_dout;
3094 22 dilbert57
                                   end case;
3095
             else
3096 19 dilbert57
                                   case op_code(3 downto 0) is
3097 22 dilbert57
                              when "1101" => -- std
3098 19 dilbert57
                 dout_ctrl  <= acca_dout; -- acca is high byte of ACCD
3099 22 dilbert57
                              when "1111" => -- stu / sts
3100 19 dilbert57
                                          case pre_code is
3101
                                          when "00010000" => -- page 2 -- sts
3102
                        dout_ctrl  <= sp_hi_dout;
3103
                                          when others =>     -- page 1 -- stu
3104
                        dout_ctrl  <= up_hi_dout;
3105
                                          end case;
3106 22 dilbert57
                                   when others =>
3107 19 dilbert57
                 dout_ctrl  <= md_hi_dout;
3108 22 dilbert57
                                   end case;
3109
             end if;
3110 19 dilbert57
                                 next_state   <= dual_op_write8_state;
3111
 
3112
           --
3113
                          -- Dual operand 8 bit write
3114
           -- Write 8 bit accumulator
3115
                          -- or low byte of 16 bit register
3116
                          -- EA holds address
3117
                          -- decode opcode to determine
3118
                          -- which register to apply to the bus
3119
                          -- Also set the condition codes here
3120
                          --
3121
                          when dual_op_write8_state =>
3122 22 dilbert57
                            if op_code(6) = '0' then
3123 19 dilbert57
                                   case op_code(3 downto 0) is
3124
                                        when "0111" => -- sta
3125
                 dout_ctrl  <= acca_dout;
3126
                                        when "1111" => -- stx / sty
3127
                                          case pre_code is
3128
                                          when "00010000" => -- page 2 -- sty
3129
                        dout_ctrl  <= iy_lo_dout;
3130
                                     when others =>     -- page 1 -- stx
3131
                   dout_ctrl  <= ix_lo_dout;
3132
                                          end case;
3133
                                        when others =>
3134
                 dout_ctrl  <= md_lo_dout;
3135
                                        end case;
3136 22 dilbert57
             else
3137 19 dilbert57
                                   case op_code(3 downto 0) is
3138
                                        when "0111" => -- stb
3139
                 dout_ctrl  <= accb_dout;
3140
                                        when "1101" => -- std
3141
                 dout_ctrl  <= accb_dout; -- accb is low byte of accd
3142
                                        when "1111" => -- stu / sts
3143
                                          case pre_code is
3144
                                          when "00010000" => -- page 2 -- sts
3145
                        dout_ctrl  <= sp_lo_dout;
3146
                                          when others =>     -- page 1 -- stu
3147
                        dout_ctrl  <= up_lo_dout;
3148
                                          end case;
3149
                                        when others =>
3150
                 dout_ctrl  <= md_lo_dout;
3151
                                        end case;
3152 22 dilbert57
             end if;
3153 19 dilbert57
                                 -- write ALU low byte output
3154
             addr_ctrl    <= write_ad;
3155
                                 next_state   <= fetch_state;
3156
 
3157
                          --
3158
                          -- 16 bit immediate addressing mode
3159
                          --
3160
                          when imm16_state =>
3161
                                   -- increment pc
3162
               pc_ctrl    <= incr_pc;
3163
                                   -- fetch next immediate byte
3164
                              md_ctrl    <= fetch_next_md;
3165
               addr_ctrl  <= fetch_ad;
3166 22 dilbert57
                                        st_ctrl    <= pull_st;
3167
                                        next_state <= saved_state;
3168 19 dilbert57
 
3169
           --
3170
                          -- md & ea holds 8 bit index offset
3171
                          -- calculate the effective memory address
3172
                          -- using the alu
3173
                          --
3174
           when indexed_state =>
3175
                                 --
3176
                                 -- decode indexing mode
3177
                                 --
3178
                                 if md(7) = '0' then
3179
                                   case md(6 downto 5) is
3180
                                        when "00" =>
3181
                                left_ctrl  <= ix_left;
3182
                                        when "01" =>
3183
                                left_ctrl  <= iy_left;
3184
                                        when "10" =>
3185
                                left_ctrl  <= up_left;
3186
                                        when others =>
3187
                                        -- when "11" =>
3188
                                left_ctrl  <= sp_left;
3189
                                        end case;
3190 22 dilbert57
                                   right_ctrl   <= md_sign5_right;
3191
                                   alu_ctrl     <= alu_add16;
3192
               ea_ctrl      <= load_ea;
3193 19 dilbert57
                                        st_ctrl      <= pull_st;
3194
                                        next_state   <= saved_state;
3195
 
3196
                                 else
3197
                                   case md(3 downto 0) is
3198
                                        when "0000" =>     -- ,R+
3199
                                     case md(6 downto 5) is
3200
                                          when "00" =>
3201
                                  left_ctrl  <= ix_left;
3202
                                          when "01" =>
3203
                                  left_ctrl  <= iy_left;
3204
                                          when "10" =>
3205
                                  left_ctrl  <= up_left;
3206
                                          when others =>
3207
                                  left_ctrl  <= sp_left;
3208
                                          end case;
3209
                                          --
3210
                                     right_ctrl <= zero_right;
3211 22 dilbert57
                                     alu_ctrl   <= alu_add16;
3212 19 dilbert57
                 ea_ctrl    <= load_ea;
3213 22 dilbert57
                 next_state <= postincr1_state;
3214 19 dilbert57
 
3215
                                        when "0001" =>     -- ,R++
3216
                                     case md(6 downto 5) is
3217
                                          when "00" =>
3218
                                  left_ctrl  <= ix_left;
3219
                                          when "01" =>
3220
                                  left_ctrl  <= iy_left;
3221
                                          when "10" =>
3222
                                  left_ctrl  <= up_left;
3223
                                          when others =>
3224
                                          -- when "11" =>
3225
                                  left_ctrl  <= sp_left;
3226
                                          end case;
3227
                                     right_ctrl <= zero_right;
3228 22 dilbert57
                                     alu_ctrl   <= alu_add16;
3229 19 dilbert57
                 ea_ctrl    <= load_ea;
3230 22 dilbert57
                 next_state <= postincr2_state;
3231 19 dilbert57
 
3232
                                        when "0010" =>     -- ,-R
3233
                                     case md(6 downto 5) is
3234
                                          when "00" =>
3235
                                  left_ctrl  <= ix_left;
3236
                   ix_ctrl    <= load_ix;
3237
                                          when "01" =>
3238
                                  left_ctrl  <= iy_left;
3239
                   iy_ctrl    <= load_iy;
3240
                                          when "10" =>
3241
                                  left_ctrl  <= up_left;
3242
                   up_ctrl    <= load_up;
3243
                                          when others =>
3244
                                          -- when "11" =>
3245
                                  left_ctrl  <= sp_left;
3246
                   sp_ctrl    <= load_sp;
3247
                                          end case;
3248 22 dilbert57
                                     right_ctrl   <= one_right;
3249
                                     alu_ctrl     <= alu_sub16;
3250
                 ea_ctrl      <= load_ea;
3251 19 dilbert57
                                          st_ctrl      <= pull_st;
3252
                                          next_state   <= saved_state;
3253
 
3254
                                        when "0011" =>     -- ,--R
3255
                                     case md(6 downto 5) is
3256
                                          when "00" =>
3257
                                  left_ctrl  <= ix_left;
3258
                   ix_ctrl    <= load_ix;
3259
                                          when "01" =>
3260
                                  left_ctrl  <= iy_left;
3261
                   iy_ctrl    <= load_iy;
3262
                                          when "10" =>
3263
                                  left_ctrl  <= up_left;
3264
                   up_ctrl    <= load_up;
3265
                                          when others =>
3266
                                          -- when "11" =>
3267
                                  left_ctrl  <= sp_left;
3268
                   sp_ctrl    <= load_sp;
3269
                                          end case;
3270
                                     right_ctrl <= two_right;
3271
                                     alu_ctrl   <= alu_sub16;
3272
                 ea_ctrl    <= load_ea;
3273
                                          if md(4) = '0' then
3274
                                            st_ctrl      <= pull_st;
3275
                                            next_state   <= saved_state;
3276
                                          else
3277
                                            next_state   <= indirect_state;
3278
                                          end if;
3279
 
3280
                                        when "0100" =>     -- ,R (zero offset)
3281
                                     case md(6 downto 5) is
3282
                                          when "00" =>
3283
                                  left_ctrl  <= ix_left;
3284
                                          when "01" =>
3285
                                  left_ctrl  <= iy_left;
3286
                                          when "10" =>
3287
                                  left_ctrl  <= up_left;
3288
                                          when others =>
3289
                                          -- when "11" =>
3290
                                  left_ctrl  <= sp_left;
3291
                                          end case;
3292
                                     right_ctrl <= zero_right;
3293 22 dilbert57
                                     alu_ctrl   <= alu_add16;
3294 19 dilbert57
                 ea_ctrl    <= load_ea;
3295
                                          if md(4) = '0' then
3296
                                            st_ctrl      <= pull_st;
3297
                                            next_state   <= saved_state;
3298
                                          else
3299
                                            next_state   <= indirect_state;
3300
                                          end if;
3301
 
3302
                                        when "0101" =>     -- ACCB,R
3303
                                     case md(6 downto 5) is
3304
                                          when "00" =>
3305
                                  left_ctrl  <= ix_left;
3306
                                          when "01" =>
3307
                                  left_ctrl  <= iy_left;
3308
                                          when "10" =>
3309
                                  left_ctrl  <= up_left;
3310
                                          when others =>
3311
                                          -- when "11" =>
3312
                                  left_ctrl  <= sp_left;
3313
                                          end case;
3314
                                     right_ctrl <= accb_right;
3315
                                     alu_ctrl   <= alu_add16;
3316
                 ea_ctrl    <= load_ea;
3317
                                          if md(4) = '0' then
3318
                                            st_ctrl      <= pull_st;
3319
                                            next_state   <= saved_state;
3320
                                          else
3321
                                            next_state   <= indirect_state;
3322
                                          end if;
3323
 
3324
                                        when "0110" =>     -- ACCA,R
3325
                                     case md(6 downto 5) is
3326
                                          when "00" =>
3327
                                  left_ctrl  <= ix_left;
3328
                                          when "01" =>
3329
                                  left_ctrl  <= iy_left;
3330
                                          when "10" =>
3331
                                  left_ctrl  <= up_left;
3332
                                          when others =>
3333
                                          -- when "11" =>
3334
                                  left_ctrl  <= sp_left;
3335
                                          end case;
3336
                                     right_ctrl <= acca_right;
3337
                                     alu_ctrl   <= alu_add16;
3338
                 ea_ctrl    <= load_ea;
3339
                                          if md(4) = '0' then
3340
                                            st_ctrl      <= pull_st;
3341
                                            next_state   <= saved_state;
3342
                                          else
3343
                                            next_state   <= indirect_state;
3344
                                          end if;
3345
 
3346
                                        when "0111" =>     -- undefined
3347
                                     case md(6 downto 5) is
3348
                                          when "00" =>
3349
                                  left_ctrl  <= ix_left;
3350
                                          when "01" =>
3351
                                  left_ctrl  <= iy_left;
3352
                                          when "10" =>
3353
                                  left_ctrl  <= up_left;
3354
                                          when others =>
3355
                                          -- when "11" =>
3356
                                  left_ctrl  <= sp_left;
3357
                                          end case;
3358
                                     right_ctrl <= zero_right;
3359 22 dilbert57
                                     alu_ctrl   <= alu_add16;
3360
                 ea_ctrl    <= load_ea;
3361 19 dilbert57
                                          if md(4) = '0' then
3362
                                            st_ctrl      <= pull_st;
3363
                                            next_state   <= saved_state;
3364
                                          else
3365
                                            next_state   <= indirect_state;
3366
                                          end if;
3367
 
3368
                                        when "1000" =>     -- offset8,R
3369
                 md_ctrl    <= fetch_first_md; -- pick up 8 bit offset
3370
                 addr_ctrl  <= fetch_ad;
3371
                 pc_ctrl    <= incr_pc;
3372 22 dilbert57
                 next_state <= index8_state;
3373 19 dilbert57
 
3374
                                        when "1001" =>     -- offset16,R
3375
                 md_ctrl    <= fetch_first_md; -- pick up first byte of 16 bit offset
3376
                 addr_ctrl  <= fetch_ad;
3377
                 pc_ctrl    <= incr_pc;
3378 22 dilbert57
                 next_state <= index16_state;
3379 19 dilbert57
 
3380
                                        when "1010" =>     -- undefined
3381
                                     case md(6 downto 5) is
3382
                                          when "00" =>
3383
                                  left_ctrl  <= ix_left;
3384
                                          when "01" =>
3385
                                  left_ctrl  <= iy_left;
3386
                                          when "10" =>
3387
                                  left_ctrl  <= up_left;
3388
                                          when others =>
3389
                                          -- when "11" =>
3390
                                  left_ctrl  <= sp_left;
3391
                                          end case;
3392
                                     right_ctrl <= zero_right;
3393 22 dilbert57
                                     alu_ctrl   <= alu_add16;
3394
                 ea_ctrl    <= load_ea;
3395 19 dilbert57
                                          --
3396
                                          if md(4) = '0' then
3397
                                            st_ctrl      <= pull_st;
3398
                                            next_state   <= saved_state;
3399
                                          else
3400
                                            next_state   <= indirect_state;
3401
                                          end if;
3402
 
3403
                                        when "1011" =>     -- ACCD,R
3404
                                     case md(6 downto 5) is
3405
                                          when "00" =>
3406
                                  left_ctrl  <= ix_left;
3407
                                          when "01" =>
3408
                                  left_ctrl  <= iy_left;
3409
                                          when "10" =>
3410
                                  left_ctrl  <= up_left;
3411
                                          when others =>
3412
                                          -- when "11" =>
3413
                                  left_ctrl  <= sp_left;
3414
                                          end case;
3415
                                     right_ctrl <= accd_right;
3416
                                     alu_ctrl   <= alu_add16;
3417
                 ea_ctrl    <= load_ea;
3418
                                          if md(4) = '0' then
3419
                                            st_ctrl      <= pull_st;
3420
                                            next_state   <= saved_state;
3421
                                          else
3422
                                            next_state   <= indirect_state;
3423
                                          end if;
3424
 
3425
                                        when "1100" =>     -- offset8,PC
3426
                                          -- fetch 8 bit offset
3427
                 md_ctrl    <= fetch_first_md;
3428
                 addr_ctrl  <= fetch_ad;
3429
                 pc_ctrl    <= incr_pc;
3430 22 dilbert57
                 next_state <= pcrel8_state;
3431 19 dilbert57
 
3432
                                        when "1101" =>     -- offset16,PC
3433
                                          -- fetch offset
3434
                 md_ctrl    <= fetch_first_md;
3435
                 addr_ctrl  <= fetch_ad;
3436
                 pc_ctrl    <= incr_pc;
3437 22 dilbert57
                 next_state <= pcrel16_state;
3438 19 dilbert57
 
3439
                                        when "1110" =>     -- undefined
3440
                                     case md(6 downto 5) is
3441
                                          when "00" =>
3442
                                  left_ctrl  <= ix_left;
3443
                                          when "01" =>
3444
                                  left_ctrl  <= iy_left;
3445
                                          when "10" =>
3446
                                  left_ctrl  <= up_left;
3447
                                          when others =>
3448
                                          -- when "11" =>
3449
                                  left_ctrl  <= sp_left;
3450
                                          end case;
3451
                                     right_ctrl <= zero_right;
3452 22 dilbert57
                                     alu_ctrl   <= alu_add16;
3453 19 dilbert57
                 ea_ctrl    <= load_ea;
3454
                                          if md(4) = '0' then
3455
                                            st_ctrl      <= pull_st;
3456
                                            next_state   <= saved_state;
3457
                                          else
3458
                                            next_state   <= indirect_state;
3459
                                          end if;
3460
 
3461
               when others =>
3462
--                      when "1111" =>     -- [,address]
3463
                                          -- advance PC to pick up address
3464
                 md_ctrl    <= fetch_first_md;
3465
                 addr_ctrl  <= fetch_ad;
3466
                                          pc_ctrl    <= incr_pc;
3467 22 dilbert57
                 next_state <= indexaddr_state;
3468 19 dilbert57
                                        end case;
3469
                                 end if;
3470
 
3471
                          -- load index register with ea plus one
3472
                          when postincr1_state =>
3473
                            left_ctrl  <= ea_left;
3474
                            right_ctrl <= one_right;
3475
                            alu_ctrl   <= alu_add16;
3476
                                 case md(6 downto 5) is
3477
                            when "00" =>
3478
               ix_ctrl    <= load_ix;
3479
                                 when "01" =>
3480
               iy_ctrl    <= load_iy;
3481
                                 when "10" =>
3482
               up_ctrl    <= load_up;
3483
                                 when others =>
3484
                                 -- when "11" =>
3485
               sp_ctrl    <= load_sp;
3486
                            end case;
3487
                                 -- return to previous state
3488
                            if md(4) = '0' then
3489
                                         st_ctrl      <= pull_st;
3490
                                         next_state   <= saved_state;
3491
                                 else
3492
                                         next_state   <= indirect_state;
3493
                                 end if;
3494
 
3495
                          -- load index register with ea plus two
3496
                          when postincr2_state =>
3497
                                 -- increment register by two (address)
3498
                            left_ctrl  <= ea_left;
3499
                            right_ctrl <= two_right;
3500
                            alu_ctrl   <= alu_add16;
3501
                                 case md(6 downto 5) is
3502
                            when "00" =>
3503
               ix_ctrl    <= load_ix;
3504
                                 when "01" =>
3505
               iy_ctrl    <= load_iy;
3506
                                 when "10" =>
3507
               up_ctrl    <= load_up;
3508
                                 when others =>
3509
                                 -- when "11" =>
3510
               sp_ctrl    <= load_sp;
3511
                            end case;
3512
                                 -- return to previous state
3513
                            if md(4) = '0' then
3514
                                         st_ctrl      <= pull_st;
3515
                                         next_state   <= saved_state;
3516
                                 else
3517
                                         next_state   <= indirect_state;
3518
                                 end if;
3519
           --
3520
                          -- ea = index register + md (8 bit signed offset)
3521
                          -- ea holds post byte
3522
                          --
3523
                          when index8_state =>
3524
                                 case ea(6 downto 5) is
3525
                            when "00" =>
3526
                              left_ctrl  <= ix_left;
3527
                            when "01" =>
3528
                              left_ctrl  <= iy_left;
3529
                                 when "10" =>
3530
                              left_ctrl  <= up_left;
3531
                                 when others =>
3532
                                 -- when "11" =>
3533
                              left_ctrl  <= sp_left;
3534
                                 end case;
3535
                                 -- ea = index reg + md
3536
                            right_ctrl <= md_sign8_right;
3537
                            alu_ctrl   <= alu_add16;
3538
             ea_ctrl    <= load_ea;
3539
                                 -- return to previous state
3540
                            if ea(4) = '0' then
3541
                                         st_ctrl      <= pull_st;
3542
                                         next_state   <= saved_state;
3543
                                 else
3544
                                         next_state   <= indirect_state;
3545
                                 end if;
3546
 
3547
                          -- fetch low byte of 16 bit indexed offset
3548
                          when index16_state =>
3549
                                 -- advance pc
3550
             pc_ctrl    <= incr_pc;
3551
                                 -- fetch low byte
3552
             md_ctrl    <= fetch_next_md;
3553
             addr_ctrl  <= fetch_ad;
3554 22 dilbert57
                                 next_state <= index16_2_state;
3555 19 dilbert57
 
3556
                          -- ea = index register + md (16 bit offset)
3557
                          -- ea holds post byte
3558
                          when index16_2_state =>
3559
                                 case ea(6 downto 5) is
3560
                            when "00" =>
3561
                              left_ctrl  <= ix_left;
3562
                            when "01" =>
3563
                              left_ctrl  <= iy_left;
3564
                                 when "10" =>
3565
                              left_ctrl  <= up_left;
3566
                                 when others =>
3567
                                 -- when "11" =>
3568
                              left_ctrl  <= sp_left;
3569
                                 end case;
3570
                                 -- ea = index reg + md
3571
                            right_ctrl <= md_right;
3572
                            alu_ctrl   <= alu_add16;
3573
             ea_ctrl    <= load_ea;
3574
                                 -- return to previous state
3575
                            if ea(4) = '0' then
3576
                                         st_ctrl      <= pull_st;
3577
                                         next_state   <= saved_state;
3578
                                 else
3579
                                         next_state   <= indirect_state;
3580
                                 end if;
3581
           --
3582
                          -- pc relative with 8 bit signed offest
3583
                          -- md holds signed offset
3584
                          --
3585
                          when pcrel8_state =>
3586
                                 -- ea = pc + signed md
3587
                            left_ctrl  <= pc_left;
3588
                            right_ctrl <= md_sign8_right;
3589
                            alu_ctrl   <= alu_add16;
3590
             ea_ctrl    <= load_ea;
3591
                                 -- return to previous state
3592
                            if ea(4) = '0' then
3593
                                         st_ctrl      <= pull_st;
3594
                                         next_state   <= saved_state;
3595
                                 else
3596
                                         next_state   <= indirect_state;
3597
                                 end if;
3598
 
3599
                          -- pc relative addressing with 16 bit offset
3600
                          -- pick up the low byte of the offset in md
3601
                          -- advance the pc
3602
                          when pcrel16_state =>
3603
                                 -- advance pc
3604
             pc_ctrl    <= incr_pc;
3605
                                 -- fetch low byte
3606
             md_ctrl    <= fetch_next_md;
3607
             addr_ctrl  <= fetch_ad;
3608
                                 next_state <= pcrel16_2_state;
3609
 
3610
                          -- pc relative with16 bit signed offest
3611
                          -- md holds signed offset
3612
                          when pcrel16_2_state =>
3613
                                 -- ea = pc +  md
3614
                            left_ctrl  <= pc_left;
3615
                            right_ctrl <= md_right;
3616
                            alu_ctrl   <= alu_add16;
3617
             ea_ctrl    <= load_ea;
3618
                                 -- return to previous state
3619
                            if ea(4) = '0' then
3620
                                         st_ctrl      <= pull_st;
3621
                                         next_state   <= saved_state;
3622
                                 else
3623
                                         next_state   <= indirect_state;
3624
                                 end if;
3625
 
3626
                          -- indexed to address
3627
                          -- pick up the low byte of the address
3628
                          -- advance the pc
3629
                          when indexaddr_state =>
3630
                                 -- advance pc
3631
             pc_ctrl    <= incr_pc;
3632
                                 -- fetch low byte
3633
             md_ctrl    <= fetch_next_md;
3634
             addr_ctrl  <= fetch_ad;
3635 22 dilbert57
                                 next_state <= indexaddr2_state;
3636 19 dilbert57
 
3637
                          -- indexed to absolute address
3638
                          -- md holds address
3639
                          -- ea hold indexing mode byte
3640
                          when indexaddr2_state =>
3641
                                 -- ea = md
3642
                            left_ctrl  <= pc_left;
3643
                            right_ctrl <= md_right;
3644
                            alu_ctrl   <= alu_ld16;
3645
             ea_ctrl    <= load_ea;
3646
                                 -- return to previous state
3647
                            if ea(4) = '0' then
3648
                                         st_ctrl      <= pull_st;
3649
                                         next_state   <= saved_state;
3650
                                 else
3651
                                         next_state   <= indirect_state;
3652
                                 end if;
3653
 
3654
           --
3655
                          -- load md with high byte of indirect address
3656
                          -- pointed to by ea
3657
                          -- increment ea
3658
                          --
3659
                          when indirect_state =>
3660
                                 -- increment ea
3661
                            left_ctrl  <= ea_left;
3662
                            right_ctrl <= one_right;
3663
                            alu_ctrl   <= alu_add16;
3664
             ea_ctrl    <= load_ea;
3665
                                 -- fetch high byte
3666
             md_ctrl    <= fetch_first_md;
3667
             addr_ctrl  <= read_ad;
3668
                                 next_state <= indirect2_state;
3669
           --
3670
                          -- load md with low byte of indirect address
3671
                          -- pointed to by ea
3672
                          -- ea has previously been incremented
3673
                          --
3674
                          when indirect2_state =>
3675
                                 -- fetch high byte
3676
             md_ctrl    <= fetch_next_md;
3677
             addr_ctrl  <= read_ad;
3678
             dout_ctrl  <= md_lo_dout;
3679
                                 next_state <= indirect3_state;
3680
                          --
3681
                          -- complete idirect addressing
3682
                          -- by loading ea with md
3683
                          --
3684
                          when indirect3_state =>
3685
                                 -- load ea with md
3686
                            left_ctrl  <= ea_left;
3687
                            right_ctrl <= md_right;
3688
                            alu_ctrl   <= alu_ld16;
3689
             ea_ctrl    <= load_ea;
3690
                                 -- return to previous state
3691
                                 st_ctrl      <= pull_st;
3692
                                 next_state   <= saved_state;
3693
 
3694
           --
3695
                          -- ea holds the low byte of the absolute address
3696
                          -- Move ea low byte into ea high byte
3697
                          -- load new ea low byte to for absolute 16 bit address
3698
                          -- advance the program counter
3699
                          --
3700
                          when extended_state => -- fetch ea low byte
3701
                                        -- increment pc
3702 22 dilbert57
               pc_ctrl      <= incr_pc;
3703 19 dilbert57
                                        -- fetch next effective address bytes
3704 22 dilbert57
                                        ea_ctrl      <= fetch_next_ea;
3705
               addr_ctrl    <= fetch_ad;
3706 19 dilbert57
                                   -- return to previous state
3707
                                   st_ctrl      <= pull_st;
3708
                                   next_state   <= saved_state;
3709
 
3710
                                when lea_state => -- here on load effective address
3711
                                        -- load index register with effective address
3712
               left_ctrl  <= pc_left;
3713
                                        right_ctrl <= ea_right;
3714
                                   alu_ctrl   <= alu_lea;
3715
                                        case op_code(3 downto 0) is
3716
                                        when "0000" => -- leax
3717
                   cc_ctrl    <= load_cc;
3718
                   ix_ctrl    <= load_ix;
3719
                                        when "0001" => -- leay
3720
                   cc_ctrl    <= load_cc;
3721
                   iy_ctrl    <= load_iy;
3722
                                        when "0010" => -- leas
3723
                   sp_ctrl    <= load_sp;
3724
                                        when "0011" => -- leau
3725
                   up_ctrl    <= load_up;
3726
                                        when others =>
3727 22 dilbert57
                                            null;
3728 19 dilbert57
                                        end case;
3729
               next_state   <= fetch_state;
3730
 
3731
                                --
3732
                                -- jump to subroutine
3733
                                -- sp=sp-1
3734
                                -- call push_return_lo_state to save pc
3735
                                -- return to jmp_state
3736
                                --
3737
                                when jsr_state =>
3738
                                        -- decrement sp
3739 22 dilbert57
               left_ctrl    <= sp_left;
3740
                                        right_ctrl   <= one_right;
3741
                                   alu_ctrl     <= alu_sub16;
3742
               sp_ctrl      <= load_sp;
3743 19 dilbert57
                                        -- call push_return_state
3744
                                        st_ctrl      <= push_st;
3745
                                        return_state <= jmp_state;
3746
               next_state   <= push_return_lo_state;
3747
 
3748
                                --
3749
                                -- Load pc with ea
3750
                                -- (JMP)
3751
                                --
3752
                                when jmp_state =>
3753
                                        -- load PC with effective address
3754
               left_ctrl  <= pc_left;
3755
                                        right_ctrl <= ea_right;
3756
                                   alu_ctrl   <= alu_ld16;
3757
                                        pc_ctrl    <= load_pc;
3758 22 dilbert57
               next_state <= fetch_state;
3759 19 dilbert57
 
3760
                                --
3761
                                -- long branch or branch to subroutine
3762
                                -- pick up next md byte
3763
                                -- md_hi = md_lo
3764
                                -- md_lo = (pc)
3765
                                -- pc=pc+1
3766
                                -- if a lbsr push return address
3767
                                -- continue to sbranch_state
3768
                                -- to evaluate conditional branches
3769
                                --
3770
                                when lbranch_state =>
3771
                                        pc_ctrl    <= incr_pc;
3772
                                        -- fetch the next byte into md_lo
3773
               md_ctrl    <= fetch_next_md;
3774
               addr_ctrl  <= fetch_ad;
3775
                                        -- if lbsr - push return address
3776
                                        -- then continue on to short branch
3777
                                        if op_code = "00010111" then
3778
                                          st_ctrl      <= push_st;
3779
                                          return_state <= sbranch_state;
3780
                 next_state   <= push_return_lo_state;
3781
                                        else
3782
                 next_state   <= sbranch_state;
3783
                                        end if;
3784
 
3785
                                 --
3786
                                 -- here to execute conditional branch
3787
                                 -- short conditional branch md = signed 8 bit offset
3788
                                 -- long branch md = 16 bit offset
3789
                                 -- 
3790
                  when sbranch_state =>
3791
               left_ctrl  <= pc_left;
3792
                                        right_ctrl <= md_right;
3793
                                   alu_ctrl   <= alu_add16;
3794 22 dilbert57
                                        -- Test condition for branch
3795 19 dilbert57
                              if op_code(7 downto 4) = "0010" then -- conditional branch
3796
                 case op_code(3 downto 0) is
3797
                           when "0000" => -- bra
3798
                                            cond_true := (1 = 1);
3799
                           when "0001" => -- brn
3800
                                            cond_true := (1 = 0);
3801
                           when "0010" => -- bhi
3802
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
3803
                           when "0011" => -- bls
3804
                                            cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
3805
                           when "0100" => -- bcc/bhs
3806
                                            cond_true := (cc(CBIT) = '0');
3807
                           when "0101" => -- bcs/blo
3808
                                            cond_true := (cc(CBIT) = '1');
3809
                           when "0110" => -- bne
3810
                             cond_true := (cc(ZBIT) = '0');
3811
                           when "0111" => -- beq
3812
                                            cond_true := (cc(ZBIT) = '1');
3813
                           when "1000" => -- bvc
3814
                                            cond_true := (cc(VBIT) = '0');
3815
                           when "1001" => -- bvs
3816
                                            cond_true := (cc(VBIT) = '1');
3817
                           when "1010" => -- bpl
3818
                                            cond_true := (cc(NBIT) = '0');
3819
                           when "1011" => -- bmi
3820
                                            cond_true := (cc(NBIT) = '1');
3821
                           when "1100" => -- bge
3822
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
3823
                           when "1101" => -- blt
3824
                                            cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
3825
                           when "1110" => -- bgt
3826
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
3827
                           when "1111" => -- ble
3828
                                            cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
3829
                           when others =>
3830
                                            null;
3831
                           end case;
3832
                                        else
3833
                                          cond_true := (1 = 1); -- lbra, lbsr, bsr
3834
                                   end if;
3835
                                        if cond_true then
3836
                                          pc_ctrl    <= load_pc;
3837
               end if;
3838 22 dilbert57
                                        next_state   <= fetch_state;
3839 19 dilbert57
 
3840
                                 --
3841
                                 -- push return address onto the S stack
3842
                                 --
3843
                                 -- (sp) = pc_lo
3844
                                 -- sp = sp - 1
3845
                                 --
3846
                                 when push_return_lo_state =>
3847
                                          -- decrement the sp
3848
                 left_ctrl  <= sp_left;
3849
                 right_ctrl <= one_right;
3850
                 alu_ctrl   <= alu_sub16;
3851
                 sp_ctrl    <= load_sp;
3852
                 -- write PC low
3853
                 addr_ctrl  <= pushs_ad;
3854
                 dout_ctrl  <= pc_lo_dout;
3855 22 dilbert57
                 next_state <= push_return_hi_state;
3856 19 dilbert57
 
3857
                                --
3858
                                -- push program counter hi byte onto the stack
3859
                                -- (sp) = pc_hi
3860
                                -- sp = sp
3861
                                -- return to originating state
3862
                                --
3863
                                when push_return_hi_state =>
3864
                                          -- write pc hi bytes
3865 22 dilbert57
                 addr_ctrl    <= pushs_ad;
3866
                 dout_ctrl    <= pc_hi_dout;
3867
                                          st_ctrl      <= pull_st;
3868 19 dilbert57
                 next_state   <= saved_state;
3869
 
3870
                                 when pull_return_hi_state =>
3871
                                          -- increment the sp
3872
                 left_ctrl  <= sp_left;
3873
                 right_ctrl <= one_right;
3874
                 alu_ctrl   <= alu_add16;
3875
                 sp_ctrl    <= load_sp;
3876
                 -- read pc hi
3877
                                          pc_ctrl    <= pull_hi_pc;
3878
                 addr_ctrl  <= pulls_ad;
3879 22 dilbert57
                 next_state <= pull_return_lo_state;
3880 19 dilbert57
 
3881
                                when pull_return_lo_state =>
3882
                                          -- increment the SP
3883
                 left_ctrl  <= sp_left;
3884
                 right_ctrl <= one_right;
3885
                 alu_ctrl   <= alu_add16;
3886
                 sp_ctrl    <= load_sp;
3887
                                          -- read pc low
3888
                                          pc_ctrl    <= pull_lo_pc;
3889
                 addr_ctrl  <= pulls_ad;
3890
                 dout_ctrl  <= pc_lo_dout;
3891
                                          --
3892
                                          st_ctrl      <= pull_st;
3893
                 next_state   <= saved_state;
3894
 
3895
                                 when andcc_state =>
3896
                                          -- AND CC with md
3897
                 left_ctrl  <= md_left;
3898
                 right_ctrl <= zero_right;
3899
                 alu_ctrl   <= alu_andcc;
3900
                 cc_ctrl    <= load_cc;
3901
                                          --
3902 22 dilbert57
                                          st_ctrl    <= pull_st;
3903
                                     next_state <= saved_state;
3904 19 dilbert57
 
3905
                                 when orcc_state =>
3906
                                          -- OR CC with md
3907
                 left_ctrl  <= md_left;
3908
                 right_ctrl <= zero_right;
3909
                 alu_ctrl   <= alu_orcc;
3910
                 cc_ctrl    <= load_cc;
3911
                                          --
3912 22 dilbert57
                                          st_ctrl    <= pull_st;
3913
                                     next_state <= saved_state;
3914 19 dilbert57
 
3915
                                 when tfr_state =>
3916
                                          -- select source register
3917
                                          case md(7 downto 4) is
3918
                                          when "0000" =>
3919
                                            left_ctrl <= accd_left;
3920
                                          when "0001" =>
3921
                                            left_ctrl <= ix_left;
3922
                                          when "0010" =>
3923
                                            left_ctrl <= iy_left;
3924
                                          when "0011" =>
3925
                                            left_ctrl <= up_left;
3926
                                          when "0100" =>
3927
                                            left_ctrl <= sp_left;
3928
                                          when "0101" =>
3929
                                            left_ctrl <= pc_left;
3930
                                          when "1000" =>
3931
                                            left_ctrl <= acca_left;
3932
                                          when "1001" =>
3933
                                            left_ctrl <= accb_left;
3934
                                          when "1010" =>
3935
                                            left_ctrl <= cc_left;
3936
                                          when "1011" =>
3937
                                            left_ctrl <= dp_left;
3938
                                          when others =>
3939
                   left_ctrl  <= md_left;
3940
                                          end case;
3941
                 right_ctrl <= zero_right;
3942
                 alu_ctrl   <= alu_tfr;
3943
                                          -- select destination register
3944
                                          case md(3 downto 0) is
3945
                                          when "0000" => -- accd
3946
                   acca_ctrl  <= load_hi_acca;
3947
                   accb_ctrl  <= load_accb;
3948
                                          when "0001" => -- ix
3949
                   ix_ctrl    <= load_ix;
3950
                                          when "0010" => -- iy
3951
                   iy_ctrl    <= load_iy;
3952
                                          when "0011" => -- up
3953
                   up_ctrl    <= load_up;
3954
                                          when "0100" => -- sp
3955
                   sp_ctrl    <= load_sp;
3956
                                          when "0101" => -- pc
3957
                   pc_ctrl    <= load_pc;
3958
                                          when "1000" => -- acca
3959
                   acca_ctrl  <= load_acca;
3960
                                          when "1001" => -- accb
3961
                   accb_ctrl  <= load_accb;
3962
                                          when "1010" => -- cc
3963
                   cc_ctrl    <= load_cc;
3964
                                          when "1011" => --dp
3965
                   dp_ctrl    <= load_dp;
3966
                                          when others =>
3967 22 dilbert57
                                            null;
3968 19 dilbert57
                                          end case;
3969
                                          --
3970
                                          st_ctrl      <= pull_st;
3971
                                     next_state   <= saved_state;
3972
 
3973
                                 when exg_state =>
3974
                                          -- save destination register
3975
                                          case md(3 downto 0) is
3976
                                          when "0000" =>
3977
                                            left_ctrl <= accd_left;
3978
                                          when "0001" =>
3979
                                            left_ctrl <= ix_left;
3980
                                          when "0010" =>
3981
                                            left_ctrl <= iy_left;
3982
                                          when "0011" =>
3983
                                            left_ctrl <= up_left;
3984
                                          when "0100" =>
3985
                                            left_ctrl <= sp_left;
3986
                                          when "0101" =>
3987
                                            left_ctrl <= pc_left;
3988
                                          when "1000" =>
3989
                                            left_ctrl <= acca_left;
3990
                                          when "1001" =>
3991
                                            left_ctrl <= accb_left;
3992
                                          when "1010" =>
3993
                                            left_ctrl <= cc_left;
3994
                                          when "1011" =>
3995
                                            left_ctrl <= dp_left;
3996
                                          when others =>
3997
                   left_ctrl  <= md_left;
3998
                                          end case;
3999
                 right_ctrl <= zero_right;
4000
                 alu_ctrl   <= alu_tfr;
4001
                 ea_ctrl    <= load_ea;
4002
                                          -- call tranfer microcode
4003
                                          st_ctrl      <= push_st;
4004
                                          return_state <= exg1_state;
4005
                                     next_state   <= tfr_state;
4006
 
4007
                                 when exg1_state =>
4008
                                          -- restore destination
4009
                 left_ctrl  <= ea_left;
4010
                 right_ctrl <= zero_right;
4011
                 alu_ctrl   <= alu_tfr;
4012
                                          -- save as source register
4013
                                          case md(7 downto 4) is
4014
                                          when "0000" => -- accd
4015
                   acca_ctrl  <= load_hi_acca;
4016
                   accb_ctrl  <= load_accb;
4017
                                          when "0001" => -- ix
4018
                   ix_ctrl    <= load_ix;
4019
                                          when "0010" => -- iy
4020
                   iy_ctrl    <= load_iy;
4021
                                          when "0011" => -- up
4022
                   up_ctrl    <= load_up;
4023
                                          when "0100" => -- sp
4024
                   sp_ctrl    <= load_sp;
4025
                                          when "0101" => -- pc
4026
                   pc_ctrl    <= load_pc;
4027
                                          when "1000" => -- acca
4028
                   acca_ctrl  <= load_acca;
4029
                                          when "1001" => -- accb
4030
                   accb_ctrl  <= load_accb;
4031
                                          when "1010" => -- cc
4032
                   cc_ctrl    <= load_cc;
4033
                                          when "1011" => --dp
4034
                   dp_ctrl    <= load_dp;
4035
                                          when others =>
4036 22 dilbert57
                                            null;
4037 19 dilbert57
                                          end case;
4038
                                     next_state   <= fetch_state;
4039
 
4040
                                 when mul_state =>
4041
                                          -- move acca to md
4042
                 left_ctrl  <= acca_left;
4043
                 right_ctrl <= zero_right;
4044
                 alu_ctrl   <= alu_st16;
4045
                 md_ctrl    <= load_md;
4046 22 dilbert57
                                     next_state <= mulea_state;
4047 19 dilbert57
 
4048
                                 when mulea_state =>
4049
                                          -- move accb to ea
4050
                 left_ctrl  <= accb_left;
4051
                 right_ctrl <= zero_right;
4052
                 alu_ctrl   <= alu_st16;
4053
                 ea_ctrl    <= load_ea;
4054 22 dilbert57
                                     next_state <= muld_state;
4055 19 dilbert57
 
4056
                                 when muld_state =>
4057
                                          -- clear accd
4058
                 left_ctrl  <= acca_left;
4059
                 right_ctrl <= zero_right;
4060
                 alu_ctrl   <= alu_ld8;
4061
                 acca_ctrl  <= load_hi_acca;
4062
                 accb_ctrl  <= load_accb;
4063 22 dilbert57
                                     next_state <= mul0_state;
4064 19 dilbert57
 
4065
                                 when mul0_state =>
4066
                                          -- if bit 0 of ea set, add accd to md
4067
                 left_ctrl  <= accd_left;
4068
                                          if ea(0) = '1' then
4069
                   right_ctrl <= md_right;
4070
                                          else
4071
                   right_ctrl <= zero_right;
4072
                                          end if;
4073
                 alu_ctrl   <= alu_mul;
4074
                 cc_ctrl    <= load_cc;
4075
                 acca_ctrl  <= load_hi_acca;
4076
                 accb_ctrl  <= load_accb;
4077
                 md_ctrl    <= shiftl_md;
4078 22 dilbert57
                                     next_state <= mul1_state;
4079 19 dilbert57
 
4080
                                 when mul1_state =>
4081
                                          -- if bit 1 of ea set, add accd to md
4082
                 left_ctrl  <= accd_left;
4083
                                          if ea(1) = '1' then
4084
                   right_ctrl <= md_right;
4085
                                          else
4086
                   right_ctrl <= zero_right;
4087
                                          end if;
4088
                 alu_ctrl   <= alu_mul;
4089
                 cc_ctrl    <= load_cc;
4090
                 acca_ctrl  <= load_hi_acca;
4091
                 accb_ctrl  <= load_accb;
4092
                 md_ctrl    <= shiftl_md;
4093 22 dilbert57
                                     next_state <= mul2_state;
4094 19 dilbert57
 
4095
                                 when mul2_state =>
4096
                                          -- if bit 2 of ea set, add accd to md
4097
                 left_ctrl  <= accd_left;
4098
                                          if ea(2) = '1' then
4099
                   right_ctrl <= md_right;
4100
                                          else
4101
                   right_ctrl <= zero_right;
4102
                                          end if;
4103
                 alu_ctrl   <= alu_mul;
4104
                 cc_ctrl    <= load_cc;
4105
                 acca_ctrl  <= load_hi_acca;
4106
                 accb_ctrl  <= load_accb;
4107
                 md_ctrl    <= shiftl_md;
4108 22 dilbert57
                                     next_state <= mul3_state;
4109 19 dilbert57
 
4110
                                 when mul3_state =>
4111
                                          -- if bit 3 of ea set, add accd to md
4112
                 left_ctrl  <= accd_left;
4113
                                          if ea(3) = '1' then
4114
                   right_ctrl <= md_right;
4115
                                          else
4116
                   right_ctrl <= zero_right;
4117
                                          end if;
4118
                 alu_ctrl   <= alu_mul;
4119
                 cc_ctrl    <= load_cc;
4120
                 acca_ctrl  <= load_hi_acca;
4121
                 accb_ctrl  <= load_accb;
4122
                 md_ctrl    <= shiftl_md;
4123 22 dilbert57
                                     next_state <= mul4_state;
4124 19 dilbert57
 
4125
                                 when mul4_state =>
4126
                                          -- if bit 4 of ea set, add accd to md
4127
                 left_ctrl  <= accd_left;
4128
                                          if ea(4) = '1' then
4129
                   right_ctrl <= md_right;
4130
                                          else
4131
                   right_ctrl <= zero_right;
4132
                                          end if;
4133
                 alu_ctrl   <= alu_mul;
4134
                 cc_ctrl    <= load_cc;
4135
                 acca_ctrl  <= load_hi_acca;
4136
                 accb_ctrl  <= load_accb;
4137
                 md_ctrl    <= shiftl_md;
4138 22 dilbert57
                                     next_state <= mul5_state;
4139 19 dilbert57
 
4140
                                 when mul5_state =>
4141
                                          -- if bit 5 of ea set, add accd to md
4142
                 left_ctrl  <= accd_left;
4143
                                          if ea(5) = '1' then
4144
                   right_ctrl <= md_right;
4145
                                          else
4146
                   right_ctrl <= zero_right;
4147
                                          end if;
4148
                 alu_ctrl   <= alu_mul;
4149
                 cc_ctrl    <= load_cc;
4150
                 acca_ctrl  <= load_hi_acca;
4151
                 accb_ctrl  <= load_accb;
4152
                 md_ctrl    <= shiftl_md;
4153 22 dilbert57
                                     next_state <= mul6_state;
4154 19 dilbert57
 
4155
                                 when mul6_state =>
4156
                                          -- if bit 6 of ea set, add accd to md
4157
                 left_ctrl  <= accd_left;
4158
                                          if ea(6) = '1' then
4159
                   right_ctrl <= md_right;
4160
                                          else
4161
                   right_ctrl <= zero_right;
4162
                                          end if;
4163
                 alu_ctrl   <= alu_mul;
4164
                 cc_ctrl    <= load_cc;
4165
                 acca_ctrl  <= load_hi_acca;
4166
                 accb_ctrl  <= load_accb;
4167
                 md_ctrl    <= shiftl_md;
4168 22 dilbert57
                                     next_state <= mul7_state;
4169 19 dilbert57
 
4170
                                 when mul7_state =>
4171
                                          -- if bit 7 of ea set, add accd to md
4172
                 left_ctrl  <= accd_left;
4173
                                          if ea(7) = '1' then
4174
                   right_ctrl <= md_right;
4175
                                          else
4176
                   right_ctrl <= zero_right;
4177
                                          end if;
4178
                 alu_ctrl   <= alu_mul;
4179
                 cc_ctrl    <= load_cc;
4180
                 acca_ctrl  <= load_hi_acca;
4181
                 accb_ctrl  <= load_accb;
4182
                 md_ctrl    <= shiftl_md;
4183 22 dilbert57
                                     next_state <= fetch_state;
4184 19 dilbert57
 
4185
                          --
4186
                          -- Enter here on pushs
4187
                          -- ea holds post byte
4188
                          --
4189
                          when pshs_state =>
4190
             -- decrement sp if any registers to be pushed
4191
             left_ctrl  <= sp_left;
4192
             right_ctrl <= one_right;
4193
             alu_ctrl   <= alu_sub16;
4194
                                 if ea(7 downto 0) = "00000000" then
4195
               sp_ctrl    <= latch_sp;
4196
                                 else
4197
               sp_ctrl    <= load_sp;
4198
                                 end if;
4199
                                 if ea(7) = '1' then
4200
               next_state <= pshs_pcl_state;
4201
                                 elsif ea(6) = '1' then
4202
               next_state <= pshs_upl_state;
4203
                                 elsif ea(5) = '1' then
4204
                                   next_state <= pshs_iyl_state;
4205
                                 elsif ea(4) = '1' then
4206
                                   next_state <= pshs_ixl_state;
4207
                                 elsif ea(3) = '1' then
4208
                                   next_state <= pshs_dp_state;
4209
                                 elsif ea(2) = '1' then
4210
                                   next_state <= pshs_accb_state;
4211
                                 elsif ea(1) = '1' then
4212
                                   next_state <= pshs_acca_state;
4213
                                 elsif ea(0) = '1' then
4214
                                   next_state <= pshs_cc_state;
4215
                                 else
4216
                                   next_state <= fetch_state;
4217
                                 end if;
4218
 
4219
                          when pshs_pcl_state =>
4220
             -- decrement sp
4221
             left_ctrl  <= sp_left;
4222
             right_ctrl <= one_right;
4223
             alu_ctrl   <= alu_sub16;
4224
             sp_ctrl    <= load_sp;
4225
                                 -- write pc low
4226
             addr_ctrl  <= pushs_ad;
4227
                            dout_ctrl  <= pc_lo_dout;
4228 22 dilbert57
             next_state <= pshs_pch_state;
4229 19 dilbert57
 
4230
                          when pshs_pch_state =>
4231
             -- decrement sp
4232
             left_ctrl  <= sp_left;
4233
             right_ctrl <= one_right;
4234
             alu_ctrl   <= alu_sub16;
4235
                                 if ea(6 downto 0) = "0000000" then
4236
               sp_ctrl    <= latch_sp;
4237
                                 else
4238
               sp_ctrl    <= load_sp;
4239
                                 end if;
4240
                                 -- write pc hi
4241
             addr_ctrl  <= pushs_ad;
4242
                            dout_ctrl  <= pc_hi_dout;
4243
                                 if ea(6) = '1' then
4244
               next_state <= pshs_upl_state;
4245
                                 elsif ea(5) = '1' then
4246
                                   next_state <= pshs_iyl_state;
4247
                                 elsif ea(4) = '1' then
4248
                                   next_state <= pshs_ixl_state;
4249
                                 elsif ea(3) = '1' then
4250
                                   next_state <= pshs_dp_state;
4251
                                 elsif ea(2) = '1' then
4252
                                   next_state <= pshs_accb_state;
4253
                                 elsif ea(1) = '1' then
4254
                                   next_state <= pshs_acca_state;
4255
                                 elsif ea(0) = '1' then
4256
                                   next_state <= pshs_cc_state;
4257
                                 else
4258
                                   next_state <= fetch_state;
4259
                                 end if;
4260
 
4261
 
4262
                          when pshs_upl_state =>
4263
             -- decrement sp
4264
             left_ctrl  <= sp_left;
4265
             right_ctrl <= one_right;
4266
             alu_ctrl   <= alu_sub16;
4267
             sp_ctrl    <= load_sp;
4268
                                 -- write pc low
4269
             addr_ctrl  <= pushs_ad;
4270
                            dout_ctrl  <= up_lo_dout;
4271 22 dilbert57
             next_state <= pshs_uph_state;
4272 19 dilbert57
 
4273
                          when pshs_uph_state =>
4274
             -- decrement sp
4275
             left_ctrl  <= sp_left;
4276
             right_ctrl <= one_right;
4277
             alu_ctrl   <= alu_sub16;
4278
                                 if ea(5 downto 0) = "000000" then
4279
               sp_ctrl    <= latch_sp;
4280
                                 else
4281
               sp_ctrl    <= load_sp;
4282
                                 end if;
4283
                                 -- write pc hi
4284
             addr_ctrl  <= pushs_ad;
4285
                            dout_ctrl  <= up_hi_dout;
4286
                                 if ea(5) = '1' then
4287
                                   next_state   <= pshs_iyl_state;
4288
                                 elsif ea(4) = '1' then
4289
                                   next_state   <= pshs_ixl_state;
4290
                                 elsif ea(3) = '1' then
4291
                                   next_state   <= pshs_dp_state;
4292
                                 elsif ea(2) = '1' then
4293
                                   next_state   <= pshs_accb_state;
4294
                                 elsif ea(1) = '1' then
4295
                                   next_state   <= pshs_acca_state;
4296
                                 elsif ea(0) = '1' then
4297
                                   next_state   <= pshs_cc_state;
4298
                                 else
4299
                                   next_state   <= fetch_state;
4300
                                 end if;
4301
 
4302
                          when pshs_iyl_state =>
4303
             -- decrement sp
4304
             left_ctrl  <= sp_left;
4305
             right_ctrl <= one_right;
4306
             alu_ctrl   <= alu_sub16;
4307
             sp_ctrl    <= load_sp;
4308
                                 -- write iy low
4309
             addr_ctrl  <= pushs_ad;
4310
                            dout_ctrl  <= iy_lo_dout;
4311 22 dilbert57
             next_state <= pshs_iyh_state;
4312 19 dilbert57
 
4313
                          when pshs_iyh_state =>
4314
             -- decrement sp
4315
             left_ctrl  <= sp_left;
4316
             right_ctrl <= one_right;
4317
             alu_ctrl   <= alu_sub16;
4318
                                 if ea(4 downto 0) = "00000" then
4319
               sp_ctrl    <= latch_sp;
4320
                                 else
4321
               sp_ctrl    <= load_sp;
4322
                                 end if;
4323
                                 -- write iy hi
4324
             addr_ctrl  <= pushs_ad;
4325
                            dout_ctrl  <= iy_hi_dout;
4326
                                 if ea(4) = '1' then
4327
                                   next_state   <= pshs_ixl_state;
4328
                                 elsif ea(3) = '1' then
4329
                                   next_state   <= pshs_dp_state;
4330
                                 elsif ea(2) = '1' then
4331
                                   next_state   <= pshs_accb_state;
4332
                                 elsif ea(1) = '1' then
4333
                                   next_state   <= pshs_acca_state;
4334
                                 elsif ea(0) = '1' then
4335
                                   next_state   <= pshs_cc_state;
4336
                                 else
4337
                                   next_state   <= fetch_state;
4338
                                 end if;
4339
 
4340
                          when pshs_ixl_state =>
4341
             -- decrement sp
4342
             left_ctrl  <= sp_left;
4343
             right_ctrl <= one_right;
4344
             alu_ctrl   <= alu_sub16;
4345
             sp_ctrl    <= load_sp;
4346
                                 -- write ix low
4347
             addr_ctrl  <= pushs_ad;
4348
                            dout_ctrl  <= ix_lo_dout;
4349 22 dilbert57
             next_state <= pshs_ixh_state;
4350 19 dilbert57
 
4351
                          when pshs_ixh_state =>
4352
             -- decrement sp
4353
             left_ctrl  <= sp_left;
4354
             right_ctrl <= one_right;
4355
             alu_ctrl   <= alu_sub16;
4356
                                 if ea(3 downto 0) = "0000" then
4357
               sp_ctrl    <= latch_sp;
4358
                                 else
4359
               sp_ctrl    <= load_sp;
4360
                                 end if;
4361
                                 -- write ix hi
4362
             addr_ctrl  <= pushs_ad;
4363
                            dout_ctrl  <= ix_hi_dout;
4364
                                 if ea(3) = '1' then
4365
                                   next_state   <= pshs_dp_state;
4366
                                 elsif ea(2) = '1' then
4367
                                   next_state   <= pshs_accb_state;
4368
                                 elsif ea(1) = '1' then
4369
                                   next_state   <= pshs_acca_state;
4370
                                 elsif ea(0) = '1' then
4371
                                   next_state   <= pshs_cc_state;
4372
                                 else
4373
                                   next_state   <= fetch_state;
4374
                                 end if;
4375
 
4376
                          when pshs_dp_state =>
4377
             -- decrement sp
4378
             left_ctrl  <= sp_left;
4379
             right_ctrl <= one_right;
4380
             alu_ctrl   <= alu_sub16;
4381
                                 if ea(2 downto 0) = "000" then
4382
               sp_ctrl    <= latch_sp;
4383
                                 else
4384
               sp_ctrl    <= load_sp;
4385
                                 end if;
4386
                                 -- write dp
4387
             addr_ctrl  <= pushs_ad;
4388
                            dout_ctrl  <= dp_dout;
4389
                                 if ea(2) = '1' then
4390
                                   next_state   <= pshs_accb_state;
4391
                                 elsif ea(1) = '1' then
4392
                                   next_state   <= pshs_acca_state;
4393
                                 elsif ea(0) = '1' then
4394
                                   next_state   <= pshs_cc_state;
4395
                                 else
4396
                                   next_state   <= fetch_state;
4397
                                 end if;
4398
 
4399
                          when pshs_accb_state =>
4400
             -- decrement sp
4401
             left_ctrl  <= sp_left;
4402
             right_ctrl <= one_right;
4403
             alu_ctrl   <= alu_sub16;
4404
                                 if ea(1 downto 0) = "00" then
4405
               sp_ctrl    <= latch_sp;
4406
                                 else
4407
               sp_ctrl    <= load_sp;
4408
                                 end if;
4409
                                 -- write accb
4410
             addr_ctrl  <= pushs_ad;
4411
                            dout_ctrl  <= accb_dout;
4412
                                 if ea(1) = '1' then
4413
                                   next_state   <= pshs_acca_state;
4414
                                 elsif ea(0) = '1' then
4415
                                   next_state   <= pshs_cc_state;
4416
                                 else
4417
                                   next_state   <= fetch_state;
4418
                                 end if;
4419
 
4420
                          when pshs_acca_state =>
4421
             -- decrement sp
4422
             left_ctrl  <= sp_left;
4423
             right_ctrl <= one_right;
4424
             alu_ctrl   <= alu_sub16;
4425
                                 if ea(0) = '1' then
4426
               sp_ctrl    <= load_sp;
4427
                                 else
4428
               sp_ctrl    <= latch_sp;
4429
                                 end if;
4430
                                 -- write acca
4431
             addr_ctrl  <= pushs_ad;
4432
                            dout_ctrl  <= acca_dout;
4433
                                 if ea(0) = '1' then
4434
                                   next_state   <= pshs_cc_state;
4435
                                 else
4436
                                   next_state   <= fetch_state;
4437
                                 end if;
4438
 
4439
                          when pshs_cc_state =>
4440
             -- idle sp
4441
                                 -- write cc
4442
             addr_ctrl  <= pushs_ad;
4443
                            dout_ctrl  <= cc_dout;
4444 22 dilbert57
             next_state <= fetch_state;
4445 19 dilbert57
 
4446
                          --
4447
                          -- enter here on PULS
4448
                          -- ea hold register mask
4449
                          --
4450
                          when puls_state =>
4451
                                 if ea(0) = '1' then
4452
                                   next_state <= puls_cc_state;
4453
                                 elsif ea(1) = '1' then
4454
                                   next_state <= puls_acca_state;
4455
                                 elsif ea(2) = '1' then
4456
                                   next_state <= puls_accb_state;
4457
                                 elsif ea(3) = '1' then
4458
                                   next_state <= puls_dp_state;
4459
                                 elsif ea(4) = '1' then
4460
                                   next_state <= puls_ixh_state;
4461
                                 elsif ea(5) = '1' then
4462
                                   next_state <= puls_iyh_state;
4463
                                 elsif ea(6) = '1' then
4464
               next_state <= puls_uph_state;
4465
                                 elsif ea(7) = '1' then
4466
               next_state <= puls_pch_state;
4467
                                 else
4468
                                   next_state <= fetch_state;
4469
                                 end if;
4470
 
4471
                          when puls_cc_state =>
4472 22 dilbert57
                                 -- increment sp
4473 19 dilbert57
             left_ctrl  <= sp_left;
4474
             right_ctrl <= one_right;
4475
             alu_ctrl   <= alu_add16;
4476
             sp_ctrl    <= load_sp;
4477
                                 -- read cc
4478
             cc_ctrl    <= pull_cc;
4479
             addr_ctrl  <= pulls_ad;
4480
                                 if ea(1) = '1' then
4481
                                   next_state <= puls_acca_state;
4482
                                 elsif ea(2) = '1' then
4483
                                   next_state <= puls_accb_state;
4484
                                 elsif ea(3) = '1' then
4485
                                   next_state <= puls_dp_state;
4486
                                 elsif ea(4) = '1' then
4487
                                   next_state <= puls_ixh_state;
4488
                                 elsif ea(5) = '1' then
4489
                                   next_state <= puls_iyh_state;
4490
                                 elsif ea(6) = '1' then
4491
               next_state <= puls_uph_state;
4492
                                 elsif ea(7) = '1' then
4493
               next_state <= puls_pch_state;
4494
                                 else
4495
                                   next_state <= fetch_state;
4496
                                 end if;
4497
 
4498
                          when puls_acca_state =>
4499 22 dilbert57
                                 -- increment sp
4500 19 dilbert57
             left_ctrl  <= sp_left;
4501
             right_ctrl <= one_right;
4502
             alu_ctrl   <= alu_add16;
4503
             sp_ctrl    <= load_sp;
4504
                                 -- read acca
4505
                                 acca_ctrl  <= pull_acca;
4506
             addr_ctrl  <= pulls_ad;
4507
                                 if ea(2) = '1' then
4508
                                   next_state <= puls_accb_state;
4509
                                 elsif ea(3) = '1' then
4510
                                   next_state <= puls_dp_state;
4511
                                 elsif ea(4) = '1' then
4512
                                   next_state <= puls_ixh_state;
4513
                                 elsif ea(5) = '1' then
4514
                                   next_state <= puls_iyh_state;
4515
                                 elsif ea(6) = '1' then
4516
               next_state <= puls_uph_state;
4517
                                 elsif ea(7) = '1' then
4518
               next_state <= puls_pch_state;
4519
                                 else
4520
                                   next_state <= fetch_state;
4521
                                 end if;
4522
 
4523
                          when puls_accb_state =>
4524 22 dilbert57
                                 -- increment sp
4525 19 dilbert57
             left_ctrl  <= sp_left;
4526
             right_ctrl <= one_right;
4527
             alu_ctrl   <= alu_add16;
4528
             sp_ctrl    <= load_sp;
4529
                                 -- read accb
4530
                                 accb_ctrl  <= pull_accb;
4531
             addr_ctrl  <= pulls_ad;
4532
                                 if ea(3) = '1' then
4533
                                   next_state <= puls_dp_state;
4534
                                 elsif ea(4) = '1' then
4535
                                   next_state <= puls_ixh_state;
4536
                                 elsif ea(5) = '1' then
4537
                                   next_state <= puls_iyh_state;
4538
                                 elsif ea(6) = '1' then
4539
               next_state <= puls_uph_state;
4540
                                 elsif ea(7) = '1' then
4541
               next_state <= puls_pch_state;
4542
                                 else
4543
                                   next_state <= fetch_state;
4544
                                 end if;
4545
 
4546
                          when puls_dp_state =>
4547 22 dilbert57
                                 -- increment sp
4548 19 dilbert57
             left_ctrl  <= sp_left;
4549
             right_ctrl <= one_right;
4550
             alu_ctrl   <= alu_add16;
4551
             sp_ctrl    <= load_sp;
4552
                                 -- read dp
4553
                                 dp_ctrl    <= pull_dp;
4554
             addr_ctrl  <= pulls_ad;
4555
                                 if ea(4) = '1' then
4556
                                   next_state <= puls_ixh_state;
4557
                                 elsif ea(5) = '1' then
4558
                                   next_state <= puls_iyh_state;
4559
                                 elsif ea(6) = '1' then
4560
               next_state <= puls_uph_state;
4561
                                 elsif ea(7) = '1' then
4562
               next_state <= puls_pch_state;
4563
                                 else
4564
                                   next_state <= fetch_state;
4565
                                 end if;
4566
 
4567
                          when puls_ixh_state =>
4568
             -- increment sp
4569
             left_ctrl  <= sp_left;
4570
             right_ctrl <= one_right;
4571
             alu_ctrl   <= alu_add16;
4572
             sp_ctrl    <= load_sp;
4573
                                 -- pull ix hi
4574
                                 ix_ctrl    <= pull_hi_ix;
4575
             addr_ctrl  <= pulls_ad;
4576 22 dilbert57
             next_state <= puls_ixl_state;
4577 19 dilbert57
 
4578
                          when puls_ixl_state =>
4579 22 dilbert57
                                 -- increment sp
4580 19 dilbert57
             left_ctrl  <= sp_left;
4581
             right_ctrl <= one_right;
4582
             alu_ctrl   <= alu_add16;
4583
             sp_ctrl    <= load_sp;
4584
                                 -- read ix low
4585
                                 ix_ctrl    <= pull_lo_ix;
4586
             addr_ctrl  <= pulls_ad;
4587
                                 if ea(5) = '1' then
4588
                                   next_state <= puls_iyh_state;
4589
                                 elsif ea(6) = '1' then
4590
               next_state <= puls_uph_state;
4591
                                 elsif ea(7) = '1' then
4592
               next_state <= puls_pch_state;
4593
                                 else
4594
                                   next_state <= fetch_state;
4595
                                 end if;
4596
 
4597
                          when puls_iyh_state =>
4598
             -- increment sp
4599
             left_ctrl  <= sp_left;
4600
             right_ctrl <= one_right;
4601
             alu_ctrl   <= alu_add16;
4602
             sp_ctrl    <= load_sp;
4603
                                 -- pull iy hi
4604
                                 iy_ctrl    <= pull_hi_iy;
4605
             addr_ctrl  <= pulls_ad;
4606
             next_state   <= puls_iyl_state;
4607
 
4608
                          when puls_iyl_state =>
4609
             -- increment sp
4610
             left_ctrl  <= sp_left;
4611
             right_ctrl <= one_right;
4612
             alu_ctrl   <= alu_add16;
4613
             sp_ctrl    <= load_sp;
4614
                                 -- read iy low
4615
                                 iy_ctrl    <= pull_lo_iy;
4616
             addr_ctrl  <= pulls_ad;
4617
                                 if ea(6) = '1' then
4618
               next_state <= puls_uph_state;
4619
                                 elsif ea(7) = '1' then
4620
               next_state <= puls_pch_state;
4621
                                 else
4622
                                   next_state <= fetch_state;
4623
                                 end if;
4624
 
4625
                          when puls_uph_state =>
4626
             -- increment sp
4627
             left_ctrl  <= sp_left;
4628
             right_ctrl <= one_right;
4629
             alu_ctrl   <= alu_add16;
4630
             sp_ctrl    <= load_sp;
4631
                                 -- pull up hi
4632
                                 up_ctrl    <= pull_hi_up;
4633
             addr_ctrl  <= pulls_ad;
4634 22 dilbert57
             next_state <= puls_upl_state;
4635 19 dilbert57
 
4636
                          when puls_upl_state =>
4637
                                 -- increment sp
4638
             left_ctrl  <= sp_left;
4639
             right_ctrl <= one_right;
4640
             alu_ctrl   <= alu_add16;
4641
             sp_ctrl    <= load_sp;
4642
                                 -- read up low
4643
                                 up_ctrl    <= pull_lo_up;
4644
             addr_ctrl  <= pulls_ad;
4645
                                 if ea(7) = '1' then
4646
               next_state <= puls_pch_state;
4647
                                 else
4648
                                   next_state <= fetch_state;
4649
                                 end if;
4650
 
4651
                          when puls_pch_state =>
4652
             -- increment sp
4653
             left_ctrl  <= sp_left;
4654
             right_ctrl <= one_right;
4655
             alu_ctrl   <= alu_add16;
4656
             sp_ctrl    <= load_sp;
4657
                                 -- pull pc hi
4658
                                 pc_ctrl    <= pull_hi_pc;
4659
             addr_ctrl  <= pulls_ad;
4660 22 dilbert57
             next_state <= puls_pcl_state;
4661 19 dilbert57
 
4662
                          when puls_pcl_state =>
4663
                                 -- increment sp
4664
             left_ctrl  <= sp_left;
4665
             right_ctrl <= one_right;
4666
             alu_ctrl   <= alu_add16;
4667
             sp_ctrl    <= load_sp;
4668
                                 -- read pc low
4669
                                 pc_ctrl    <= pull_lo_pc;
4670
             addr_ctrl  <= pulls_ad;
4671 22 dilbert57
             next_state <= fetch_state;
4672 19 dilbert57
 
4673
                          --
4674
                          -- Enter here on pshu
4675
                          -- ea holds post byte
4676
                          --
4677
                          when pshu_state =>
4678
             -- decrement up if any registers to be pushed
4679
             left_ctrl  <= up_left;
4680
             right_ctrl <= one_right;
4681
             alu_ctrl   <= alu_sub16;
4682
                                 if ea(7 downto 0) = "00000000" then
4683
               up_ctrl    <= latch_up;
4684
                                 else
4685
               up_ctrl    <= load_up;
4686
                                 end if;
4687
                                 -- write idle bus
4688
                                 if ea(7) = '1' then
4689
               next_state   <= pshu_pcl_state;
4690
                                 elsif ea(6) = '1' then
4691
               next_state   <= pshu_spl_state;
4692
                                 elsif ea(5) = '1' then
4693
                                   next_state   <= pshu_iyl_state;
4694
                                 elsif ea(4) = '1' then
4695
                                   next_state   <= pshu_ixl_state;
4696
                                 elsif ea(3) = '1' then
4697
                                   next_state   <= pshu_dp_state;
4698
                                 elsif ea(2) = '1' then
4699
                                   next_state   <= pshu_accb_state;
4700
                                 elsif ea(1) = '1' then
4701
                                   next_state   <= pshu_acca_state;
4702
                                 elsif ea(0) = '1' then
4703
                                   next_state   <= pshu_cc_state;
4704
                                 else
4705
                                   next_state   <= fetch_state;
4706
                                 end if;
4707
                          --
4708
                          -- push PC onto U stack
4709
                          --
4710
                          when pshu_pcl_state =>
4711
             -- decrement up
4712
             left_ctrl  <= up_left;
4713
             right_ctrl <= one_right;
4714
             alu_ctrl   <= alu_sub16;
4715
             up_ctrl    <= load_up;
4716
                                 -- write pc low
4717
             addr_ctrl  <= pushu_ad;
4718
                            dout_ctrl  <= pc_lo_dout;
4719 22 dilbert57
             next_state <= pshu_pch_state;
4720 19 dilbert57
 
4721
                          when pshu_pch_state =>
4722
             -- decrement up
4723
             left_ctrl  <= up_left;
4724
             right_ctrl <= one_right;
4725
             alu_ctrl   <= alu_sub16;
4726
                                 if ea(6 downto 0) = "0000000" then
4727
               up_ctrl    <= latch_up;
4728
                                 else
4729
               up_ctrl    <= load_up;
4730
                                 end if;
4731
                                 -- write pc hi
4732
             addr_ctrl  <= pushu_ad;
4733
                            dout_ctrl  <= pc_hi_dout;
4734
                                 if ea(6) = '1' then
4735
               next_state   <= pshu_spl_state;
4736
                                 elsif ea(5) = '1' then
4737
                                   next_state   <= pshu_iyl_state;
4738
                                 elsif ea(4) = '1' then
4739
                                   next_state   <= pshu_ixl_state;
4740
                                 elsif ea(3) = '1' then
4741
                                   next_state   <= pshu_dp_state;
4742
                                 elsif ea(2) = '1' then
4743
                                   next_state   <= pshu_accb_state;
4744
                                 elsif ea(1) = '1' then
4745
                                   next_state   <= pshu_acca_state;
4746
                                 elsif ea(0) = '1' then
4747
                                   next_state   <= pshu_cc_state;
4748
                                 else
4749
                                   next_state   <= fetch_state;
4750
                                 end if;
4751
 
4752
                          when pshu_spl_state =>
4753 22 dilbert57
             -- decrement up
4754 19 dilbert57
             left_ctrl  <= up_left;
4755
             right_ctrl <= one_right;
4756
             alu_ctrl   <= alu_sub16;
4757
             up_ctrl    <= load_up;
4758 22 dilbert57
                                 -- write sp low
4759 19 dilbert57
             addr_ctrl  <= pushu_ad;
4760
                            dout_ctrl  <= sp_lo_dout;
4761 22 dilbert57
             next_state <= pshu_sph_state;
4762 19 dilbert57
 
4763
                          when pshu_sph_state =>
4764 22 dilbert57
             -- decrement up
4765 19 dilbert57
             left_ctrl  <= up_left;
4766
             right_ctrl <= one_right;
4767
             alu_ctrl   <= alu_sub16;
4768
                                 if ea(5 downto 0) = "000000" then
4769
               up_ctrl    <= latch_up;
4770
                                 else
4771
               up_ctrl    <= load_up;
4772
                                 end if;
4773
                                 -- write sp hi
4774
             addr_ctrl  <= pushu_ad;
4775
                            dout_ctrl  <= sp_hi_dout;
4776
                                 if ea(5) = '1' then
4777
                                   next_state   <= pshu_iyl_state;
4778
                                 elsif ea(4) = '1' then
4779
                                   next_state   <= pshu_ixl_state;
4780
                                 elsif ea(3) = '1' then
4781
                                   next_state   <= pshu_dp_state;
4782
                                 elsif ea(2) = '1' then
4783
                                   next_state   <= pshu_accb_state;
4784
                                 elsif ea(1) = '1' then
4785
                                   next_state   <= pshu_acca_state;
4786
                                 elsif ea(0) = '1' then
4787
                                   next_state   <= pshu_cc_state;
4788
                                 else
4789
                                   next_state   <= fetch_state;
4790
                                 end if;
4791
 
4792
                          when pshu_iyl_state =>
4793 22 dilbert57
             -- decrement up
4794 19 dilbert57
             left_ctrl  <= up_left;
4795
             right_ctrl <= one_right;
4796
             alu_ctrl   <= alu_sub16;
4797
             up_ctrl    <= load_up;
4798
                                 -- write iy low
4799
             addr_ctrl  <= pushu_ad;
4800
                            dout_ctrl  <= iy_lo_dout;
4801 22 dilbert57
             next_state <= pshu_iyh_state;
4802 19 dilbert57
 
4803
                          when pshu_iyh_state =>
4804 22 dilbert57
             -- decrement up
4805 19 dilbert57
             left_ctrl  <= up_left;
4806
             right_ctrl <= one_right;
4807
             alu_ctrl   <= alu_sub16;
4808
                                 if ea(4 downto 0) = "00000" then
4809
               up_ctrl    <= latch_up;
4810
                                 else
4811
               up_ctrl    <= load_up;
4812
                                 end if;
4813
                                 -- write iy hi
4814
             addr_ctrl  <= pushu_ad;
4815
                            dout_ctrl  <= iy_hi_dout;
4816
                                 if ea(4) = '1' then
4817
                                   next_state   <= pshu_ixl_state;
4818
                                 elsif ea(3) = '1' then
4819
                                   next_state   <= pshu_dp_state;
4820
                                 elsif ea(2) = '1' then
4821
                                   next_state   <= pshu_accb_state;
4822
                                 elsif ea(1) = '1' then
4823
                                   next_state   <= pshu_acca_state;
4824
                                 elsif ea(0) = '1' then
4825
                                   next_state   <= pshu_cc_state;
4826
                                 else
4827
                                   next_state   <= fetch_state;
4828
                                 end if;
4829
 
4830
                          when pshu_ixl_state =>
4831 22 dilbert57
             -- decrement up
4832 19 dilbert57
             left_ctrl  <= up_left;
4833
             right_ctrl <= one_right;
4834
             alu_ctrl   <= alu_sub16;
4835
             up_ctrl    <= load_up;
4836
                                 -- write ix low
4837
             addr_ctrl  <= pushu_ad;
4838
                            dout_ctrl  <= ix_lo_dout;
4839 22 dilbert57
             next_state <= pshu_ixh_state;
4840 19 dilbert57
 
4841
                          when pshu_ixh_state =>
4842 22 dilbert57
             -- decrement up
4843 19 dilbert57
             left_ctrl  <= up_left;
4844
             right_ctrl <= one_right;
4845
             alu_ctrl   <= alu_sub16;
4846
                                 if ea(3 downto 0) = "0000" then
4847
               up_ctrl    <= latch_up;
4848
                                 else
4849
               up_ctrl    <= load_up;
4850
                                 end if;
4851
                                 -- write ix hi
4852
             addr_ctrl  <= pushu_ad;
4853
                            dout_ctrl  <= ix_hi_dout;
4854
                                 if ea(3) = '1' then
4855
                                   next_state   <= pshu_dp_state;
4856
                                 elsif ea(2) = '1' then
4857
                                   next_state   <= pshu_accb_state;
4858
                                 elsif ea(1) = '1' then
4859
                                   next_state   <= pshu_acca_state;
4860
                                 elsif ea(0) = '1' then
4861
                                   next_state   <= pshu_cc_state;
4862
                                 else
4863
                                   next_state   <= fetch_state;
4864
                                 end if;
4865
 
4866
                          when pshu_dp_state =>
4867 22 dilbert57
             -- decrement up
4868 19 dilbert57
             left_ctrl  <= up_left;
4869
             right_ctrl <= one_right;
4870
             alu_ctrl   <= alu_sub16;
4871
                                 if ea(2 downto 0) = "000" then
4872
               up_ctrl    <= latch_up;
4873
                                 else
4874
               up_ctrl    <= load_up;
4875
                                 end if;
4876 22 dilbert57
                                 -- write dp
4877 19 dilbert57
             addr_ctrl  <= pushu_ad;
4878
                            dout_ctrl  <= dp_dout;
4879
                                 if ea(2) = '1' then
4880
                                   next_state   <= pshu_accb_state;
4881
                                 elsif ea(1) = '1' then
4882
                                   next_state   <= pshu_acca_state;
4883
                                 elsif ea(0) = '1' then
4884
                                   next_state   <= pshu_cc_state;
4885
                                 else
4886
                                   next_state   <= fetch_state;
4887
                                 end if;
4888
 
4889
                          when pshu_accb_state =>
4890
             -- decrement up
4891
             left_ctrl  <= up_left;
4892
             right_ctrl <= one_right;
4893
             alu_ctrl   <= alu_sub16;
4894
                                 if ea(1 downto 0) = "00" then
4895
               up_ctrl    <= latch_up;
4896
                                 else
4897
               up_ctrl    <= load_up;
4898
                                 end if;
4899
                                 -- write accb
4900
             addr_ctrl  <= pushu_ad;
4901
                            dout_ctrl  <= accb_dout;
4902
                                 if ea(1) = '1' then
4903
                                   next_state   <= pshu_acca_state;
4904
                                 elsif ea(0) = '1' then
4905
                                   next_state   <= pshu_cc_state;
4906
                                 else
4907
                                   next_state   <= fetch_state;
4908
                                 end if;
4909
 
4910
                          when pshu_acca_state =>
4911 22 dilbert57
             -- decrement up
4912 19 dilbert57
             left_ctrl  <= up_left;
4913
             right_ctrl <= one_right;
4914
             alu_ctrl   <= alu_sub16;
4915
                                 if ea(0) = '0' then
4916
               up_ctrl    <= latch_up;
4917
                                 else
4918
               up_ctrl    <= load_up;
4919
                                 end if;
4920
                                 -- write acca
4921
             addr_ctrl  <= pushu_ad;
4922
                            dout_ctrl  <= acca_dout;
4923
                                 if ea(0) = '1' then
4924
                                   next_state   <= pshu_cc_state;
4925
                                 else
4926
                                   next_state   <= fetch_state;
4927
                                 end if;
4928
 
4929
                          when pshu_cc_state =>
4930
             -- idle up
4931
                                 -- write cc
4932
             addr_ctrl  <= pushu_ad;
4933
                            dout_ctrl  <= cc_dout;
4934 22 dilbert57
             next_state <= fetch_state;
4935 19 dilbert57
 
4936
                          --
4937
                          -- enter here on PULU
4938
                          -- ea hold register mask
4939
                          --
4940
                          when pulu_state =>
4941
                                 -- idle UP
4942
                                 -- idle bus
4943
                                 if ea(0) = '1' then
4944
                                   next_state <= pulu_cc_state;
4945
                                 elsif ea(1) = '1' then
4946
                                   next_state <= pulu_acca_state;
4947
                                 elsif ea(2) = '1' then
4948
                                   next_state <= pulu_accb_state;
4949
                                 elsif ea(3) = '1' then
4950
                                   next_state <= pulu_dp_state;
4951
                                 elsif ea(4) = '1' then
4952
                                   next_state <= pulu_ixh_state;
4953
                                 elsif ea(5) = '1' then
4954
                                   next_state <= pulu_iyh_state;
4955
                                 elsif ea(6) = '1' then
4956
               next_state <= pulu_sph_state;
4957
                                 elsif ea(7) = '1' then
4958
               next_state <= pulu_pch_state;
4959
                                 else
4960
                                   next_state <= fetch_state;
4961
                                 end if;
4962
 
4963
                          when pulu_cc_state =>
4964
                                 -- increment up
4965
             left_ctrl  <= up_left;
4966
             right_ctrl <= one_right;
4967
             alu_ctrl   <= alu_add16;
4968
             up_ctrl    <= load_up;
4969
                                 -- read cc
4970
             cc_ctrl    <= pull_cc;
4971
             addr_ctrl  <= pullu_ad;
4972
                                 if ea(1) = '1' then
4973
                                   next_state <= pulu_acca_state;
4974
                                 elsif ea(2) = '1' then
4975
                                   next_state <= pulu_accb_state;
4976
                                 elsif ea(3) = '1' then
4977
                                   next_state <= pulu_dp_state;
4978
                                 elsif ea(4) = '1' then
4979
                                   next_state <= pulu_ixh_state;
4980
                                 elsif ea(5) = '1' then
4981
                                   next_state <= pulu_iyh_state;
4982
                                 elsif ea(6) = '1' then
4983
               next_state <= pulu_sph_state;
4984
                                 elsif ea(7) = '1' then
4985
               next_state <= pulu_pch_state;
4986
                                 else
4987
                                   next_state <= fetch_state;
4988
                                 end if;
4989
 
4990
                          when pulu_acca_state =>
4991
                                 -- increment up
4992
             left_ctrl  <= up_left;
4993
             right_ctrl <= one_right;
4994
             alu_ctrl   <= alu_add16;
4995
             up_ctrl    <= load_up;
4996
                                 -- read acca
4997
                                 acca_ctrl  <= pull_acca;
4998
             addr_ctrl  <= pullu_ad;
4999
                                 if ea(2) = '1' then
5000
                                   next_state <= pulu_accb_state;
5001
                                 elsif ea(3) = '1' then
5002
                                   next_state <= pulu_dp_state;
5003
                                 elsif ea(4) = '1' then
5004
                                   next_state <= pulu_ixh_state;
5005
                                 elsif ea(5) = '1' then
5006
                                   next_state <= pulu_iyh_state;
5007
                                 elsif ea(6) = '1' then
5008
               next_state <= pulu_sph_state;
5009
                                 elsif ea(7) = '1' then
5010
               next_state <= pulu_pch_state;
5011
                                 else
5012
                                   next_state <= fetch_state;
5013
                                 end if;
5014
 
5015
                          when pulu_accb_state =>
5016
                                 -- increment up
5017
             left_ctrl  <= up_left;
5018
             right_ctrl <= one_right;
5019
             alu_ctrl   <= alu_add16;
5020
             up_ctrl    <= load_up;
5021
                                 -- read accb
5022
                                 accb_ctrl  <= pull_accb;
5023
             addr_ctrl  <= pullu_ad;
5024
                                 if ea(3) = '1' then
5025
                                   next_state <= pulu_dp_state;
5026
                                 elsif ea(4) = '1' then
5027
                                   next_state <= pulu_ixh_state;
5028
                                 elsif ea(5) = '1' then
5029
                                   next_state <= pulu_iyh_state;
5030
                                 elsif ea(6) = '1' then
5031
               next_state <= pulu_sph_state;
5032
                                 elsif ea(7) = '1' then
5033
               next_state <= pulu_pch_state;
5034
                                 else
5035
                                   next_state <= fetch_state;
5036
                                 end if;
5037
 
5038
                          when pulu_dp_state =>
5039
                                 -- increment up
5040
             left_ctrl  <= up_left;
5041
             right_ctrl <= one_right;
5042
             alu_ctrl   <= alu_add16;
5043
             up_ctrl    <= load_up;
5044
                                 -- read dp
5045
                                 dp_ctrl    <= pull_dp;
5046
             addr_ctrl  <= pullu_ad;
5047
                                 if ea(4) = '1' then
5048
                                   next_state <= pulu_ixh_state;
5049
                                 elsif ea(5) = '1' then
5050
                                   next_state <= pulu_iyh_state;
5051
                                 elsif ea(6) = '1' then
5052
               next_state <= pulu_sph_state;
5053
                                 elsif ea(7) = '1' then
5054
               next_state <= pulu_pch_state;
5055
                                 else
5056
                                   next_state <= fetch_state;
5057
                                 end if;
5058
 
5059
                          when pulu_ixh_state =>
5060
             -- increment up
5061
             left_ctrl  <= up_left;
5062
             right_ctrl <= one_right;
5063
             alu_ctrl   <= alu_add16;
5064
             up_ctrl    <= load_up;
5065 22 dilbert57
                                 -- read ix hi
5066 19 dilbert57
                                 ix_ctrl    <= pull_hi_ix;
5067
             addr_ctrl  <= pullu_ad;
5068 22 dilbert57
             next_state <= pulu_ixl_state;
5069 19 dilbert57
 
5070
                          when pulu_ixl_state =>
5071
                                 -- increment up
5072
             left_ctrl  <= up_left;
5073
             right_ctrl <= one_right;
5074
             alu_ctrl   <= alu_add16;
5075
             up_ctrl    <= load_up;
5076
                                 -- read ix low
5077
                                 ix_ctrl    <= pull_lo_ix;
5078
             addr_ctrl  <= pullu_ad;
5079
                                 if ea(5) = '1' then
5080
                                   next_state <= pulu_iyh_state;
5081
                                 elsif ea(6) = '1' then
5082
               next_state <= pulu_sph_state;
5083
                                 elsif ea(7) = '1' then
5084
               next_state <= pulu_pch_state;
5085
                                 else
5086
                                   next_state <= fetch_state;
5087
                                 end if;
5088
 
5089
                          when pulu_iyh_state =>
5090
             -- increment up
5091
             left_ctrl  <= up_left;
5092
             right_ctrl <= one_right;
5093
             alu_ctrl   <= alu_add16;
5094
             up_ctrl    <= load_up;
5095 22 dilbert57
                                 -- read iy hi
5096 19 dilbert57
                                 iy_ctrl    <= pull_hi_iy;
5097
             addr_ctrl  <= pullu_ad;
5098 22 dilbert57
             next_state <= pulu_iyl_state;
5099 19 dilbert57
 
5100
                          when pulu_iyl_state =>
5101
             -- increment up
5102
             left_ctrl  <= up_left;
5103
             right_ctrl <= one_right;
5104
             alu_ctrl   <= alu_add16;
5105
             up_ctrl    <= load_up;
5106
                                 -- read iy low
5107
                                 iy_ctrl    <= pull_lo_iy;
5108
             addr_ctrl  <= pullu_ad;
5109
                                 if ea(6) = '1' then
5110
               next_state <= pulu_sph_state;
5111
                                 elsif ea(7) = '1' then
5112
               next_state <= pulu_pch_state;
5113
                                 else
5114
                                   next_state <= fetch_state;
5115
                                 end if;
5116
 
5117
                          when pulu_sph_state =>
5118
             -- increment up
5119
             left_ctrl  <= up_left;
5120
             right_ctrl <= one_right;
5121
             alu_ctrl   <= alu_add16;
5122
             up_ctrl    <= load_up;
5123 22 dilbert57
                                 -- read sp hi
5124 19 dilbert57
                                 sp_ctrl    <= pull_hi_sp;
5125
             addr_ctrl  <= pullu_ad;
5126 22 dilbert57
             next_state <= pulu_spl_state;
5127 19 dilbert57
 
5128
                          when pulu_spl_state =>
5129
                                 -- increment up
5130
             left_ctrl  <= up_left;
5131
             right_ctrl <= one_right;
5132
             alu_ctrl   <= alu_add16;
5133
             up_ctrl    <= load_up;
5134
                                 -- read sp low
5135
                                 sp_ctrl    <= pull_lo_sp;
5136
             addr_ctrl  <= pullu_ad;
5137
                                 if ea(7) = '1' then
5138
               next_state <= pulu_pch_state;
5139
                                 else
5140
                                   next_state <= fetch_state;
5141
                                 end if;
5142
 
5143
                          when pulu_pch_state =>
5144
             -- increment up
5145
             left_ctrl  <= up_left;
5146
             right_ctrl <= one_right;
5147
             alu_ctrl   <= alu_add16;
5148
             up_ctrl    <= load_up;
5149
                                 -- pull pc hi
5150
                                 pc_ctrl    <= pull_hi_pc;
5151
             addr_ctrl  <= pullu_ad;
5152 22 dilbert57
             next_state <= pulu_pcl_state;
5153 19 dilbert57
 
5154
                          when pulu_pcl_state =>
5155
                                 -- increment up
5156
             left_ctrl  <= up_left;
5157
             right_ctrl <= one_right;
5158
             alu_ctrl   <= alu_add16;
5159
             up_ctrl    <= load_up;
5160
                                 -- read pc low
5161
                                 pc_ctrl    <= pull_lo_pc;
5162
             addr_ctrl  <= pullu_ad;
5163 22 dilbert57
             next_state <= fetch_state;
5164 19 dilbert57
 
5165
                          --
5166
                          -- pop the Condition codes
5167
                          --
5168
                          when rti_cc_state =>
5169
                                 -- increment sp
5170
             left_ctrl  <= sp_left;
5171
             right_ctrl <= one_right;
5172
             alu_ctrl   <= alu_add16;
5173
             sp_ctrl    <= load_sp;
5174
                                 -- read cc
5175
             cc_ctrl    <= pull_cc;
5176
             addr_ctrl  <= pulls_ad;
5177 22 dilbert57
             next_state <= rti_entire_state;
5178 19 dilbert57
 
5179
                          --
5180
                          -- Added RTI cycle 11th July 2006 John Kent.
5181
                          -- test the "Entire" Flag
5182
                          -- that has just been popped off the stack
5183
                          --
5184
                          when rti_entire_state =>
5185
                                 --
5186
                                 -- The Entire flag must be recovered from the stack
5187
                                 -- before testing.
5188
                                 --
5189
                                 if cc(EBIT) = '1' then
5190
               next_state   <= rti_acca_state;
5191
                                 else
5192
               next_state   <= rti_pch_state;
5193
                                 end if;
5194
 
5195
                          when rti_acca_state =>
5196
                                 -- increment sp
5197
             left_ctrl  <= sp_left;
5198
             right_ctrl <= one_right;
5199
             alu_ctrl   <= alu_add16;
5200
             sp_ctrl    <= load_sp;
5201
                                 -- read acca
5202
                                 acca_ctrl  <= pull_acca;
5203
             addr_ctrl  <= pulls_ad;
5204 22 dilbert57
             next_state <= rti_accb_state;
5205 19 dilbert57
 
5206
                          when rti_accb_state =>
5207
                                 -- increment sp
5208
             left_ctrl  <= sp_left;
5209
             right_ctrl <= one_right;
5210
             alu_ctrl   <= alu_add16;
5211
             sp_ctrl    <= load_sp;
5212
                                 -- read accb
5213
                                 accb_ctrl  <= pull_accb;
5214
             addr_ctrl  <= pulls_ad;
5215 22 dilbert57
             next_state <= rti_dp_state;
5216 19 dilbert57
 
5217
                          when rti_dp_state =>
5218
                                 -- increment sp
5219
             left_ctrl  <= sp_left;
5220
             right_ctrl <= one_right;
5221
             alu_ctrl   <= alu_add16;
5222
             sp_ctrl    <= load_sp;
5223
                                 -- read dp
5224
                                 dp_ctrl    <= pull_dp;
5225
             addr_ctrl  <= pulls_ad;
5226 22 dilbert57
             next_state <= rti_ixh_state;
5227 19 dilbert57
 
5228
                          when rti_ixh_state =>
5229
                                 -- increment sp
5230
             left_ctrl  <= sp_left;
5231
             right_ctrl <= one_right;
5232
             alu_ctrl   <= alu_add16;
5233
             sp_ctrl    <= load_sp;
5234
                                 -- read ix hi
5235
                                 ix_ctrl    <= pull_hi_ix;
5236
             addr_ctrl  <= pulls_ad;
5237 22 dilbert57
             next_state <= rti_ixl_state;
5238 19 dilbert57
 
5239
                          when rti_ixl_state =>
5240
                                 -- increment sp
5241
             left_ctrl  <= sp_left;
5242
             right_ctrl <= one_right;
5243
             alu_ctrl   <= alu_add16;
5244
             sp_ctrl    <= load_sp;
5245
                                 -- read ix low
5246
                                 ix_ctrl    <= pull_lo_ix;
5247
             addr_ctrl  <= pulls_ad;
5248 22 dilbert57
             next_state <= rti_iyh_state;
5249 19 dilbert57
 
5250
                          when rti_iyh_state =>
5251
                                 -- increment sp
5252
             left_ctrl  <= sp_left;
5253
             right_ctrl <= one_right;
5254
             alu_ctrl   <= alu_add16;
5255
             sp_ctrl    <= load_sp;
5256
                                 -- read iy hi
5257
                                 iy_ctrl    <= pull_hi_iy;
5258
             addr_ctrl  <= pulls_ad;
5259 22 dilbert57
             next_state <= rti_iyl_state;
5260 19 dilbert57
 
5261
                          when rti_iyl_state =>
5262
                                 -- increment sp
5263
             left_ctrl  <= sp_left;
5264
             right_ctrl <= one_right;
5265
             alu_ctrl   <= alu_add16;
5266
             sp_ctrl    <= load_sp;
5267
                                 -- read iy low
5268
                                 iy_ctrl    <= pull_lo_iy;
5269
             addr_ctrl  <= pulls_ad;
5270 22 dilbert57
             next_state <= rti_uph_state;
5271 19 dilbert57
 
5272
 
5273
                          when rti_uph_state =>
5274
                                 -- increment sp
5275
             left_ctrl  <= sp_left;
5276
             right_ctrl <= one_right;
5277
             alu_ctrl   <= alu_add16;
5278
             sp_ctrl    <= load_sp;
5279
                                 -- read up hi
5280
                                 up_ctrl    <= pull_hi_up;
5281
             addr_ctrl  <= pulls_ad;
5282 22 dilbert57
             next_state <= rti_upl_state;
5283 19 dilbert57
 
5284
                          when rti_upl_state =>
5285
                                 -- increment sp
5286
             left_ctrl  <= sp_left;
5287
             right_ctrl <= one_right;
5288
             alu_ctrl   <= alu_add16;
5289
             sp_ctrl    <= load_sp;
5290
                                 -- read up low
5291
             up_ctrl    <= pull_lo_up;
5292
             addr_ctrl  <= pulls_ad;
5293 22 dilbert57
             next_state <= rti_pch_state;
5294 19 dilbert57
 
5295
                          when rti_pch_state =>
5296
                  -- increment sp
5297
             left_ctrl  <= sp_left;
5298
             right_ctrl <= one_right;
5299
             alu_ctrl   <= alu_add16;
5300
             sp_ctrl    <= load_sp;
5301
                                 -- pull pc hi
5302
                                 pc_ctrl    <= pull_hi_pc;
5303
             addr_ctrl  <= pulls_ad;
5304 22 dilbert57
             next_state <= rti_pcl_state;
5305 19 dilbert57
 
5306
                          when rti_pcl_state =>
5307
                                 -- increment sp
5308
             left_ctrl  <= sp_left;
5309
             right_ctrl <= one_right;
5310
             alu_ctrl   <= alu_add16;
5311
             sp_ctrl    <= load_sp;
5312
                  -- pull pc low
5313
                                 pc_ctrl    <= pull_lo_pc;
5314
             addr_ctrl  <= pulls_ad;
5315 22 dilbert57
             next_state <= fetch_state;
5316 19 dilbert57
 
5317
                          --
5318 22 dilbert57
                          -- here on IRQ or NMI interrupt
5319 19 dilbert57
                          -- pre decrement the sp
5320 22 dilbert57
                          -- Idle bus cycle
5321 19 dilbert57
                          --
5322 22 dilbert57
                          when int_nmiirq_state =>
5323 19 dilbert57
             -- decrement sp
5324
             left_ctrl  <= sp_left;
5325
             right_ctrl <= one_right;
5326
             alu_ctrl   <= alu_sub16;
5327
             sp_ctrl    <= load_sp;
5328 22 dilbert57
             next_state <= int_entire_state;
5329 19 dilbert57
 
5330
                          --
5331
                          -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
5332
                          -- clear Entire Flag on FIRQ
5333
                          -- before stacking all registers
5334
                          --
5335
                          when int_entire_state =>
5336 22 dilbert57
             -- set entire flag
5337
             alu_ctrl   <= alu_see;
5338
             cc_ctrl    <= load_cc;
5339
             next_state <= int_pcl_state;
5340
 
5341
                          --
5342
                          -- here on FIRQ interrupt
5343
                          -- pre decrement the sp
5344
                          -- Idle bus cycle
5345
                          --
5346
                          when int_firq_state =>
5347
             -- decrement sp
5348 19 dilbert57
             left_ctrl  <= sp_left;
5349 22 dilbert57
             right_ctrl <= one_right;
5350
             alu_ctrl   <= alu_sub16;
5351
             sp_ctrl    <= load_sp;
5352
             next_state <= int_fast_state;
5353
                          --
5354
                          -- clear Entire Flag on FIRQ
5355
                          -- before stacking all registers
5356
                          --
5357
                          when int_fast_state =>
5358
             -- clear entire flag
5359
             alu_ctrl   <= alu_cle;
5360 19 dilbert57
             cc_ctrl    <= load_cc;
5361 22 dilbert57
             next_state <= int_pcl_state;
5362 19 dilbert57
 
5363
                          when int_pcl_state =>
5364
             -- decrement sp
5365
             left_ctrl  <= sp_left;
5366
             right_ctrl <= one_right;
5367
             alu_ctrl   <= alu_sub16;
5368
             sp_ctrl    <= load_sp;
5369
                                 -- write pc low
5370
             addr_ctrl  <= pushs_ad;
5371
                            dout_ctrl  <= pc_lo_dout;
5372 22 dilbert57
             next_state <= int_pch_state;
5373 19 dilbert57
 
5374
                          when int_pch_state =>
5375
             -- decrement sp
5376
             left_ctrl  <= sp_left;
5377
             right_ctrl <= one_right;
5378
             alu_ctrl   <= alu_sub16;
5379
             sp_ctrl    <= load_sp;
5380
                                 -- write pc hi
5381
             addr_ctrl  <= pushs_ad;
5382
                            dout_ctrl  <= pc_hi_dout;
5383
                                 if cc(EBIT) = '1' then
5384
               next_state   <= int_upl_state;
5385
                                 else
5386
               next_state   <= int_cc_state;
5387
                                 end if;
5388
 
5389
                          when int_upl_state =>
5390
             -- decrement sp
5391
             left_ctrl  <= sp_left;
5392
             right_ctrl <= one_right;
5393
             alu_ctrl   <= alu_sub16;
5394
             sp_ctrl    <= load_sp;
5395
                                 -- write up low
5396
             addr_ctrl  <= pushs_ad;
5397
                            dout_ctrl  <= up_lo_dout;
5398 22 dilbert57
             next_state <= int_uph_state;
5399 19 dilbert57
 
5400
                          when int_uph_state =>
5401
             -- decrement sp
5402
             left_ctrl  <= sp_left;
5403
             right_ctrl <= one_right;
5404
             alu_ctrl   <= alu_sub16;
5405
             sp_ctrl    <= load_sp;
5406
                                 -- write ix hi
5407
             addr_ctrl  <= pushs_ad;
5408
                            dout_ctrl  <= up_hi_dout;
5409 22 dilbert57
             next_state <= int_iyl_state;
5410 19 dilbert57
 
5411
                          when int_iyl_state =>
5412
             -- decrement sp
5413
             left_ctrl  <= sp_left;
5414
             right_ctrl <= one_right;
5415
             alu_ctrl   <= alu_sub16;
5416
             sp_ctrl    <= load_sp;
5417
                                 -- write ix low
5418
             addr_ctrl  <= pushs_ad;
5419
                            dout_ctrl  <= iy_lo_dout;
5420 22 dilbert57
             next_state <= int_iyh_state;
5421 19 dilbert57
 
5422
                          when int_iyh_state =>
5423
             -- decrement sp
5424
             left_ctrl  <= sp_left;
5425
             right_ctrl <= one_right;
5426
             alu_ctrl   <= alu_sub16;
5427
             sp_ctrl    <= load_sp;
5428
                                 -- write ix hi
5429
             addr_ctrl  <= pushs_ad;
5430
                            dout_ctrl  <= iy_hi_dout;
5431 22 dilbert57
             next_state <= int_ixl_state;
5432 19 dilbert57
 
5433
                          when int_ixl_state =>
5434
             -- decrement sp
5435
             left_ctrl  <= sp_left;
5436
             right_ctrl <= one_right;
5437
             alu_ctrl   <= alu_sub16;
5438
             sp_ctrl    <= load_sp;
5439
                                 -- write ix low
5440
             addr_ctrl  <= pushs_ad;
5441
                            dout_ctrl  <= ix_lo_dout;
5442 22 dilbert57
             next_state <= int_ixh_state;
5443 19 dilbert57
 
5444
                          when int_ixh_state =>
5445
             -- decrement sp
5446
             left_ctrl  <= sp_left;
5447
             right_ctrl <= one_right;
5448
             alu_ctrl   <= alu_sub16;
5449
             sp_ctrl    <= load_sp;
5450
                                 -- write ix hi
5451
             addr_ctrl  <= pushs_ad;
5452
                            dout_ctrl  <= ix_hi_dout;
5453 22 dilbert57
             next_state <= int_dp_state;
5454 19 dilbert57
 
5455
                          when int_dp_state =>
5456
             -- decrement sp
5457
             left_ctrl  <= sp_left;
5458
             right_ctrl <= one_right;
5459
             alu_ctrl   <= alu_sub16;
5460
             sp_ctrl    <= load_sp;
5461
                                 -- write accb
5462
             addr_ctrl  <= pushs_ad;
5463
                            dout_ctrl  <= dp_dout;
5464 22 dilbert57
             next_state <= int_accb_state;
5465 19 dilbert57
 
5466
                          when int_accb_state =>
5467
             -- decrement sp
5468
             left_ctrl  <= sp_left;
5469
             right_ctrl <= one_right;
5470
             alu_ctrl   <= alu_sub16;
5471
             sp_ctrl    <= load_sp;
5472
                                 -- write accb
5473
             addr_ctrl  <= pushs_ad;
5474
                            dout_ctrl  <= accb_dout;
5475 22 dilbert57
             next_state <= int_acca_state;
5476 19 dilbert57
 
5477
                          when int_acca_state =>
5478
             -- decrement sp
5479
             left_ctrl  <= sp_left;
5480
             right_ctrl <= one_right;
5481
             alu_ctrl   <= alu_sub16;
5482
             sp_ctrl    <= load_sp;
5483
                                 -- write acca
5484
             addr_ctrl  <= pushs_ad;
5485
                            dout_ctrl  <= acca_dout;
5486 22 dilbert57
             next_state <= int_cc_state;
5487 19 dilbert57
 
5488
                          when int_cc_state =>
5489
                                 -- write cc
5490
             addr_ctrl  <= pushs_ad;
5491
                            dout_ctrl  <= cc_dout;
5492
                                 case iv is
5493
                                 when NMI_VEC =>
5494 22 dilbert57
                              next_state <= int_maskif_state;
5495 19 dilbert57
                                 when SWI_VEC =>
5496 22 dilbert57
                              next_state <= int_maskif_state;
5497
                                 when FIRQ_VEC =>
5498
                              next_state <= int_maskif_state;
5499 19 dilbert57
                                 when IRQ_VEC =>
5500 22 dilbert57
                              next_state <= int_maski_state;
5501 19 dilbert57
                                 when SWI2_VEC =>
5502
                    next_state <= vect_hi_state;
5503
                                 when SWI3_VEC =>
5504
                    next_state <= vect_hi_state;
5505
                                 when others =>
5506
                                   if op_code = "00111100" then -- CWAI
5507
                                          next_state <= int_cwai_state;
5508
                                        else
5509
                      next_state <= rti_cc_state; -- spurious interrupt, do a RTI
5510
                                        end if;
5511
                                 end case;
5512
 
5513
                          --
5514
                          -- wait here for an inteerupt
5515
                          --
5516
                          when int_cwai_state =>
5517
                            if (nmi_req = '1') and (nmi_ack='0') then
5518
                                        iv_ctrl    <= nmi_iv;
5519
                                   nmi_ctrl   <= set_nmi;
5520 22 dilbert57
                              next_state <= int_maskif_state;
5521 19 dilbert57
                            else
5522
                                   --
5523
                                        -- nmi request is not cleared until nmi input goes low
5524
                                        --
5525
                                   if (nmi_req = '0') and (nmi_ack='1') then
5526
                                     nmi_ctrl <= reset_nmi;
5527
                                        end if;
5528
                                        --
5529 22 dilbert57
                                        -- FIRQ is level sensitive
5530
                                        --
5531
               if (firq = '1') and (cc(FBIT) = '0') then
5532
                                          iv_ctrl    <= firq_iv;
5533
                                next_state <= int_maskif_state;
5534
                                        --
5535 19 dilbert57
                                        -- IRQ is level sensitive
5536
                                        --
5537 22 dilbert57
                                   elsif (irq = '1') and (cc(IBIT) = '0') then
5538 19 dilbert57
                                          iv_ctrl    <= irq_iv;
5539 22 dilbert57
                                next_state <= int_maski_state;
5540 19 dilbert57
               else
5541 22 dilbert57
                 iv_ctrl    <= reset_iv;
5542 19 dilbert57
                      next_state <= int_cwai_state;
5543
                                        end if;
5544
                                 end if;
5545
 
5546 22 dilbert57
                          when int_maski_state =>
5547
                                 alu_ctrl   <= alu_sei;
5548 19 dilbert57
                                 cc_ctrl    <= load_cc;
5549 22 dilbert57
             next_state <= vect_hi_state;
5550 19 dilbert57
 
5551 22 dilbert57
                          when int_maskif_state =>
5552
                            alu_ctrl   <= alu_seif;
5553
                                 cc_ctrl    <= load_cc;
5554
             next_state <= vect_hi_state;
5555
 
5556 19 dilbert57
                          --
5557
                          -- According to the 6809 programming manual:
5558
                          -- If an interrupt is received and is masked 
5559
                          -- or lasts for less than three cycles, the PC 
5560
                          -- will advance to the next instruction.
5561
                          -- If an interrupt is unmasked and lasts
5562
                          -- for more than three cycles, an interrupt
5563
                          -- will be generated.
5564
                          -- Note that I don't wait 3 clock cycles.
5565
                          -- John Kent 11th July 2006
5566
                          --
5567
                          when sync_state =>
5568
                            if (nmi_req = '1') and (nmi_ack='0') then
5569
                                        iv_ctrl    <= nmi_iv;
5570
                                   nmi_ctrl   <= set_nmi;
5571 22 dilbert57
               next_state <= int_nmiirq_state;
5572 19 dilbert57
                            else
5573
                                   --
5574
                                        -- nmi request is not cleared until nmi input goes low
5575
                                        --
5576
                                   if (nmi_req = '0') and (nmi_ack='1') then
5577 22 dilbert57
                                          iv_ctrl  <= reset_iv;
5578 19 dilbert57
                                     nmi_ctrl <= reset_nmi;
5579
                                        end if;
5580
                                        --
5581 22 dilbert57
                                        -- FIRQ is level sensitive
5582 19 dilbert57
                                        --
5583 22 dilbert57
               if (firq = '1') then
5584
                                          if (cc(FBIT) = '0') then
5585
                   iv_ctrl    <= firq_iv;
5586
                   next_state <= int_firq_state;
5587 19 dilbert57
                                          else
5588 22 dilbert57
                   iv_ctrl    <= reset_iv;
5589 19 dilbert57
                                  next_state <= fetch_state;
5590
                                          end if;
5591 22 dilbert57
                                        --
5592
                                        -- IRQ is level sensitive
5593
                                        --
5594
                                   elsif (irq = '1') then
5595
                                          if (cc(IBIT) = '0') then
5596
                   iv_ctrl    <= irq_iv;
5597
                   next_state <= int_nmiirq_state;
5598 19 dilbert57
                                          else
5599 22 dilbert57
                   iv_ctrl    <= reset_iv;
5600 19 dilbert57
                                  next_state <= fetch_state;
5601
                                          end if;
5602
               else
5603 22 dilbert57
                 iv_ctrl    <= reset_iv;
5604 19 dilbert57
                      next_state <= sync_state;
5605
                                        end if;
5606
                                 end if;
5607
 
5608
 
5609
                          when halt_state =>
5610
                                 if halt = '1' then
5611
               next_state   <= halt_state;
5612
                                 else
5613 22 dilbert57
                                   next_state   <= fetch_state;
5614 19 dilbert57
                                 end if;
5615
 
5616
                          when others => -- halt on undefine states
5617
                            next_state <= error_state;
5618
                  end case;
5619
end process;
5620
 
5621
end rtl;
5622
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.