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[/] [System09/] [branches/] [mkfiles_rev1/] [rtl/] [VHDL/] [cpu09new.vhd] - Blame information for rev 162

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1 19 dilbert57
-- $Id: cpu09new.vhd,v 1.1 2007-12-09 16:06:03 dilbert57 Exp $
2
--===========================================================================----
3
--
4
--  S Y N T H E S I Z A B L E    CPU09 - 6809 compatible CPU Core
5
--
6
--  www.OpenCores.Org - September 2003
7
--  This core adheres to the GNU public license
8
--
9
-- File name      : cpu09.vhd
10
--
11
-- Purpose        : 6809 CPU core
12
--
13
-- Dependencies   : ieee.Std_Logic_1164
14
--                  ieee.std_logic_unsigned
15
--
16
-- Uses           : None
17
--
18
-- Author         : John E. Kent
19
--                  dilbert57@opencores.org
20
--
21
--===========================================================================----
22
--
23
-- Revision History:
24
--===========================================================================--
25
--
26
-- Version 0.1 - 26 June 2003 - John Kent
27
-- Added extra level in state stack
28
-- fixed some calls to the extended addressing state
29
--
30
-- Version 0.2 - 5 Sept 2003 - John Kent
31
-- Fixed 16 bit indexed offset (was doing read rather than fetch)
32
-- Added/Fixed STY and STS instructions.
33
-- ORCC_STATE ANDed CC state rather than ORed it - Now fixed
34
-- CMPX Loaded ACCA and ACCB - Now fixed
35
--
36
-- Version 1.0 - 6 Sep 2003 - John Kent
37
-- Initial release to Open Cores
38
-- reversed clock edge
39
--
40
-- Version 1.1 - 29 November 2003 John kent
41
--      ACCA and ACCB indexed offsets are 2's complement.
42
-- ALU Right Mux now sign extends ACCA & ACCB offsets
43
-- Absolute Indirect addressing performed a read on the
44
-- second byte of the address rather than a fetch
45
-- so it formed an incorrect address. Now fixed.
46
--
47
-- Version 1.2 - 29 November 2003 John Kent
48
-- LEAX and LEAY affect the Z bit only
49
--      LEAS and LEAU do not affect any condition codes
50
-- added an extra ALU control for LEA.
51
--
52
-- Version 1.3 - 12 December 2003 John Kent
53
-- CWAI did not work, was missed a PUSH_ST on calling
54
-- the ANDCC_STATE. Thanks go to Ghassan Kraidy for
55
-- finding this fault.
56
--
57
-- Version 1.4 - 12 December 2003 John Kent
58
-- Missing cc_ctrl assignment in otherwise case of
59
-- lea_state resulted in cc_ctrl being latched in
60
-- that state.
61
-- The otherwise statement should never be reached,
62
-- and has been fixed simply to resolve synthesis warnings.
63
--
64
-- Version 1.5 - 17 january 2004 John kent
65
-- The clear instruction used "alu_ld8" to control the ALU
66
-- rather than "alu_clr". This mean the Carry was not being
67
-- cleared correctly.
68
--
69
-- Version 1.6 - 24 January 2004 John Kent
70
-- Fixed problems in PSHU instruction
71
--
72
-- Version 1.7 - 25 January 2004 John Kent
73
-- removed redundant "alu_inx" and "alu_dex'
74
-- Removed "test_alu" and "test_cc"
75
-- STD instruction did not set condition codes
76
-- JMP direct was not decoded properly
77
-- CLR direct performed an unwanted read cycle
78
-- Bogus "latch_md" in Page2 indexed addressing
79
--
80
-- Version 1.8 - 27 January 2004 John Kent
81
-- CWAI in decode1_state should increment the PC.
82
-- ABX is supposed to be an unsigned addition.
83
-- Added extra ALU function
84
-- ASR8 slightly changed in the ALU.
85
--
86
--      Version 1.9 - 20 August 2005
87
-- LSR8 is now handled in ASR8 and ROR8 case in the ALU,
88
-- rather than LSR16. There was a problem with single
89
-- operand instructions using the MD register which is
90
-- sign extended on the first 8 bit fetch.
91
--
92
-- Version 1.10 - 13 September 2005
93
-- TFR & EXG instructions did not work for the Condition Code Register
94
-- An extra case has been added to the ALU for the alu_tfr control
95
-- to assign the left ALU input (alu_left) to the condition code
96
-- outputs (cc_out).
97
--
98
-- Version 1.11 - 16 September 2005
99
-- JSR ,X should not predecrement S before calculating the jump address.
100
-- The reason is that JSR [0,S] needs S to point to the top of the stack
101
-- to fetch a valid vector address. The solution is to have the addressing
102
-- mode microcode called before decrementing S and then decrementing S in
103
-- JSR_STATE. JSR_STATE in turn calls PUSH_RETURN_LO_STATE rather than
104
-- PUSH_RETURN_HI_STATE so that both the High & Low halves of the PC are
105
-- pushed on the stack. This adds one extra bus cycle, but resolves the
106
-- addressing conflict. I've also removed the pre-decement S in
107
-- JSR EXTENDED as it also calls JSR_STATE.
108
--
109
-- Version 1.12 - 6th June 2006
110
-- 6809 Programming reference manual says V is not affected by ASR, LSR and ROR
111
-- This is different to the 6800. CLR should reset the V bit.
112
--
113
-- Version 1.13 - 7th July 2006
114
-- Disable NMI on reset until S Stack pointer has been loaded.
115
-- Added nmi_enable signal in sp_reg process and nmi_handler process.
116
--
117
-- Version 1.4 - 11th July 2006
118
-- 1. Added new state to RTI called rti_entire_state.
119
-- This state tests the CC register after it has been loaded
120
-- from the stack. Previously the current CC was tested which
121
-- was incorrect. The Entire Flag should be set before the
122
-- interrupt stacks the CC.
123
-- 2. On bogus Interrupts, int_cc_state went to rti_state,
124
-- which was an enumerated state, but not defined anywhere.
125
-- rti_state has been changed to rti_cc_state so that bogus interrupt
126
-- will perform an RTI after entering that state.
127
-- 3. Sync should generate an interrupt if the interrupt masks
128
-- are cleared. If the interrupt masks are set, then an interrupt
129
-- will cause the the PC to advance to the next instruction.
130
-- Note that I don't wait for an interrupt to be asserted for
131
-- three clock cycles.
132
-- 4. Added new ALU control state "alu_mul". "alu_mul" is used in
133
-- the Multiply instruction replacing "alu_add16". This is similar
134
-- to "alu_add16" except it sets the Carry bit to B7 of the result
135
-- in ACCB, sets the Zero bit if the 16 bit result is zero, but
136
-- does not affect The Half carry (H), Negative (N) or Overflow (V)
137
-- flags. The logic was re-arranged so that it adds md or zero so
138
-- that the Carry condition code is set on zero multiplicands.
139
-- 5. DAA (Decimal Adjust Accumulator) should set the Negative (N)
140
-- and Zero Flags. It will also affect the Overflow (V) flag although
141
-- the operation is undefined. It's anyones guess what DAA does to V.
142
--
143
--
144
-- Version 1.5  Jan 2007 - B. Cuzeau
145
--  * all rising_edge !
146
--  * code style,
147
--  * sensitivity lists
148
--  * cosmetic changes
149
--  * Added PC_OUT for debug purpose
150
--  * if halt <='1' line 9618 fixed
151
 
152
Library IEEE;
153
  use IEEE.std_logic_1164.all;
154
  use IEEE.std_logic_unsigned.all;
155
 
156
entity cpu09 is
157
  port (  clk      : in  std_logic;
158
          rst      : in  std_logic;
159
          rw       : out std_logic;
160
          vma      : out std_logic;
161
          address  : out std_logic_vector(15 downto 0);
162
          data_in  : in  std_logic_vector(7 downto 0);
163
          data_out : out std_logic_vector(7 downto 0);
164
          halt     : in  std_logic;
165
          hold     : in  std_logic;
166
          irq      : in  std_logic;
167
          firq     : in  std_logic;
168
          nmi      : in  std_logic;
169
          pc_out   : out std_logic_vector(15 downto 0)  -- For debug purpose
170
      );
171
end;
172
 
173
architecture CPU_ARCH of cpu09 is
174
 
175
  constant EBIT : integer := 7;
176
  constant FBIT : integer := 6;
177
  constant HBIT : integer := 5;
178
  constant IBIT : integer := 4;
179
  constant NBIT : integer := 3;
180
  constant ZBIT : integer := 2;
181
  constant VBIT : integer := 1;
182
  constant CBIT : integer := 0;
183
 
184
  --
185
  -- Interrupt vector modifiers
186
  --
187
  constant RST_VEC  : std_logic_vector(2 downto 0) := "111";
188
  constant NMI_VEC  : std_logic_vector(2 downto 0) := "110";
189
  constant SWI_VEC  : std_logic_vector(2 downto 0) := "101";
190
  constant IRQ_VEC  : std_logic_vector(2 downto 0) := "100";
191
  constant FIRQ_VEC : std_logic_vector(2 downto 0) := "011";
192
  constant SWI2_VEC : std_logic_vector(2 downto 0) := "010";
193
  constant SWI3_VEC : std_logic_vector(2 downto 0) := "001";
194
  constant RESV_VEC : std_logic_vector(2 downto 0) := "000";
195
 
196
  type state_type is (
197
    -- Start off in Reset
198
    reset_state,
199
    -- Fetch Interrupt Vectors (including reset)
200
    vect_lo_state, vect_hi_state,
201
    -- Fetch Instruction Cycle
202
    fetch_state,
203
    -- Decode Instruction Cycles
204
    decode1_state, decode2_state, decode3_state,
205
    -- Calculate Effective Address
206
    imm16_state,
207
    indexed_state, index8_state, index16_state, index16_2_state,
208
    pcrel8_state, pcrel16_state, pcrel16_2_state,
209
    indexaddr_state, indexaddr2_state,
210
    postincr1_state, postincr2_state,
211
    indirect_state, indirect2_state, indirect3_state,
212
    extended_state,
213
    -- single ops
214
    single_op_read_state,
215
    single_op_exec_state,
216
    single_op_write_state,
217
    -- Dual op states
218
    dual_op_read8_state, dual_op_read16_state, dual_op_read16_2_state,
219
    dual_op_write8_state, dual_op_write16_state,
220
    --
221
    sync_state, halt_state, error_state,
222
    --
223
    andcc_state, orcc_state,
224
    tfr_state, exg_state, exg1_state,
225
    lea_state,
226
    -- Multiplication
227
    mul_state, mulea_state, muld_state,
228
    mul0_state, mul1_state, mul2_state, mul3_state,
229
    mul4_state, mul5_state, mul6_state, mul7_state,
230
    --  Branches
231
    lbranch_state, sbranch_state,
232
    -- Jumps, Subroutine Calls and Returns
233
    jsr_state, jmp_state,
234
    push_return_hi_state, push_return_lo_state,
235
    pull_return_hi_state, pull_return_lo_state,
236
    -- Interrupt cycles
237
    int_decr_state,
238
    int_entire_state,
239
    int_pcl_state, int_pch_state,
240
    int_upl_state, int_uph_state,
241
    int_iyl_state, int_iyh_state,
242
    int_ixl_state, int_ixh_state,
243
    int_cc_state,
244
    int_acca_state, int_accb_state,
245
    int_dp_state,
246
    int_cwai_state, int_mask_state,
247
    -- Return From Interrupt
248
    rti_cc_state, rti_entire_state,
249
    rti_acca_state, rti_accb_state,
250
    rti_dp_state,
251
    rti_ixl_state, rti_ixh_state,
252
    rti_iyl_state, rti_iyh_state,
253
    rti_upl_state, rti_uph_state,
254
    rti_pcl_state, rti_pch_state,
255
    -- Push Registers using SP
256
    pshs_state,
257
    pshs_pcl_state, pshs_pch_state,
258
    pshs_upl_state, pshs_uph_state,
259
    pshs_iyl_state, pshs_iyh_state,
260
    pshs_ixl_state, pshs_ixh_state,
261
    pshs_dp_state,
262
    pshs_acca_state, pshs_accb_state,
263
    pshs_cc_state,
264
    -- Pull Registers using SP
265
    puls_state,
266
    puls_cc_state,
267
    puls_acca_state, puls_accb_state,
268
    puls_dp_state,
269
    puls_ixl_state, puls_ixh_state,
270
    puls_iyl_state, puls_iyh_state,
271
    puls_upl_state, puls_uph_state,
272
    puls_pcl_state, puls_pch_state,
273
    -- Push Registers using UP
274
    pshu_state,
275
    pshu_pcl_state, pshu_pch_state,
276
    pshu_spl_state, pshu_sph_state,
277
    pshu_iyl_state, pshu_iyh_state,
278
    pshu_ixl_state, pshu_ixh_state,
279
    pshu_dp_state,
280
    pshu_acca_state, pshu_accb_state,
281
    pshu_cc_state,
282
    -- Pull Registers using UP
283
    pulu_state,
284
    pulu_cc_state,
285
    pulu_acca_state, pulu_accb_state,
286
    pulu_dp_state,
287
    pulu_ixl_state, pulu_ixh_state,
288
    pulu_iyl_state, pulu_iyh_state,
289
    pulu_spl_state, pulu_sph_state,
290
    pulu_pcl_state, pulu_pch_state);
291
 
292
  type stack_type is array(2 downto 0) of state_type;
293
  type st_type    is (idle_st, push_st, pull_st);
294
  type addr_type  is (idle_ad, fetch_ad, read_ad, write_ad, pushu_ad, pullu_ad, pushs_ad, pulls_ad, int_hi_ad, int_lo_ad);
295
  type dout_type  is (cc_dout, acca_dout, accb_dout, dp_dout,
296
                      ix_lo_dout, ix_hi_dout, iy_lo_dout, iy_hi_dout,
297
                      up_lo_dout, up_hi_dout, sp_lo_dout, sp_hi_dout,
298
                      pc_lo_dout, pc_hi_dout, md_lo_dout, md_hi_dout);
299
  type op_type    is (reset_op, fetch_op, latch_op);
300
  type pre_type   is (reset_pre, fetch_pre, latch_pre);
301
  type cc_type    is (reset_cc, load_cc, pull_cc, latch_cc);
302
  type acca_type  is (reset_acca, load_acca, load_hi_acca, pull_acca, latch_acca);
303
  type accb_type  is (reset_accb, load_accb, pull_accb, latch_accb);
304
  type dp_type    is (reset_dp, load_dp, pull_dp, latch_dp);
305
  type ix_type    is (reset_ix, load_ix, pull_lo_ix, pull_hi_ix, latch_ix);
306
  type iy_type    is (reset_iy, load_iy, pull_lo_iy, pull_hi_iy, latch_iy);
307
  type sp_type    is (reset_sp, latch_sp, load_sp, pull_hi_sp, pull_lo_sp);
308
  type up_type    is (reset_up, latch_up, load_up, pull_hi_up, pull_lo_up);
309
  type pc_type    is (reset_pc, latch_pc, load_pc, pull_lo_pc, pull_hi_pc, incr_pc);
310
  type md_type    is (reset_md, latch_md, load_md, fetch_first_md, fetch_next_md, shiftl_md);
311
  type ea_type    is (reset_ea, latch_ea, load_ea, fetch_first_ea, fetch_next_ea);
312
  type iv_type    is (reset_iv, latch_iv, nmi_iv, irq_iv, firq_iv, swi_iv, swi2_iv, swi3_iv, resv_iv);
313
  type nmi_type   is (reset_nmi, set_nmi, latch_nmi);
314
  type left_type  is (cc_left, acca_left, accb_left, dp_left,
315
                      ix_left, iy_left, up_left, sp_left,
316
                      accd_left, md_left, pc_left, ea_left);
317
  type right_type is (ea_right, zero_right, one_right, two_right,
318
                      acca_right, accb_right, accd_right,
319
                      md_right, md_sign5_right, md_sign8_right);
320
  type alu_type   is (alu_add8, alu_sub8, alu_add16, alu_sub16, alu_adc, alu_sbc,
321
                      alu_and, alu_ora, alu_eor,
322
                      alu_tst, alu_inc, alu_dec, alu_clr, alu_neg, alu_com,
323
                      alu_lsr16, alu_lsl16,
324
                      alu_ror8, alu_rol8, alu_mul,
325
                      alu_asr8, alu_asl8, alu_lsr8,
326
                      alu_andcc, alu_orcc, alu_sex, alu_tfr, alu_abx,
327
                      alu_seif, alu_sei, alu_see, alu_cle,
328
                      alu_ld8, alu_st8, alu_ld16, alu_st16, alu_lea, alu_nop, alu_daa);
329
 
330
  signal op_code      : std_logic_vector(7 downto 0);
331
  signal pre_code     : std_logic_vector(7 downto 0);
332
  signal acca         : std_logic_vector(7 downto 0);
333
  signal accb         : std_logic_vector(7 downto 0);
334
  signal cc           : std_logic_vector(7 downto 0);
335
  signal cc_out       : std_logic_vector(7 downto 0);
336
  signal dp           : std_logic_vector(7 downto 0);
337
  signal xreg         : std_logic_vector(15 downto 0);
338
  signal yreg         : std_logic_vector(15 downto 0);
339
  signal sp           : std_logic_vector(15 downto 0);
340
  signal up           : std_logic_vector(15 downto 0);
341
  signal ea           : std_logic_vector(15 downto 0);
342
  signal pc           : std_logic_vector(15 downto 0);
343
  signal md           : std_logic_vector(15 downto 0);
344
  signal left         : std_logic_vector(15 downto 0);
345
  signal right        : std_logic_vector(15 downto 0);
346
  signal out_alu      : std_logic_vector(15 downto 0);
347
  signal iv           : std_logic_vector(2 downto 0);
348
  signal nmi_req      : std_logic;
349
  signal nmi_ack      : std_logic;
350
  signal nmi_enable   : std_logic;
351
 
352
  signal state        : state_type;
353
  signal next_state   : state_type;
354
  signal saved_state  : state_type;
355
  signal return_state : state_type;
356
  signal state_stack  : stack_type;
357
  signal st_ctrl      : st_type;
358
  signal pc_ctrl      : pc_type;
359
  signal ea_ctrl      : ea_type;
360
  signal op_ctrl      : op_type;
361
  signal pre_ctrl     : pre_type;
362
  signal md_ctrl      : md_type;
363
  signal acca_ctrl    : acca_type;
364
  signal accb_ctrl    : accb_type;
365
  signal ix_ctrl      : ix_type;
366
  signal iy_ctrl      : iy_type;
367
  signal cc_ctrl      : cc_type;
368
  signal dp_ctrl      : dp_type;
369
  signal sp_ctrl      : sp_type;
370
  signal up_ctrl      : up_type;
371
  signal iv_ctrl      : iv_type;
372
  signal left_ctrl    : left_type;
373
  signal right_ctrl   : right_type;
374
  signal alu_ctrl     : alu_type;
375
  signal addr_ctrl    : addr_type;
376
  signal dout_ctrl    : dout_type;
377
  signal nmi_ctrl     : nmi_type;
378
 
379
 
380
------
381
BEGIN
382
------
383
 
384
pc_out <= pc when rising_edge(clk); -- register to avoid timing path issues
385
 
386
----------------------------------
387
--
388
-- State machine stack
389
--
390
----------------------------------
391
  state_stack_proc : process(clk)
392
  begin
393
    if rising_edge(clk) then
394
      if hold = '0' then
395
        case st_ctrl is
396
          when push_st =>
397
            state_stack(0) <= return_state;
398
            state_stack(1) <= state_stack(0);
399
            state_stack(2) <= state_stack(1);
400
          when pull_st =>
401
            state_stack(0) <= state_stack(1);
402
            state_stack(1) <= state_stack(2);
403
            state_stack(2) <= fetch_state;
404
          when others =>  -- including idle_st
405
            null;
406
        end case;
407
      end if;
408
    end if;
409
  end process;
410
 
411
  saved_state <= state_stack(0);
412
 
413
----------------------------------
414
--
415
-- Program Counter Control
416
--
417
----------------------------------
418
 
419
  pc_reg : process(clk)
420
  begin
421
    if rising_edge(clk) then
422
      if hold = '0' then
423
        case pc_ctrl is
424
          when reset_pc =>
425
            pc <=  (others=>'0');
426
          when load_pc =>
427
            pc <= out_alu(15 downto 0);
428
          when pull_lo_pc =>
429
            pc(7 downto 0) <= data_in;
430
          when pull_hi_pc =>
431
            pc(15 downto 8) <= data_in;
432
          when incr_pc =>
433
            pc <= pc + 1;
434
          when others =>   --  including when latch_pc =>
435
            null;
436
        end case;
437
      end if;
438
    end if;
439
  end process;
440
 
441
----------------------------------
442
--
443
-- Effective Address  Control
444
--
445
----------------------------------
446
 
447
  ea_reg : process(clk)
448
  begin
449
 
450
    if rising_edge(clk) then
451
      if hold = '0' then
452
        case ea_ctrl is
453
          when reset_ea =>
454
            ea <=  (others=>'0');
455
          when fetch_first_ea =>
456
            ea(7 downto 0)  <= data_in;
457
            ea(15 downto 8) <= dp;
458
          when fetch_next_ea =>
459
            ea(15 downto 8) <= ea(7 downto 0);
460
            ea(7 downto 0)  <= data_in;
461
          when load_ea =>
462
            ea <= out_alu(15 downto 0);
463
          when others => -- when latch_ea =>
464
            null;
465
        end case;
466
      end if;
467
    end if;
468
  end process;
469
 
470
--------------------------------
471
--
472
-- Accumulator A
473
--
474
--------------------------------
475
  acca_reg : process(clk)
476
  begin
477
    if rising_edge(clk) then
478
      if hold = '0' then
479
        case acca_ctrl is
480
          when reset_acca =>
481
            acca <=  x"00";
482
          when load_acca =>
483
            acca <= out_alu(7 downto 0);
484
          when load_hi_acca =>
485
            acca <= out_alu(15 downto 8);
486
          when pull_acca =>
487
            acca <= data_in;
488
          when others =>  --  when latch_acca =>
489
            null;
490
        end case;
491
      end if;
492
    end if;
493
  end process;
494
 
495
--------------------------------
496
--
497
-- Accumulator B
498
--
499
--------------------------------
500
  accb_reg : process(clk)
501
  begin
502
    if rising_edge(clk) then
503
      if hold = '0' then
504
        case accb_ctrl is
505
          when reset_accb =>
506
            accb <= x"00";
507
          when load_accb =>
508
            accb <= out_alu(7 downto 0);
509
          when pull_accb =>
510
            accb <= data_in;
511
          when others =>  -- when latch_accb =>
512
            null;
513
        end case;
514
      end if;
515
    end if;
516
  end process;
517
 
518
--------------------------------
519
--
520
-- X Index register
521
--
522
--------------------------------
523
  ix_reg : process(clk)
524
  begin
525
    if rising_edge(clk) then
526
      if hold = '0' then
527
        case ix_ctrl is
528
          when reset_ix =>
529
            xreg <= (others=>'0');
530
          when load_ix =>
531
            xreg <= out_alu(15 downto 0);
532
          when pull_hi_ix =>
533
            xreg(15 downto 8) <= data_in;
534
          when pull_lo_ix =>
535
            xreg(7 downto 0) <= data_in;
536
          when others => -- when latch_ix =>
537
            null;
538
        end case;
539
      end if;
540
    end if;
541
  end process;
542
 
543
--------------------------------
544
--
545
-- Y Index register
546
--
547
--------------------------------
548
  iy_reg : process(clk)
549
  begin
550
    if rising_edge(clk) then
551
      if hold = '0' then
552
        case iy_ctrl is
553
          when reset_iy =>
554
            yreg <= (others=>'0');
555
          when load_iy =>
556
            yreg <= out_alu(15 downto 0);
557
          when pull_hi_iy =>
558
            yreg(15 downto 8) <= data_in;
559
          when pull_lo_iy =>
560
            yreg(7 downto 0) <= data_in;
561
          when others =>  -- when latch_iy =>
562
            null;
563
        end case;
564
      end if;
565
    end if;
566
  end process;
567
 
568
--------------------------------
569
--
570
-- S stack pointer
571
--
572
--------------------------------
573
  sp_reg : process(clk)
574
  begin
575
    if rising_edge(clk) then
576
      if hold = '0' then
577
        case sp_ctrl is
578
          when reset_sp =>
579
            sp         <=  (others=>'0');
580
            nmi_enable <= '0';
581
          when load_sp =>
582
            sp         <= out_alu(15 downto 0);
583
            nmi_enable <= '1';
584
          when pull_hi_sp =>
585
            sp(15 downto 8) <= data_in;
586
          when pull_lo_sp =>
587
            sp(7 downto 0) <= data_in;
588
            nmi_enable     <= '1';
589
          when others =>   -- when latch_sp =>
590
            null;
591
        end case;
592
      end if;
593
    end if;
594
  end process;
595
 
596
--------------------------------
597
--
598
-- U stack pointer
599
--
600
--------------------------------
601
  up_reg : process(clk)
602
  begin
603
    if rising_edge(clk) then
604
      if hold = '0' then
605
        case up_ctrl is
606
          when reset_up =>
607
            up <= (others=>'0');
608
          when load_up =>
609
            up <= out_alu(15 downto 0);
610
          when pull_hi_up =>
611
            up(15 downto 8) <= data_in;
612
          when pull_lo_up =>
613
            up(7 downto 0) <= data_in;
614
          when others =>  -- when latch_up =>
615
            null;
616
        end case;
617
      end if;
618
    end if;
619
  end process;
620
 
621
--------------------------------
622
--
623
-- Memory Data
624
--
625
--------------------------------
626
  md_reg : process(clk)
627
  begin
628
    if rising_edge(clk) then
629
      if hold = '0' then
630
        case md_ctrl is
631
          when reset_md =>
632
            md <=  (others=>'0');
633
          when load_md =>
634
            md <= out_alu(15 downto 0);
635
          when fetch_first_md =>        -- sign extend md for branches
636
            md(15 downto 8) <= data_in(7) & data_in(7) & data_in(7) & data_in(7) &
637
                               data_in(7) & data_in(7) & data_in(7) & data_in(7);
638
            md(7 downto 0) <= data_in;
639
          when fetch_next_md =>
640
            md(15 downto 8) <= md(7 downto 0);
641
            md(7 downto 0)  <= data_in;
642
          when shiftl_md =>
643
            md(15 downto 1) <= md(14 downto 0);
644
            md(0)           <= '0';
645
          when others =>   -- when latch_md =>
646
            null;
647
        end case;
648
      end if;
649
    end if;
650
  end process;
651
 
652
 
653
----------------------------------
654
--
655
-- Condition Codes
656
--
657
----------------------------------
658
 
659
  cc_reg : process(clk)
660
  begin
661
    if rising_edge(clk) then
662
      if hold = '0' then
663
        case cc_ctrl is
664
          when reset_cc =>
665
            cc <= "11010000";           -- set EBIT, FBIT & IBIT
666
          when load_cc =>
667
            cc <= cc_out;
668
          when pull_cc =>
669
            cc <= data_in;
670
          when others =>   -- when latch_cc =>
671
            null;
672
        end case;
673
      end if;
674
    end if;
675
  end process;
676
 
677
----------------------------------
678
--
679
-- Direct Page register
680
--
681
----------------------------------
682
 
683
  dp_reg : process(clk)
684
  begin
685
    if rising_edge(clk) then
686
      if hold = '0' then
687
        case dp_ctrl is
688
          when reset_dp =>
689
            dp <=  (others=>'0');
690
          when load_dp =>
691
            dp <= out_alu(7 downto 0);
692
          when pull_dp =>
693
            dp <= data_in;
694
          when others =>   -- when latch_dp =>
695
            null;
696
        end case;
697
      end if;
698
    end if;
699
  end process;
700
 
701
----------------------------------
702
--
703
-- interrupt vector
704
--
705
----------------------------------
706
 
707
  iv_mux : process(clk)
708
  begin
709
    if rising_edge(clk) then
710
      if hold = '0' then
711
        case iv_ctrl is
712
          when reset_iv =>
713
            iv <= RST_VEC;
714
          when nmi_iv =>
715
            iv <= NMI_VEC;
716
          when swi_iv =>
717
            iv <= SWI_VEC;
718
          when irq_iv =>
719
            iv <= IRQ_VEC;
720
          when firq_iv =>
721
            iv <= FIRQ_VEC;
722
          when swi2_iv =>
723
            iv <= SWI2_VEC;
724
          when swi3_iv =>
725
            iv <= SWI3_VEC;
726
          when resv_iv =>
727
            iv <= RESV_VEC;
728
          when others =>
729
            iv <= iv;
730
        end case;
731
      end if;
732
    end if;
733
  end process;
734
 
735
 
736
----------------------------------
737
--
738
-- op code register
739
--
740
----------------------------------
741
 
742
  op_reg : process(clk)
743
  begin
744
    if rising_edge(clk) then
745
      if hold = '0' then
746
        case op_ctrl is
747
          when reset_op =>
748
            op_code <= "00010010";
749
          when fetch_op =>
750
            op_code <= data_in;
751
          when others =>   -- when latch_op =>
752
            null;
753
        end case;
754
      end if;
755
    end if;
756
  end process;
757
 
758
 
759
----------------------------------
760
--
761
-- pre byte op code register
762
--
763
----------------------------------
764
 
765
  pre_reg : process(clk)
766
  begin
767
    if rising_edge(clk) then
768
      if hold = '0' then
769
        case pre_ctrl is
770
          when reset_pre =>
771
            pre_code <= x"00";
772
          when fetch_pre =>
773
            pre_code <= data_in;
774
          when others =>   -- when latch_pre =>
775
            null;
776
        end case;
777
      end if;
778
    end if;
779
  end process;
780
 
781
--------------------------------
782
--
783
-- state machine
784
--
785
--------------------------------
786
 
787
  change_state : process(clk)
788
  begin
789
    if rising_edge(clk) then
790
      if rst = '1' then
791
        state <= reset_state;
792
      else
793
        if hold = '0' then
794
          state <= next_state;
795
        end if;
796
      end if;
797
    end if;
798
  end process;
799
  -- output
800
 
801
------------------------------------
802
--
803
-- Nmi register
804
--
805
------------------------------------
806
 
807
  nmi_reg : process(clk)
808
  begin
809
    if rising_edge(clk) then
810
      if hold = '0' then
811
        case nmi_ctrl is
812
          when set_nmi =>
813
            nmi_ack <= '1';
814
          when reset_nmi =>
815
            nmi_ack <= '0';
816
          when others =>  --  when latch_nmi =>
817
            null;
818
        end case;
819
      end if;
820
    end if;
821
  end process;
822
 
823
------------------------------------
824
--
825
-- Detect Edge of NMI interrupt
826
--
827
------------------------------------
828
 
829
  nmi_handler : process(clk)
830
  begin
831
    if rising_edge(clk) then
832
      if rst = '1' then
833
        nmi_req <= '0';
834
      else
835
        if (nmi = '1') and (nmi_ack = '0') and (nmi_enable = '1') then
836
          nmi_req <= '1';
837
        else
838
          if (nmi = '0') and (nmi_ack = '1') then
839
            nmi_req <= '0';
840
          end if;
841
        end if;
842
      end if;
843
    end if;
844
  end process;
845
 
846
 
847
----------------------------------
848
--
849
-- Address output multiplexer
850
--
851
----------------------------------
852
 
853
  addr_mux : process(addr_ctrl, pc, ea, up, sp, iv)
854
  begin
855
    case addr_ctrl is
856
      when idle_ad =>
857
        address <= "1111111111111111";
858
        vma     <= '0';
859
        rw      <= '1';
860
      when fetch_ad =>
861
        address <= pc;
862
        vma     <= '1';
863
        rw      <= '1';
864
      when read_ad =>
865
        address <= ea;
866
        vma     <= '1';
867
        rw      <= '1';
868
      when write_ad =>
869
        address <= ea;
870
        vma     <= '1';
871
        rw      <= '0';
872
      when pushs_ad =>
873
        address <= sp;
874
        vma     <= '1';
875
        rw      <= '0';
876
      when pulls_ad =>
877
        address <= sp;
878
        vma     <= '1';
879
        rw      <= '1';
880
      when pushu_ad =>
881
        address <= up;
882
        vma     <= '1';
883
        rw      <= '0';
884
      when pullu_ad =>
885
        address <= up;
886
        vma     <= '1';
887
        rw      <= '1';
888
      when int_hi_ad =>
889
        address <= "111111111111" & iv & "0";
890
        vma     <= '1';
891
        rw      <= '1';
892
      when int_lo_ad =>
893
        address <= "111111111111" & iv & "1";
894
        vma     <= '1';
895
        rw      <= '1';
896
      when others =>
897
        address <= "1111111111111111";
898
        vma     <= '0';
899
        rw      <= '1';
900
    end case;
901
  end process;
902
 
903
--------------------------------
904
--
905
-- Data Bus output
906
--
907
--------------------------------
908
  dout_mux : process(dout_ctrl, md, acca, accb, dp, xreg, yreg, sp, up, pc, cc)
909
  begin
910
    case dout_ctrl is
911
      when md_hi_dout =>                -- alu output
912
        data_out <= md(15 downto 8);
913
      when md_lo_dout =>                -- alu output
914
        data_out <= md(7 downto 0);
915
      when acca_dout =>                 -- accumulator a
916
        data_out <= acca;
917
      when accb_dout =>                 -- accumulator b
918
        data_out <= accb;
919
      when ix_lo_dout =>                -- index reg
920
        data_out <= xreg(7 downto 0);
921
      when ix_hi_dout =>                -- index reg
922
        data_out <= xreg(15 downto 8);
923
      when iy_lo_dout =>                -- index reg
924
        data_out <= yreg(7 downto 0);
925
      when iy_hi_dout =>                -- index reg
926
        data_out <= yreg(15 downto 8);
927
      when sp_lo_dout =>                -- s stack pointer
928
        data_out <= sp(7 downto 0);
929
      when sp_hi_dout =>                -- s stack pointer
930
        data_out <= sp(15 downto 8);
931
      when up_lo_dout =>                -- u stack pointer
932
        data_out <= up(7 downto 0);
933
      when up_hi_dout =>                -- u stack pointer
934
        data_out <= up(15 downto 8);
935
      when cc_dout =>                   -- condition code register
936
        data_out <= cc;
937
      when dp_dout =>                   -- direct page register
938
        data_out <= dp;
939
      when pc_lo_dout =>                -- low order pc
940
        data_out <= pc(7 downto 0);
941
      when pc_hi_dout =>                -- high order pc
942
        data_out <= pc(15 downto 8);
943
      when others =>
944
        data_out <= "00000000";
945
    end case;
946
  end process;
947
 
948
----------------------------------
949
--
950
-- Left Mux
951
--
952
----------------------------------
953
 
954
  left_mux : process(left_ctrl, acca, accb, cc, dp, xreg, yreg, up, sp, pc, ea, md)
955
  begin
956
    case left_ctrl is
957
      when cc_left =>
958
        left(15 downto 8) <= "00000000";
959
        left(7 downto 0)  <= cc;
960
      when acca_left =>
961
        left(15 downto 8) <= "00000000";
962
        left(7 downto 0)  <= acca;
963
      when accb_left =>
964
        left(15 downto 8) <= "00000000";
965
        left(7 downto 0)  <= accb;
966
      when dp_left =>
967
        left(15 downto 8) <= "00000000";
968
        left(7 downto 0)  <= dp;
969
      when accd_left =>
970
        left(15 downto 8) <= acca;
971
        left(7 downto 0)  <= accb;
972
      when md_left =>
973
        left <= md;
974
      when ix_left =>
975
        left <= xreg;
976
      when iy_left =>
977
        left <= yreg;
978
      when sp_left =>
979
        left <= sp;
980
      when up_left =>
981
        left <= up;
982
      when pc_left =>
983
        left <= pc;
984
      when others => -- when ea_left =>
985
        left <= ea;
986
    end case;
987
  end process;
988
 
989
----------------------------------
990
--
991
-- Right Mux
992
--
993
----------------------------------
994
 
995
  right_mux : process(right_ctrl, md, acca, accb, ea)
996
  begin
997
    case right_ctrl is
998
      when ea_right =>
999
        right <= ea;
1000
      when zero_right =>
1001
        right <= x"0000"; -- "0000000000000000";
1002
      when one_right =>
1003
        right <= x"0001";
1004
      when two_right =>
1005
        right <= x"0002";
1006
      when acca_right =>
1007
        if acca(7) = '0' then
1008
          right <= x"00" & acca(7 downto 0);
1009
        else
1010
          right <= x"FF" & acca(7 downto 0);
1011
        end if;
1012
      when accb_right =>
1013
        if accb(7) = '0' then
1014
          right <= x"00" & accb(7 downto 0);
1015
        else
1016
          right <= x"FF" & accb(7 downto 0);
1017
        end if;
1018
      when accd_right =>
1019
        right <= acca & accb;
1020
      when md_sign5_right =>
1021
        if md(4) = '0' then
1022
          right <= "00000000000" & md(4 downto 0);
1023
        else
1024
          right <= "11111111111" & md(4 downto 0);
1025
        end if;
1026
      when md_sign8_right =>
1027
        if md(7) = '0' then
1028
          right <= x"00" & md(7 downto 0);
1029
        else
1030
          right <= x"FF" & md(7 downto 0);
1031
        end if;
1032
      when others =>  --  when md_right =>
1033
        right <= md;
1034
    end case;
1035
  end process;
1036
 
1037
----------------------------------
1038
--
1039
-- Arithmetic Logic Unit
1040
--
1041
----------------------------------
1042
 
1043
ALU: process(alu_ctrl, cc, left, right, out_alu, cc_out)
1044
  variable valid_lo, valid_hi : boolean;
1045
  variable carry_in           : std_logic;
1046
  variable daa_reg            : std_logic_vector(7 downto 0);
1047
  begin
1048
 
1049
    case alu_ctrl is
1050
      when alu_adc  | alu_sbc | alu_rol8 | alu_ror8 =>
1051
        carry_in := cc(CBIT);
1052
      when alu_asr8 =>
1053
        carry_in := left(7);
1054
      when others =>
1055
        carry_in := '0';
1056
    end case;
1057
 
1058
    valid_lo := left(3 downto 0) <= 9;
1059
    valid_hi := left(7 downto 4) <= 9;
1060
 
1061
    if (cc(CBIT) = '0') then
1062
      if(cc(HBIT) = '1') then
1063
        if valid_hi then
1064
          daa_reg := "00000110";
1065
        else
1066
          daa_reg := "01100110";
1067
        end if;
1068
      else
1069
        if valid_lo then
1070
          if valid_hi then
1071
            daa_reg := "00000000";
1072
          else
1073
            daa_reg := "01100000";
1074
          end if;
1075
        else
1076
          if(left(7 downto 4) <= 8) then
1077
            daa_reg := "00000110";
1078
          else
1079
            daa_reg := "01100110";
1080
          end if;
1081
        end if;
1082
      end if;
1083
    else
1084
      if (cc(HBIT) = '1')then
1085
        daa_reg := "01100110";
1086
      else
1087
        if valid_lo then
1088
          daa_reg := "01100000";
1089
        else
1090
          daa_reg := "01100110";
1091
        end if;
1092
      end if;
1093
    end if;
1094
 
1095
    case alu_ctrl is
1096
      when alu_add8 | alu_inc |
1097
        alu_add16 | alu_adc | alu_mul =>
1098
        out_alu <= left + right + ("000000000000000" & carry_in);
1099
      when alu_sub8 | alu_dec |
1100
        alu_sub16 | alu_sbc =>
1101
        out_alu <= left - right - ("000000000000000" & carry_in);
1102
      when alu_abx =>
1103
        out_alu <= left + ("00000000" & right(7 downto 0));
1104
      when alu_and =>
1105
        out_alu <= left and right;      -- and/bit
1106
      when alu_ora =>
1107
        out_alu <= left or right;       -- or
1108
      when alu_eor =>
1109
        out_alu <= left xor right;      -- eor/xor
1110
      when alu_lsl16 | alu_asl8 | alu_rol8 =>
1111
        out_alu <= left(14 downto 0) & carry_in;  -- rol8/asl8/lsl16
1112
      when alu_lsr16 =>
1113
        out_alu <= carry_in & left(15 downto 1);  -- lsr16
1114
      when alu_lsr8 | alu_asr8 | alu_ror8 =>
1115
        out_alu <= "00000000" & carry_in & left(7 downto 1);  -- ror8/asr8/lsr8
1116
      when alu_neg =>
1117
        out_alu <= right - left;        -- neg (right=0)
1118
      when alu_com =>
1119
        out_alu <= not left;
1120
      when alu_clr | alu_ld8 | alu_ld16 | alu_lea =>
1121
        out_alu <= right;               -- clr, ld
1122
      when alu_st8 | alu_st16 | alu_andcc | alu_orcc | alu_tfr =>
1123
        out_alu <= left;
1124
      when alu_daa =>
1125
        out_alu <= left + ("00000000" & daa_reg);
1126
      when alu_sex =>
1127
        if left(7) = '0' then
1128
          out_alu <= "00000000" & left(7 downto 0);
1129
        else
1130
          out_alu <= "11111111" & left(7 downto 0);
1131
        end if;
1132
      when others =>
1133
        out_alu <= left;                -- nop
1134
    end case;
1135
 
1136
    --
1137
    -- carry bit
1138
    --
1139
    case alu_ctrl is
1140
      when alu_add8 | alu_adc =>
1141
        cc_out(CBIT) <= (left(7) and right(7)) or
1142
                        (left(7) and not out_alu(7)) or
1143
                        (right(7) and not out_alu(7));
1144
      when alu_sub8 | alu_sbc =>
1145
        cc_out(CBIT) <= ((not left(7)) and right(7)) or
1146
                        ((not left(7)) and out_alu(7)) or
1147
                        (right(7) and out_alu(7));
1148
      when alu_add16 =>
1149
        cc_out(CBIT) <= (left(15) and right(15)) or
1150
                        (left(15) and not out_alu(15)) or
1151
                        (right(15) and not out_alu(15));
1152
      when alu_sub16 =>
1153
        cc_out(CBIT) <= ((not left(15)) and right(15)) or
1154
                        ((not left(15)) and out_alu(15)) or
1155
                        (right(15) and out_alu(15));
1156
      when alu_ror8 | alu_lsr16 | alu_lsr8 | alu_asr8 =>
1157
        cc_out(CBIT) <= left(0);
1158
      when alu_rol8 | alu_asl8 =>
1159
        cc_out(CBIT) <= left(7);
1160
      when alu_lsl16 =>
1161
        cc_out(CBIT) <= left(15);
1162
      when alu_com =>
1163
        cc_out(CBIT) <= '1';
1164
      when alu_neg | alu_clr =>
1165
        cc_out(CBIT) <= out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1166
                        out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0);
1167
      when alu_mul =>
1168
        cc_out(CBIT) <= out_alu(7);
1169
      when alu_daa =>
1170
        if (daa_reg(7 downto 4) = "0110") then
1171
          cc_out(CBIT) <= '1';
1172
        else
1173
          cc_out(CBIT) <= '0';
1174
        end if;
1175
      when alu_andcc =>
1176
        cc_out(CBIT) <= left(CBIT) and cc(CBIT);
1177
      when alu_orcc =>
1178
        cc_out(CBIT) <= left(CBIT) or cc(CBIT);
1179
      when alu_tfr =>
1180
        cc_out(CBIT) <= left(CBIT);
1181
      when others =>
1182
        cc_out(CBIT) <= cc(CBIT);
1183
    end case;
1184
    --
1185
    -- Zero flag
1186
    --
1187
    case alu_ctrl is
1188
      when alu_add8 | alu_sub8 |
1189
        alu_adc | alu_sbc |
1190
        alu_and | alu_ora | alu_eor |
1191
        alu_inc | alu_dec |
1192
        alu_neg | alu_com | alu_clr |
1193
        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1194
        alu_ld8 | alu_st8 | alu_sex | alu_daa =>
1195
        cc_out(ZBIT) <= not(out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1196
                             out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0));
1197
      when alu_add16 | alu_sub16 | alu_mul |
1198
        alu_lsl16 | alu_lsr16 |
1199
        alu_ld16 | alu_st16 | alu_lea =>
1200
        cc_out(ZBIT) <= not(out_alu(15) or out_alu(14) or out_alu(13) or out_alu(12) or
1201
                             out_alu(11) or out_alu(10) or out_alu(9) or out_alu(8) or
1202
                             out_alu(7) or out_alu(6) or out_alu(5) or out_alu(4) or
1203
                             out_alu(3) or out_alu(2) or out_alu(1) or out_alu(0));
1204
      when alu_andcc =>
1205
        cc_out(ZBIT) <= left(ZBIT) and cc(ZBIT);
1206
      when alu_orcc =>
1207
        cc_out(ZBIT) <= left(ZBIT) or cc(ZBIT);
1208
      when alu_tfr =>
1209
        cc_out(ZBIT) <= left(ZBIT);
1210
      when others =>
1211
        cc_out(ZBIT) <= cc(ZBIT);
1212
    end case;
1213
 
1214
    --
1215
    -- negative flag
1216
    --
1217
    case alu_ctrl is
1218
      when alu_add8 | alu_sub8 |
1219
        alu_adc | alu_sbc |
1220
        alu_and | alu_ora | alu_eor |
1221
        alu_rol8 | alu_ror8 | alu_asr8 | alu_asl8 | alu_lsr8 |
1222
        alu_inc | alu_dec | alu_neg | alu_com | alu_clr |
1223
        alu_ld8 | alu_st8 | alu_sex | alu_daa =>
1224
        cc_out(NBIT) <= out_alu(7);
1225
      when alu_add16 | alu_sub16 |
1226
        alu_lsl16 | alu_lsr16 |
1227
        alu_ld16 | alu_st16 =>
1228
        cc_out(NBIT) <= out_alu(15);
1229
      when alu_andcc =>
1230
        cc_out(NBIT) <= left(NBIT) and cc(NBIT);
1231
      when alu_orcc =>
1232
        cc_out(NBIT) <= left(NBIT) or cc(NBIT);
1233
      when alu_tfr =>
1234
        cc_out(NBIT) <= left(NBIT);
1235
      when others =>
1236
        cc_out(NBIT) <= cc(NBIT);
1237
    end case;
1238
 
1239
    --
1240
    -- Interrupt mask flag
1241
    --
1242
    case alu_ctrl is
1243
      when alu_andcc =>
1244
        cc_out(IBIT) <= left(IBIT) and cc(IBIT);
1245
      when alu_orcc =>
1246
        cc_out(IBIT) <= left(IBIT) or cc(IBIT);
1247
      when alu_tfr =>
1248
        cc_out(IBIT) <= left(IBIT);
1249
      when alu_seif | alu_sei =>
1250
        cc_out(IBIT) <= '1';
1251
      when others =>
1252
        cc_out(IBIT) <= cc(IBIT);       -- interrupt mask
1253
    end case;
1254
 
1255
    --
1256
    -- Half Carry flag
1257
    --
1258
    case alu_ctrl is
1259
      when alu_add8 | alu_adc =>
1260
        cc_out(HBIT) <= (left(3) and right(3)) or
1261
                        (right(3) and not out_alu(3)) or
1262
                        (left(3) and not out_alu(3));
1263
      when alu_andcc =>
1264
        cc_out(HBIT) <= left(HBIT) and cc(HBIT);
1265
      when alu_orcc =>
1266
        cc_out(HBIT) <= left(HBIT) or cc(HBIT);
1267
      when alu_tfr =>
1268
        cc_out(HBIT) <= left(HBIT);
1269
      when others =>
1270
        cc_out(HBIT) <= cc(HBIT);
1271
    end case;
1272
 
1273
    --
1274
    -- Overflow flag
1275
    --
1276
    case alu_ctrl is
1277
      when alu_add8 | alu_adc =>
1278
        cc_out(VBIT) <= (left(7) and right(7) and (not out_alu(7))) or
1279
                        ((not left(7)) and (not right(7)) and out_alu(7));
1280
      when alu_sub8 | alu_sbc =>
1281
        cc_out(VBIT) <= (left(7) and (not right(7)) and (not out_alu(7))) or
1282
                        ((not left(7)) and right(7) and out_alu(7));
1283
      when alu_add16 =>
1284
        cc_out(VBIT) <= (left(15) and right(15) and (not out_alu(15))) or
1285
                        ((not left(15)) and (not right(15)) and out_alu(15));
1286
      when alu_sub16 =>
1287
        cc_out(VBIT) <= (left(15) and (not right(15)) and (not out_alu(15))) or
1288
                        ((not left(15)) and right(15) and out_alu(15));
1289
      when alu_inc =>
1290
        cc_out(VBIT) <= ((not left(7)) and left(6) and left(5) and left(4) and
1291
                         left(3) and left(2) and left(1) and left(0));
1292
      when alu_dec | alu_neg =>
1293
        cc_out(VBIT) <= (left(7) and (not left(6)) and (not left(5)) and (not left(4)) and
1294
                         (not left(3)) and (not left(2)) and (not left(1)) and (not left(0)));
1295
-- 6809 Programming reference manual says
1296
-- V not affected by ASR, LSR and ROR
1297
-- This is different to the 6800
1298
-- John Kent 6th June 2006
1299
--       when alu_asr8 =>
1300
--         cc_out(VBIT) <= left(0) xor left(7);
1301
--       when alu_lsr8 | alu_lsr16 =>
1302
--         cc_out(VBIT) <= left(0);
1303
--       when alu_ror8 =>
1304
--      cc_out(VBIT) <= left(0) xor cc(CBIT);
1305
      when alu_lsl16 =>
1306
        cc_out(VBIT) <= left(15) xor left(14);
1307
      when alu_rol8 | alu_asl8 =>
1308
        cc_out(VBIT) <= left(7) xor left(6);
1309
--
1310
-- 11th July 2006 - John Kent
1311
-- What DAA does with V is anyones guess
1312
-- It is undefined in the 6809 programming manual
1313
--
1314
      when alu_daa =>
1315
        cc_out(VBIT) <= left(7) xor out_alu(7) xor cc(CBIT);
1316
-- CLR resets V Bit
1317
-- John Kent 6th June 2006
1318
      when alu_and | alu_ora | alu_eor | alu_com | alu_clr |
1319
        alu_st8 | alu_st16 | alu_ld8 | alu_ld16 | alu_sex =>
1320
        cc_out(VBIT) <= '0';
1321
      when alu_andcc =>
1322
        cc_out(VBIT) <= left(VBIT) and cc(VBIT);
1323
      when alu_orcc =>
1324
        cc_out(VBIT) <= left(VBIT) or cc(VBIT);
1325
      when alu_tfr =>
1326
        cc_out(VBIT) <= left(VBIT);
1327
      when others =>
1328
        cc_out(VBIT) <= cc(VBIT);
1329
    end case;
1330
 
1331
    case alu_ctrl is
1332
      when alu_andcc =>
1333
        cc_out(FBIT) <= left(FBIT) and cc(FBIT);
1334
      when alu_orcc =>
1335
        cc_out(FBIT) <= left(FBIT) or cc(FBIT);
1336
      when alu_tfr =>
1337
        cc_out(FBIT) <= left(FBIT);
1338
      when alu_seif =>
1339
        cc_out(FBIT) <= '1';
1340
      when others =>
1341
        cc_out(FBIT) <= cc(FBIT);
1342
    end case;
1343
 
1344
    case alu_ctrl is
1345
      when alu_andcc =>
1346
        cc_out(EBIT) <= left(EBIT) and cc(EBIT);
1347
      when alu_orcc =>
1348
        cc_out(EBIT) <= left(EBIT) or cc(EBIT);
1349
      when alu_tfr =>
1350
        cc_out(EBIT) <= left(EBIT);
1351
      when alu_see =>
1352
        cc_out(EBIT) <= '1';
1353
      when alu_cle =>
1354
        cc_out(EBIT) <= '0';
1355
      when others =>
1356
        cc_out(EBIT) <= cc(EBIT);
1357
    end case;
1358
  end process;
1359
 
1360
------------------------------------
1361
--
1362
-- state sequencer
1363
--
1364
------------------------------------
1365
  process(state, saved_state,
1366
           op_code, pre_code,
1367
           cc, ea, md, iv,
1368
           irq, firq, nmi_req, nmi_ack, halt)
1369
    variable cond_true : boolean;  -- variable used to evaluate coditional branches
1370
  begin
1371
    case state is
1372
      when reset_state =>               --  released from reset
1373
        -- reset the registers
1374
        op_ctrl      <= reset_op;
1375
        pre_ctrl     <= reset_pre;
1376
        acca_ctrl    <= reset_acca;
1377
        accb_ctrl    <= reset_accb;
1378
        ix_ctrl      <= reset_ix;
1379
        iy_ctrl      <= reset_iy;
1380
        sp_ctrl      <= reset_sp;
1381
        up_ctrl      <= reset_up;
1382
        pc_ctrl      <= reset_pc;
1383
        ea_ctrl      <= reset_ea;
1384
        md_ctrl      <= reset_md;
1385
        iv_ctrl      <= reset_iv;
1386
        nmi_ctrl     <= reset_nmi;
1387
        -- idle the ALU
1388
        left_ctrl    <= pc_left;
1389
        right_ctrl   <= zero_right;
1390
        alu_ctrl     <= alu_nop;
1391
        cc_ctrl      <= reset_cc;
1392
        dp_ctrl      <= reset_dp;
1393
        -- idle the bus
1394
        dout_ctrl    <= md_lo_dout;
1395
        addr_ctrl    <= idle_ad;
1396
        st_ctrl      <= idle_st;
1397
        return_state <= vect_hi_state;
1398
        next_state   <= vect_hi_state;
1399
 
1400
      --
1401
      -- Jump via interrupt vector
1402
      -- iv holds interrupt type
1403
      -- fetch PC hi from vector location
1404
      --
1405
      when vect_hi_state =>
1406
        -- default the registers
1407
        op_ctrl      <= latch_op;
1408
        pre_ctrl     <= latch_pre;
1409
        nmi_ctrl     <= latch_nmi;
1410
        acca_ctrl    <= latch_acca;
1411
        accb_ctrl    <= latch_accb;
1412
        ix_ctrl      <= latch_ix;
1413
        iy_ctrl      <= latch_iy;
1414
        sp_ctrl      <= latch_sp;
1415
        up_ctrl      <= latch_up;
1416
        md_ctrl      <= latch_md;
1417
        ea_ctrl      <= latch_ea;
1418
        iv_ctrl      <= latch_iv;
1419
        -- idle the ALU
1420
        left_ctrl    <= pc_left;
1421
        right_ctrl   <= zero_right;
1422
        alu_ctrl     <= alu_nop;
1423
        cc_ctrl      <= latch_cc;
1424
        dp_ctrl      <= latch_dp;
1425
        -- fetch pc low interrupt vector
1426
        pc_ctrl      <= pull_hi_pc;
1427
        addr_ctrl    <= int_hi_ad;
1428
        dout_ctrl    <= pc_hi_dout;
1429
        st_ctrl      <= idle_st;
1430
        return_state <= vect_lo_state;
1431
        next_state   <= vect_lo_state;
1432
        --
1433
        -- jump via interrupt vector
1434
        -- iv holds vector type
1435
        -- fetch PC lo from vector location
1436
        --
1437
      when vect_lo_state =>
1438
        -- default the registers
1439
        op_ctrl      <= latch_op;
1440
        pre_ctrl     <= latch_pre;
1441
        nmi_ctrl     <= latch_nmi;
1442
        acca_ctrl    <= latch_acca;
1443
        accb_ctrl    <= latch_accb;
1444
        ix_ctrl      <= latch_ix;
1445
        iy_ctrl      <= latch_iy;
1446
        sp_ctrl      <= latch_sp;
1447
        up_ctrl      <= latch_up;
1448
        md_ctrl      <= latch_md;
1449
        ea_ctrl      <= latch_ea;
1450
        iv_ctrl      <= latch_iv;
1451
        -- idle the ALU
1452
        left_ctrl    <= pc_left;
1453
        right_ctrl   <= zero_right;
1454
        alu_ctrl     <= alu_nop;
1455
        cc_ctrl      <= latch_cc;
1456
        dp_ctrl      <= latch_dp;
1457
        -- fetch the vector low byte
1458
        pc_ctrl      <= pull_lo_pc;
1459
        addr_ctrl    <= int_lo_ad;
1460
        dout_ctrl    <= pc_lo_dout;
1461
        st_ctrl      <= idle_st;
1462
        return_state <= fetch_state;
1463
        next_state   <= fetch_state;
1464
        --
1465
        -- Here to fetch an instruction
1466
        -- PC points to opcode
1467
        -- Should service interrupt requests at this point
1468
        -- either from the timer
1469
        -- or from the external input.
1470
        --
1471
      when fetch_state =>
1472
        -- fetch the op code
1473
        op_ctrl   <= fetch_op;
1474
        pre_ctrl  <= fetch_pre;
1475
        ea_ctrl   <= reset_ea;
1476
        md_ctrl   <= latch_md;
1477
        -- Fetch op code
1478
        addr_ctrl <= fetch_ad;
1479
        dout_ctrl <= md_lo_dout;
1480
        dp_ctrl   <= latch_dp;
1481
        --
1482
        case op_code(7 downto 6) is
1483
          when "10" =>                  -- acca
1484
            case op_code(3 downto 0) is
1485
              when "0000" =>            -- suba
1486
                left_ctrl  <= acca_left;
1487
                right_ctrl <= md_right;
1488
                alu_ctrl   <= alu_sub8;
1489
                cc_ctrl    <= load_cc;
1490
                acca_ctrl  <= load_acca;
1491
                accb_ctrl  <= latch_accb;
1492
                ix_ctrl    <= latch_ix;
1493
                iy_ctrl    <= latch_iy;
1494
                up_ctrl    <= latch_up;
1495
                sp_ctrl    <= latch_sp;
1496
              when "0001" =>            -- cmpa
1497
                left_ctrl  <= acca_left;
1498
                right_ctrl <= md_right;
1499
                alu_ctrl   <= alu_sub8;
1500
                cc_ctrl    <= load_cc;
1501
                acca_ctrl  <= latch_acca;
1502
                accb_ctrl  <= latch_accb;
1503
                ix_ctrl    <= latch_ix;
1504
                iy_ctrl    <= latch_iy;
1505
                up_ctrl    <= latch_up;
1506
                sp_ctrl    <= latch_sp;
1507
              when "0010" =>            -- sbca
1508
                left_ctrl  <= acca_left;
1509
                right_ctrl <= md_right;
1510
                alu_ctrl   <= alu_sbc;
1511
                cc_ctrl    <= load_cc;
1512
                acca_ctrl  <= load_acca;
1513
                accb_ctrl  <= latch_accb;
1514
                ix_ctrl    <= latch_ix;
1515
                iy_ctrl    <= latch_iy;
1516
                up_ctrl    <= latch_up;
1517
                sp_ctrl    <= latch_sp;
1518
              when "0011" =>
1519
                case pre_code is
1520
                  when "00010000" =>  -- page 2 -- cmpd
1521
                    left_ctrl  <= accd_left;
1522
                    right_ctrl <= md_right;
1523
                    alu_ctrl   <= alu_sub16;
1524
                    cc_ctrl    <= load_cc;
1525
                    acca_ctrl  <= latch_acca;
1526
                    accb_ctrl  <= latch_accb;
1527
                    ix_ctrl    <= latch_ix;
1528
                    iy_ctrl    <= latch_iy;
1529
                    up_ctrl    <= latch_up;
1530
                    sp_ctrl    <= latch_sp;
1531
                  when "00010001" =>  -- page 3 -- cmpu
1532
                    left_ctrl  <= up_left;
1533
                    right_ctrl <= md_right;
1534
                    alu_ctrl   <= alu_sub16;
1535
                    cc_ctrl    <= load_cc;
1536
                    acca_ctrl  <= latch_acca;
1537
                    accb_ctrl  <= latch_accb;
1538
                    ix_ctrl    <= latch_ix;
1539
                    iy_ctrl    <= latch_iy;
1540
                    up_ctrl    <= latch_up;
1541
                    sp_ctrl    <= latch_sp;
1542
                  when others =>  -- page 1 -- subd
1543
                    left_ctrl  <= accd_left;
1544
                    right_ctrl <= md_right;
1545
                    alu_ctrl   <= alu_sub16;
1546
                    cc_ctrl    <= load_cc;
1547
                    acca_ctrl  <= load_hi_acca;
1548
                    accb_ctrl  <= load_accb;
1549
                    ix_ctrl    <= latch_ix;
1550
                    iy_ctrl    <= latch_iy;
1551
                    up_ctrl    <= latch_up;
1552
                    sp_ctrl    <= latch_sp;
1553
                end case;
1554
              when "0100" =>            -- anda
1555
                left_ctrl  <= acca_left;
1556
                right_ctrl <= md_right;
1557
                alu_ctrl   <= alu_and;
1558
                cc_ctrl    <= load_cc;
1559
                acca_ctrl  <= load_acca;
1560
                accb_ctrl  <= latch_accb;
1561
                ix_ctrl    <= latch_ix;
1562
                iy_ctrl    <= latch_iy;
1563
                up_ctrl    <= latch_up;
1564
                sp_ctrl    <= latch_sp;
1565
              when "0101" =>            -- bita
1566
                left_ctrl  <= acca_left;
1567
                right_ctrl <= md_right;
1568
                alu_ctrl   <= alu_and;
1569
                cc_ctrl    <= load_cc;
1570
                acca_ctrl  <= latch_acca;
1571
                accb_ctrl  <= latch_accb;
1572
                ix_ctrl    <= latch_ix;
1573
                iy_ctrl    <= latch_iy;
1574
                up_ctrl    <= latch_up;
1575
                sp_ctrl    <= latch_sp;
1576
              when "0110" =>            -- ldaa
1577
                left_ctrl  <= acca_left;
1578
                right_ctrl <= md_right;
1579
                alu_ctrl   <= alu_ld8;
1580
                cc_ctrl    <= load_cc;
1581
                acca_ctrl  <= load_acca;
1582
                accb_ctrl  <= latch_accb;
1583
                ix_ctrl    <= latch_ix;
1584
                iy_ctrl    <= latch_iy;
1585
                up_ctrl    <= latch_up;
1586
                sp_ctrl    <= latch_sp;
1587
              when "0111" =>            -- staa
1588
                left_ctrl  <= acca_left;
1589
                right_ctrl <= md_right;
1590
                alu_ctrl   <= alu_st8;
1591
                cc_ctrl    <= load_cc;
1592
                acca_ctrl  <= latch_acca;
1593
                accb_ctrl  <= latch_accb;
1594
                ix_ctrl    <= latch_ix;
1595
                iy_ctrl    <= latch_iy;
1596
                up_ctrl    <= latch_up;
1597
                sp_ctrl    <= latch_sp;
1598
              when "1000" =>            -- eora
1599
                left_ctrl  <= acca_left;
1600
                right_ctrl <= md_right;
1601
                alu_ctrl   <= alu_eor;
1602
                cc_ctrl    <= load_cc;
1603
                acca_ctrl  <= load_acca;
1604
                accb_ctrl  <= latch_accb;
1605
                ix_ctrl    <= latch_ix;
1606
                iy_ctrl    <= latch_iy;
1607
                up_ctrl    <= latch_up;
1608
                sp_ctrl    <= latch_sp;
1609
              when "1001" =>            -- adca
1610
                left_ctrl  <= acca_left;
1611
                right_ctrl <= md_right;
1612
                alu_ctrl   <= alu_adc;
1613
                cc_ctrl    <= load_cc;
1614
                acca_ctrl  <= load_acca;
1615
                accb_ctrl  <= latch_accb;
1616
                ix_ctrl    <= latch_ix;
1617
                iy_ctrl    <= latch_iy;
1618
                up_ctrl    <= latch_up;
1619
                sp_ctrl    <= latch_sp;
1620
              when "1010" =>            -- oraa
1621
                left_ctrl  <= acca_left;
1622
                right_ctrl <= md_right;
1623
                alu_ctrl   <= alu_ora;
1624
                cc_ctrl    <= load_cc;
1625
                acca_ctrl  <= load_acca;
1626
                accb_ctrl  <= latch_accb;
1627
                ix_ctrl    <= latch_ix;
1628
                iy_ctrl    <= latch_iy;
1629
                up_ctrl    <= latch_up;
1630
                sp_ctrl    <= latch_sp;
1631
              when "1011" =>            -- adda
1632
                left_ctrl  <= acca_left;
1633
                right_ctrl <= md_right;
1634
                alu_ctrl   <= alu_add8;
1635
                cc_ctrl    <= load_cc;
1636
                acca_ctrl  <= load_acca;
1637
                accb_ctrl  <= latch_accb;
1638
                ix_ctrl    <= latch_ix;
1639
                iy_ctrl    <= latch_iy;
1640
                up_ctrl    <= latch_up;
1641
                sp_ctrl    <= latch_sp;
1642
              when "1100" =>
1643
                case pre_code is
1644
                  when "00010000" =>  -- page 2 -- cmpy
1645
                    left_ctrl  <= iy_left;
1646
                    right_ctrl <= md_right;
1647
                    alu_ctrl   <= alu_sub16;
1648
                    cc_ctrl    <= load_cc;
1649
                    acca_ctrl  <= latch_acca;
1650
                    accb_ctrl  <= latch_accb;
1651
                    ix_ctrl    <= latch_ix;
1652
                    iy_ctrl    <= latch_iy;
1653
                    up_ctrl    <= latch_up;
1654
                    sp_ctrl    <= latch_sp;
1655
                  when "00010001" =>  -- page 3 -- cmps
1656
                    left_ctrl  <= sp_left;
1657
                    right_ctrl <= md_right;
1658
                    alu_ctrl   <= alu_sub16;
1659
                    cc_ctrl    <= load_cc;
1660
                    acca_ctrl  <= latch_acca;
1661
                    accb_ctrl  <= latch_accb;
1662
                    ix_ctrl    <= latch_ix;
1663
                    iy_ctrl    <= latch_iy;
1664
                    up_ctrl    <= latch_up;
1665
                    sp_ctrl    <= latch_sp;
1666
                  when others =>  -- page 1 -- cmpx
1667
                    left_ctrl  <= ix_left;
1668
                    right_ctrl <= md_right;
1669
                    alu_ctrl   <= alu_sub16;
1670
                    cc_ctrl    <= load_cc;
1671
                    acca_ctrl  <= latch_acca;
1672
                    accb_ctrl  <= latch_accb;
1673
                    ix_ctrl    <= latch_ix;
1674
                    iy_ctrl    <= latch_iy;
1675
                    up_ctrl    <= latch_up;
1676
                    sp_ctrl    <= latch_sp;
1677
                end case;
1678
              when "1101" =>            -- bsr / jsr
1679
                left_ctrl  <= pc_left;
1680
                right_ctrl <= md_right;
1681
                alu_ctrl   <= alu_nop;
1682
                cc_ctrl    <= latch_cc;
1683
                acca_ctrl  <= latch_acca;
1684
                accb_ctrl  <= latch_accb;
1685
                ix_ctrl    <= latch_ix;
1686
                iy_ctrl    <= latch_iy;
1687
                up_ctrl    <= latch_up;
1688
                sp_ctrl    <= latch_sp;
1689
              when "1110" =>            -- ldx
1690
                case pre_code is
1691
                  when "00010000" =>  -- page 2 -- ldy
1692
                    left_ctrl  <= iy_left;
1693
                    right_ctrl <= md_right;
1694
                    alu_ctrl   <= alu_ld16;
1695
                    cc_ctrl    <= load_cc;
1696
                    acca_ctrl  <= latch_acca;
1697
                    accb_ctrl  <= latch_accb;
1698
                    ix_ctrl    <= latch_ix;
1699
                    iy_ctrl    <= load_iy;
1700
                    up_ctrl    <= latch_up;
1701
                    sp_ctrl    <= latch_sp;
1702
                  when others =>  -- page 1 -- ldx
1703
                    left_ctrl  <= ix_left;
1704
                    right_ctrl <= md_right;
1705
                    alu_ctrl   <= alu_ld16;
1706
                    cc_ctrl    <= load_cc;
1707
                    acca_ctrl  <= latch_acca;
1708
                    accb_ctrl  <= latch_accb;
1709
                    ix_ctrl    <= load_ix;
1710
                    iy_ctrl    <= latch_iy;
1711
                    up_ctrl    <= latch_up;
1712
                    sp_ctrl    <= latch_sp;
1713
                end case;
1714
              when "1111" =>            -- stx
1715
                case pre_code is
1716
                  when "00010000" =>  -- page 2 -- sty
1717
                    left_ctrl  <= iy_left;
1718
                    right_ctrl <= md_right;
1719
                    alu_ctrl   <= alu_st16;
1720
                    cc_ctrl    <= load_cc;
1721
                    acca_ctrl  <= latch_acca;
1722
                    accb_ctrl  <= latch_accb;
1723
                    ix_ctrl    <= latch_ix;
1724
                    iy_ctrl    <= latch_iy;
1725
                    up_ctrl    <= latch_up;
1726
                    sp_ctrl    <= latch_sp;
1727
                  when others =>  -- page 1 -- stx
1728
                    left_ctrl  <= ix_left;
1729
                    right_ctrl <= md_right;
1730
                    alu_ctrl   <= alu_st16;
1731
                    cc_ctrl    <= load_cc;
1732
                    acca_ctrl  <= latch_acca;
1733
                    accb_ctrl  <= latch_accb;
1734
                    ix_ctrl    <= latch_ix;
1735
                    iy_ctrl    <= latch_iy;
1736
                    up_ctrl    <= latch_up;
1737
                    sp_ctrl    <= latch_sp;
1738
                end case;
1739
              when others =>
1740
                left_ctrl  <= acca_left;
1741
                right_ctrl <= md_right;
1742
                alu_ctrl   <= alu_nop;
1743
                cc_ctrl    <= latch_cc;
1744
                acca_ctrl  <= latch_acca;
1745
                accb_ctrl  <= latch_accb;
1746
                ix_ctrl    <= latch_ix;
1747
                iy_ctrl    <= latch_iy;
1748
                up_ctrl    <= latch_up;
1749
                sp_ctrl    <= latch_sp;
1750
            end case;
1751
          when "11" =>                  -- accb dual op
1752
            case op_code(3 downto 0) is
1753
              when "0000" =>            -- subb
1754
                left_ctrl  <= accb_left;
1755
                right_ctrl <= md_right;
1756
                alu_ctrl   <= alu_sub8;
1757
                cc_ctrl    <= load_cc;
1758
                acca_ctrl  <= latch_acca;
1759
                accb_ctrl  <= load_accb;
1760
                ix_ctrl    <= latch_ix;
1761
                iy_ctrl    <= latch_iy;
1762
                up_ctrl    <= latch_up;
1763
                sp_ctrl    <= latch_sp;
1764
              when "0001" =>            -- cmpb
1765
                left_ctrl  <= accb_left;
1766
                right_ctrl <= md_right;
1767
                alu_ctrl   <= alu_sub8;
1768
                cc_ctrl    <= load_cc;
1769
                acca_ctrl  <= latch_acca;
1770
                accb_ctrl  <= latch_accb;
1771
                ix_ctrl    <= latch_ix;
1772
                iy_ctrl    <= latch_iy;
1773
                up_ctrl    <= latch_up;
1774
                sp_ctrl    <= latch_sp;
1775
              when "0010" =>            -- sbcb
1776
                left_ctrl  <= accb_left;
1777
                right_ctrl <= md_right;
1778
                alu_ctrl   <= alu_sbc;
1779
                cc_ctrl    <= load_cc;
1780
                acca_ctrl  <= latch_acca;
1781
                accb_ctrl  <= load_accb;
1782
                ix_ctrl    <= latch_ix;
1783
                iy_ctrl    <= latch_iy;
1784
                up_ctrl    <= latch_up;
1785
                sp_ctrl    <= latch_sp;
1786
              when "0011" =>            -- addd
1787
                left_ctrl  <= accd_left;
1788
                right_ctrl <= md_right;
1789
                alu_ctrl   <= alu_add16;
1790
                cc_ctrl    <= load_cc;
1791
                acca_ctrl  <= load_hi_acca;
1792
                accb_ctrl  <= load_accb;
1793
                ix_ctrl    <= latch_ix;
1794
                iy_ctrl    <= latch_iy;
1795
                up_ctrl    <= latch_up;
1796
                sp_ctrl    <= latch_sp;
1797
              when "0100" =>            -- andb
1798
                left_ctrl  <= accb_left;
1799
                right_ctrl <= md_right;
1800
                alu_ctrl   <= alu_and;
1801
                cc_ctrl    <= load_cc;
1802
                acca_ctrl  <= latch_acca;
1803
                accb_ctrl  <= load_accb;
1804
                ix_ctrl    <= latch_ix;
1805
                iy_ctrl    <= latch_iy;
1806
                up_ctrl    <= latch_up;
1807
                sp_ctrl    <= latch_sp;
1808
              when "0101" =>            -- bitb
1809
                left_ctrl  <= accb_left;
1810
                right_ctrl <= md_right;
1811
                alu_ctrl   <= alu_and;
1812
                cc_ctrl    <= load_cc;
1813
                acca_ctrl  <= latch_acca;
1814
                accb_ctrl  <= latch_accb;
1815
                ix_ctrl    <= latch_ix;
1816
                iy_ctrl    <= latch_iy;
1817
                up_ctrl    <= latch_up;
1818
                sp_ctrl    <= latch_sp;
1819
              when "0110" =>            -- ldab
1820
                left_ctrl  <= accb_left;
1821
                right_ctrl <= md_right;
1822
                alu_ctrl   <= alu_ld8;
1823
                cc_ctrl    <= load_cc;
1824
                acca_ctrl  <= latch_acca;
1825
                accb_ctrl  <= load_accb;
1826
                ix_ctrl    <= latch_ix;
1827
                iy_ctrl    <= latch_iy;
1828
                up_ctrl    <= latch_up;
1829
                sp_ctrl    <= latch_sp;
1830
              when "0111" =>            -- stab
1831
                left_ctrl  <= accb_left;
1832
                right_ctrl <= md_right;
1833
                alu_ctrl   <= alu_st8;
1834
                cc_ctrl    <= load_cc;
1835
                acca_ctrl  <= latch_acca;
1836
                accb_ctrl  <= latch_accb;
1837
                ix_ctrl    <= latch_ix;
1838
                iy_ctrl    <= latch_iy;
1839
                up_ctrl    <= latch_up;
1840
                sp_ctrl    <= latch_sp;
1841
              when "1000" =>            -- eorb
1842
                left_ctrl  <= accb_left;
1843
                right_ctrl <= md_right;
1844
                alu_ctrl   <= alu_eor;
1845
                cc_ctrl    <= load_cc;
1846
                acca_ctrl  <= latch_acca;
1847
                accb_ctrl  <= load_accb;
1848
                ix_ctrl    <= latch_ix;
1849
                iy_ctrl    <= latch_iy;
1850
                up_ctrl    <= latch_up;
1851
                sp_ctrl    <= latch_sp;
1852
              when "1001" =>            -- adcb
1853
                left_ctrl  <= accb_left;
1854
                right_ctrl <= md_right;
1855
                alu_ctrl   <= alu_adc;
1856
                cc_ctrl    <= load_cc;
1857
                acca_ctrl  <= latch_acca;
1858
                accb_ctrl  <= load_accb;
1859
                ix_ctrl    <= latch_ix;
1860
                iy_ctrl    <= latch_iy;
1861
                up_ctrl    <= latch_up;
1862
                sp_ctrl    <= latch_sp;
1863
              when "1010" =>            -- orab
1864
                left_ctrl  <= accb_left;
1865
                right_ctrl <= md_right;
1866
                alu_ctrl   <= alu_ora;
1867
                cc_ctrl    <= load_cc;
1868
                acca_ctrl  <= latch_acca;
1869
                accb_ctrl  <= load_accb;
1870
                ix_ctrl    <= latch_ix;
1871
                iy_ctrl    <= latch_iy;
1872
                up_ctrl    <= latch_up;
1873
                sp_ctrl    <= latch_sp;
1874
              when "1011" =>            -- addb
1875
                left_ctrl  <= accb_left;
1876
                right_ctrl <= md_right;
1877
                alu_ctrl   <= alu_add8;
1878
                cc_ctrl    <= load_cc;
1879
                acca_ctrl  <= latch_acca;
1880
                accb_ctrl  <= load_accb;
1881
                ix_ctrl    <= latch_ix;
1882
                iy_ctrl    <= latch_iy;
1883
                up_ctrl    <= latch_up;
1884
                sp_ctrl    <= latch_sp;
1885
              when "1100" =>            -- ldd
1886
                left_ctrl  <= accd_left;
1887
                right_ctrl <= md_right;
1888
                alu_ctrl   <= alu_ld16;
1889
                cc_ctrl    <= load_cc;
1890
                acca_ctrl  <= load_hi_acca;
1891
                accb_ctrl  <= load_accb;
1892
                ix_ctrl    <= latch_ix;
1893
                iy_ctrl    <= latch_iy;
1894
                up_ctrl    <= latch_up;
1895
                sp_ctrl    <= latch_sp;
1896
              when "1101" =>            -- std
1897
                left_ctrl  <= accd_left;
1898
                right_ctrl <= md_right;
1899
                alu_ctrl   <= alu_st16;
1900
                cc_ctrl    <= load_cc;
1901
                acca_ctrl  <= latch_acca;
1902
                accb_ctrl  <= latch_accb;
1903
                ix_ctrl    <= latch_ix;
1904
                iy_ctrl    <= latch_iy;
1905
                up_ctrl    <= latch_up;
1906
                sp_ctrl    <= latch_sp;
1907
              when "1110" =>            -- ldu
1908
                case pre_code is
1909
                  when "00010000" =>  -- page 2 -- lds
1910
                    left_ctrl  <= sp_left;
1911
                    right_ctrl <= md_right;
1912
                    alu_ctrl   <= alu_ld16;
1913
                    cc_ctrl    <= load_cc;
1914
                    acca_ctrl  <= latch_acca;
1915
                    accb_ctrl  <= latch_accb;
1916
                    ix_ctrl    <= latch_ix;
1917
                    iy_ctrl    <= latch_iy;
1918
                    up_ctrl    <= latch_up;
1919
                    sp_ctrl    <= load_sp;
1920
                  when others =>  -- page 1 -- ldu
1921
                    left_ctrl  <= up_left;
1922
                    right_ctrl <= md_right;
1923
                    alu_ctrl   <= alu_ld16;
1924
                    cc_ctrl    <= load_cc;
1925
                    acca_ctrl  <= latch_acca;
1926
                    accb_ctrl  <= latch_accb;
1927
                    ix_ctrl    <= latch_ix;
1928
                    iy_ctrl    <= latch_iy;
1929
                    up_ctrl    <= load_up;
1930
                    sp_ctrl    <= latch_sp;
1931
                end case;
1932
              when "1111" =>
1933
                case pre_code is
1934
                  when "00010000" =>  -- page 2 -- sts
1935
                    left_ctrl  <= sp_left;
1936
                    right_ctrl <= md_right;
1937
                    alu_ctrl   <= alu_st16;
1938
                    cc_ctrl    <= load_cc;
1939
                    acca_ctrl  <= latch_acca;
1940
                    accb_ctrl  <= latch_accb;
1941
                    ix_ctrl    <= latch_ix;
1942
                    iy_ctrl    <= latch_iy;
1943
                    up_ctrl    <= latch_up;
1944
                    sp_ctrl    <= latch_sp;
1945
                  when others =>  -- page 1 -- stu
1946
                    left_ctrl  <= up_left;
1947
                    right_ctrl <= md_right;
1948
                    alu_ctrl   <= alu_st16;
1949
                    cc_ctrl    <= load_cc;
1950
                    acca_ctrl  <= latch_acca;
1951
                    accb_ctrl  <= latch_accb;
1952
                    ix_ctrl    <= latch_ix;
1953
                    iy_ctrl    <= latch_iy;
1954
                    up_ctrl    <= latch_up;
1955
                    sp_ctrl    <= latch_sp;
1956
                end case;
1957
              when others =>
1958
                left_ctrl  <= accb_left;
1959
                right_ctrl <= md_right;
1960
                alu_ctrl   <= alu_nop;
1961
                cc_ctrl    <= latch_cc;
1962
                acca_ctrl  <= latch_acca;
1963
                accb_ctrl  <= latch_accb;
1964
                ix_ctrl    <= latch_ix;
1965
                iy_ctrl    <= latch_iy;
1966
                up_ctrl    <= latch_up;
1967
                sp_ctrl    <= latch_sp;
1968
            end case;
1969
          when others =>
1970
            left_ctrl  <= acca_left;
1971
            right_ctrl <= md_right;
1972
            alu_ctrl   <= alu_nop;
1973
            cc_ctrl    <= latch_cc;
1974
            acca_ctrl  <= latch_acca;
1975
            accb_ctrl  <= latch_accb;
1976
            ix_ctrl    <= latch_ix;
1977
            iy_ctrl    <= latch_iy;
1978
            up_ctrl    <= latch_up;
1979
            sp_ctrl    <= latch_sp;
1980
        end case;
1981
        if halt = '1' then
1982
          iv_ctrl      <= reset_iv;
1983
          pc_ctrl      <= latch_pc;
1984
          nmi_ctrl     <= latch_nmi;
1985
          st_ctrl      <= push_st;
1986
          return_state <= fetch_state;
1987
          next_state   <= halt_state;
1988
          -- service non maskable interrupts
1989
        elsif (nmi_req = '1') and (nmi_ack = '0') then
1990
          iv_ctrl      <= nmi_iv;
1991
          pc_ctrl      <= latch_pc;
1992
          nmi_ctrl     <= set_nmi;
1993
          st_ctrl      <= idle_st;
1994
          return_state <= fetch_state;
1995
          next_state   <= int_decr_state;
1996
          -- service maskable interrupts
1997
        else
1998
          --
1999
          -- nmi request is not cleared until nmi input goes low
2000
                              --
2001
          if(nmi_req = '0') and (nmi_ack = '1') then
2002
            nmi_ctrl <= reset_nmi;
2003
          else
2004
            nmi_ctrl <= latch_nmi;
2005
          end if;
2006
                                        --
2007
                                        -- IRQ is level sensitive
2008
                                        --
2009
          if (irq = '1') and (cc(IBIT) = '0') then
2010
            iv_ctrl      <= irq_iv;
2011
            pc_ctrl      <= latch_pc;
2012
            st_ctrl      <= idle_st;
2013
            return_state <= fetch_state;
2014
            next_state   <= int_decr_state;
2015
          elsif (firq = '1') and (cc(FBIT) = '0') then
2016
            iv_ctrl      <= firq_iv;
2017
            pc_ctrl      <= latch_pc;
2018
            st_ctrl      <= idle_st;
2019
            return_state <= fetch_state;
2020
            next_state   <= int_decr_state;
2021
          else
2022
            -- Advance the PC to fetch next instruction byte
2023
            iv_ctrl      <= reset_iv;   -- default to reset
2024
            pc_ctrl      <= incr_pc;
2025
            st_ctrl      <= idle_st;
2026
            return_state <= fetch_state;
2027
            next_state   <= decode1_state;
2028
          end if;
2029
        end if;
2030
        --
2031
        -- Here to decode instruction
2032
        -- and fetch next byte of intruction
2033
        -- whether it be necessary or not
2034
        --
2035
      when decode1_state =>
2036
        pre_ctrl  <= latch_pre;
2037
        -- fetch first byte of address or immediate data
2038
        ea_ctrl   <= fetch_first_ea;
2039
        md_ctrl   <= fetch_first_md;
2040
        addr_ctrl <= fetch_ad;
2041
        dout_ctrl <= md_lo_dout;
2042
        nmi_ctrl  <= latch_nmi;
2043
        dp_ctrl   <= latch_dp;
2044
        case op_code(7 downto 4) is
2045
          --
2046
          -- direct single op (2 bytes)
2047
          -- 6809 => 6 cycles
2048
          -- cpu09 => 5 cycles
2049
          -- 1 op=(pc) / pc=pc+1
2050
          -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
2051
          -- 3 md_lo=(ea) / pc=pc
2052
          -- 4 alu_left=md / md=alu_out / pc=pc
2053
          -- 5 (ea)=md_lo / pc=pc
2054
          --
2055
          -- Exception is JMP
2056
          -- 6809 => 3 cycles
2057
          -- cpu09 => 3 cycles
2058
          -- 1 op=(pc) / pc=pc+1
2059
          -- 2 ea_hi=dp / ea_lo=(pc) / pc=pc+1
2060
          -- 3 pc=ea
2061
          --
2062
          when "0000" =>
2063
            op_ctrl      <= latch_op;
2064
            acca_ctrl    <= latch_acca;
2065
            accb_ctrl    <= latch_accb;
2066
            ix_ctrl      <= latch_ix;
2067
            iy_ctrl      <= latch_iy;
2068
            sp_ctrl      <= latch_sp;
2069
            up_ctrl      <= latch_up;
2070
            iv_ctrl      <= latch_iv;
2071
                                        -- idle ALU
2072
            left_ctrl    <= pc_left;
2073
            right_ctrl   <= one_right;
2074
            alu_ctrl     <= alu_add16;
2075
            cc_ctrl      <= latch_cc;
2076
                                        -- advance the PC
2077
            pc_ctrl      <= incr_pc;
2078
                                        --
2079
            st_ctrl      <= idle_st;
2080
            return_state <= fetch_state;
2081
            case op_code(3 downto 0) is
2082
              when "1110" =>            -- jmp
2083
                next_state <= jmp_state;
2084
              when "1111" =>            -- clr
2085
                next_state <= single_op_exec_state;
2086
              when others =>
2087
                next_state <= single_op_read_state;
2088
            end case;
2089
 
2090
            -- acca / accb inherent instructions
2091
          when "0001" =>
2092
            accb_ctrl <= latch_accb;
2093
            ix_ctrl   <= latch_ix;
2094
            iy_ctrl   <= latch_iy;
2095
            up_ctrl   <= latch_up;
2096
            iv_ctrl   <= latch_iv;
2097
            case op_code(3 downto 0) is
2098
              --
2099
              -- Page2 pre byte
2100
              -- pre=(pc) / pc=pc+1
2101
              -- op=(pc) / pc=pc+1
2102
              --
2103
              when "0000" =>            -- page2
2104
                op_ctrl      <= fetch_op;
2105
                acca_ctrl    <= latch_acca;
2106
                                        --
2107
                left_ctrl    <= pc_left;
2108
                right_ctrl   <= zero_right;
2109
                alu_ctrl     <= alu_nop;
2110
                cc_ctrl      <= latch_cc;
2111
                sp_ctrl      <= latch_sp;
2112
                                        -- advance pc
2113
                pc_ctrl      <= incr_pc;
2114
                                        --
2115
                st_ctrl      <= idle_st;
2116
                return_state <= fetch_state;
2117
                next_state   <= decode2_state;
2118
 
2119
              --
2120
              -- Page3 pre byte
2121
              -- pre=(pc) / pc=pc+1
2122
              -- op=(pc) / pc=pc+1
2123
              --
2124
              when "0001" =>            -- page3
2125
                op_ctrl      <= fetch_op;
2126
                acca_ctrl    <= latch_acca;
2127
                                        -- idle ALU
2128
                left_ctrl    <= pc_left;
2129
                right_ctrl   <= zero_right;
2130
                alu_ctrl     <= alu_nop;
2131
                cc_ctrl      <= latch_cc;
2132
                sp_ctrl      <= latch_sp;
2133
                                        -- advance pc
2134
                pc_ctrl      <= incr_pc;
2135
                                        -- Next state
2136
                st_ctrl      <= idle_st;
2137
                return_state <= fetch_state;
2138
                next_state   <= decode3_state;
2139
 
2140
              --
2141
              -- nop - No operation ( 1 byte )
2142
              -- 6809 => 2 cycles
2143
              -- cpu09 => 2 cycles
2144
              -- 1 op=(pc) / pc=pc+1
2145
              -- 2 decode
2146
              --
2147
              when "0010" =>            -- nop
2148
                op_ctrl      <= latch_op;
2149
                acca_ctrl    <= latch_acca;
2150
                                        --
2151
                left_ctrl    <= acca_left;
2152
                right_ctrl   <= zero_right;
2153
                alu_ctrl     <= alu_nop;
2154
                cc_ctrl      <= latch_cc;
2155
                sp_ctrl      <= latch_sp;
2156
                                        --
2157
                pc_ctrl      <= latch_pc;
2158
                                        --
2159
                st_ctrl      <= idle_st;
2160
                return_state <= fetch_state;
2161
                next_state   <= fetch_state;
2162
 
2163
              --
2164
              -- sync - halt execution until an interrupt is received
2165
              -- interrupt may be NMI, IRQ or FIRQ
2166
              -- program execution continues if the
2167
              -- interrupt is asserted for 3 clock cycles
2168
              -- note that registers are not pushed onto the stack
2169
              -- CPU09 => Interrupts need only be asserted for one clock cycle
2170
              --
2171
              when "0011" =>            -- sync
2172
                op_ctrl      <= latch_op;
2173
                acca_ctrl    <= latch_acca;
2174
                                        --
2175
                left_ctrl    <= acca_left;
2176
                right_ctrl   <= zero_right;
2177
                alu_ctrl     <= alu_nop;
2178
                cc_ctrl      <= latch_cc;
2179
                sp_ctrl      <= latch_sp;
2180
                                        --
2181
                pc_ctrl      <= latch_pc;
2182
                                        --
2183
                st_ctrl      <= idle_st;
2184
                return_state <= fetch_state;
2185
                next_state   <= sync_state;
2186
 
2187
                                        --
2188
                                        -- lbra -- long branch (3 bytes)
2189
                                        -- 6809 => 5 cycles
2190
                                        -- cpu09 => 4 cycles
2191
                                        -- 1 op=(pc) / pc=pc+1
2192
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
2193
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
2194
                                        -- 4 pc=pc+md
2195
                                        --
2196
              when "0110" =>
2197
                op_ctrl      <= latch_op;
2198
                acca_ctrl    <= latch_acca;
2199
                                        -- idle ALU
2200
                left_ctrl    <= pc_left;
2201
                right_ctrl   <= zero_right;
2202
                alu_ctrl     <= alu_nop;
2203
                cc_ctrl      <= latch_cc;
2204
                sp_ctrl      <= latch_sp;
2205
                                        -- increment the pc
2206
                pc_ctrl      <= incr_pc;
2207
                                        --
2208
                st_ctrl      <= idle_st;
2209
                return_state <= fetch_state;
2210
                next_state   <= lbranch_state;
2211
 
2212
                                        --
2213
                                        -- lbsr - long branch to subroutine (3 bytes)
2214
                                        -- 6809 => 9 cycles
2215
                                        -- cpu09 => 6 cycles
2216
                                        -- 1 op=(pc) /pc=pc+1
2217
                                        -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / sp=sp-1
2218
                                        -- 3 md_hi=md_lo / md_lo=(pc) / pc=pc+1
2219
                                        -- 4 (sp)= pc_lo / sp=sp-1 / pc=pc
2220
                                        -- 5 (sp)=pc_hi / pc=pc
2221
                                        -- 6 pc=pc+md
2222
                                        --
2223
              when "0111" =>
2224
                op_ctrl      <= latch_op;
2225
                acca_ctrl    <= latch_acca;
2226
                                        -- pre decrement sp
2227
                left_ctrl    <= sp_left;
2228
                right_ctrl   <= one_right;
2229
                alu_ctrl     <= alu_sub16;
2230
                cc_ctrl      <= latch_cc;
2231
                sp_ctrl      <= load_sp;
2232
                                        -- increment the pc
2233
                pc_ctrl      <= incr_pc;
2234
                                        --
2235
                st_ctrl      <= idle_st;
2236
                return_state <= fetch_state;
2237
                next_state   <= lbranch_state;
2238
 
2239
              when "1001" =>            -- daa
2240
                op_ctrl      <= latch_op;
2241
                                        --
2242
                left_ctrl    <= acca_left;
2243
                right_ctrl   <= accb_right;
2244
                alu_ctrl     <= alu_daa;
2245
                cc_ctrl      <= load_cc;
2246
                acca_ctrl    <= load_acca;
2247
                sp_ctrl      <= latch_sp;
2248
                                        -- idle pc
2249
                pc_ctrl      <= latch_pc;
2250
                                        --
2251
                st_ctrl      <= idle_st;
2252
                return_state <= fetch_state;
2253
                next_state   <= fetch_state;
2254
 
2255
              when "1010" =>            -- orcc
2256
                op_ctrl      <= latch_op;
2257
                acca_ctrl    <= latch_acca;
2258
                                        -- idle ALU
2259
                left_ctrl    <= pc_left;
2260
                right_ctrl   <= zero_right;
2261
                alu_ctrl     <= alu_nop;
2262
                cc_ctrl      <= latch_cc;
2263
                sp_ctrl      <= latch_sp;
2264
                                        -- increment the pc
2265
                pc_ctrl      <= incr_pc;
2266
                                        -- next state
2267
                st_ctrl      <= push_st;
2268
                return_state <= fetch_state;
2269
                next_state   <= orcc_state;
2270
 
2271
              when "1100" =>            -- andcc
2272
                op_ctrl      <= latch_op;
2273
                acca_ctrl    <= latch_acca;
2274
                                        -- idle ALU
2275
                left_ctrl    <= pc_left;
2276
                right_ctrl   <= zero_right;
2277
                alu_ctrl     <= alu_nop;
2278
                cc_ctrl      <= latch_cc;
2279
                sp_ctrl      <= latch_sp;
2280
                                        -- increment the pc
2281
                pc_ctrl      <= incr_pc;
2282
                                        --
2283
                st_ctrl      <= push_st;
2284
                return_state <= fetch_state;
2285
                next_state   <= andcc_state;
2286
 
2287
              when "1101" =>            -- sex
2288
                op_ctrl      <= latch_op;
2289
                                        -- have sex
2290
                left_ctrl    <= accb_left;
2291
                right_ctrl   <= zero_right;
2292
                alu_ctrl     <= alu_sex;
2293
                cc_ctrl      <= load_cc;
2294
                acca_ctrl    <= load_hi_acca;
2295
                sp_ctrl      <= latch_sp;
2296
                                        -- idle PC
2297
                pc_ctrl      <= latch_pc;
2298
                                        --
2299
                st_ctrl      <= idle_st;
2300
                return_state <= fetch_state;
2301
                next_state   <= fetch_state;
2302
 
2303
              when "1110" =>            -- exg
2304
                op_ctrl      <= latch_op;
2305
                acca_ctrl    <= latch_acca;
2306
                                        -- idle ALU
2307
                left_ctrl    <= pc_left;
2308
                right_ctrl   <= zero_right;
2309
                alu_ctrl     <= alu_nop;
2310
                cc_ctrl      <= latch_cc;
2311
                sp_ctrl      <= latch_sp;
2312
                                        -- increment the pc
2313
                pc_ctrl      <= incr_pc;
2314
                                        --
2315
                st_ctrl      <= idle_st;
2316
                return_state <= fetch_state;
2317
                next_state   <= exg_state;
2318
 
2319
              when "1111" =>            -- tfr
2320
                op_ctrl      <= latch_op;
2321
                acca_ctrl    <= latch_acca;
2322
                                        -- idle ALU
2323
                left_ctrl    <= pc_left;
2324
                right_ctrl   <= zero_right;
2325
                alu_ctrl     <= alu_nop;
2326
                cc_ctrl      <= latch_cc;
2327
                sp_ctrl      <= latch_sp;
2328
                                        -- increment the pc
2329
                pc_ctrl      <= incr_pc;
2330
                                        -- call transfer as a subroutine
2331
                st_ctrl      <= push_st;
2332
                return_state <= fetch_state;
2333
                next_state   <= tfr_state;
2334
 
2335
              when others =>
2336
                op_ctrl      <= latch_op;
2337
                acca_ctrl    <= latch_acca;
2338
                                                     -- idle ALU
2339
                left_ctrl    <= pc_left;
2340
                right_ctrl   <= zero_right;
2341
                alu_ctrl     <= alu_nop;
2342
                cc_ctrl      <= latch_cc;
2343
                sp_ctrl      <= latch_sp;
2344
                                                     -- increment the pc
2345
                pc_ctrl      <= incr_pc;
2346
                                                     --
2347
                st_ctrl      <= idle_st;
2348
                return_state <= fetch_state;
2349
                next_state   <= fetch_state;
2350
            end case;
2351
            --
2352
            -- Short branch conditional
2353
            -- 6809 => always 3 cycles
2354
            -- cpu09 => always = 3 cycles
2355
            -- 1 op=(pc) / pc=pc+1
2356
            -- 2 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1 / test cc
2357
            -- 3 if cc tru pc=pc+md else pc=pc
2358
            --
2359
          when "0010" =>                             -- branch conditional
2360
            op_ctrl      <= latch_op;
2361
            acca_ctrl    <= latch_acca;
2362
            accb_ctrl    <= latch_accb;
2363
            ix_ctrl      <= latch_ix;
2364
            iy_ctrl      <= latch_iy;
2365
            sp_ctrl      <= latch_sp;
2366
            up_ctrl      <= latch_up;
2367
            iv_ctrl      <= latch_iv;
2368
                                                     -- idle ALU
2369
            left_ctrl    <= pc_left;
2370
            right_ctrl   <= one_right;
2371
            alu_ctrl     <= alu_add16;
2372
            cc_ctrl      <= latch_cc;
2373
                                                     -- increment the pc
2374
            pc_ctrl      <= incr_pc;
2375
                                                     --
2376
            st_ctrl      <= idle_st;
2377
            return_state <= fetch_state;
2378
            next_state   <= sbranch_state;
2379
            --
2380
            -- Single byte stack operators
2381
            -- Do not advance PC
2382
            --
2383
          when "0011" =>
2384
            op_ctrl   <= latch_op;
2385
            acca_ctrl <= latch_acca;
2386
            accb_ctrl <= latch_accb;
2387
             --
2388
             -- lea - load effective address (2+ bytes)
2389
             -- 6809 => 4 cycles + addressing mode
2390
             -- cpu09 => 4 cycles + addressing mode
2391
             -- 1 op=(pc) / pc=pc+1
2392
             -- 2 md_lo=(pc) / pc=pc+1
2393
             -- 3 calculate ea
2394
             -- 4 ix/iy/sp/up = ea
2395
             --
2396
            case op_code(3 downto 0) is
2397
              when     "0000" |   -- leax
2398
                       "0001" |   -- leay
2399
                       "0010" |   -- leas
2400
                       "0011" =>  -- leau
2401
                left_ctrl    <= pc_left;
2402
                right_ctrl   <= one_right;
2403
                alu_ctrl     <= alu_add16;
2404
                cc_ctrl      <= latch_cc;
2405
                                                     -- advance PC
2406
                pc_ctrl      <= incr_pc;
2407
                                                     --
2408
                ix_ctrl      <= latch_ix;
2409
                iy_ctrl      <= latch_iy;
2410
                sp_ctrl      <= latch_sp;
2411
                up_ctrl      <= latch_up;
2412
                iv_ctrl      <= latch_iv;
2413
                                                     --
2414
                st_ctrl      <= push_st;
2415
                return_state <= lea_state;
2416
                next_state   <= indexed_state;
2417
 
2418
              --
2419
              -- pshs - push registers onto sp stack
2420
              -- 6809 => 5 cycles + registers
2421
              -- cpu09 => 3 cycles + registers
2422
              --  1 op=(pc) / pc=pc+1
2423
              --  2 ea_lo=(pc) / pc=pc+1
2424
              --  3 if ea(7 downto 0) != "00000000" then sp=sp-1
2425
              --  4 if ea(7) = 1 (sp)=pcl, sp=sp-1
2426
              --  5 if ea(7) = 1 (sp)=pch
2427
              --    if ea(6 downto 0) != "0000000" then sp=sp-1
2428
              --  6 if ea(6) = 1 (sp)=upl, sp=sp-1
2429
              --  7 if ea(6) = 1 (sp)=uph
2430
              --    if ea(5 downto 0) != "000000" then sp=sp-1
2431
              --  8 if ea(5) = 1 (sp)=iyl, sp=sp-1
2432
              --  9 if ea(5) = 1 (sp)=iyh
2433
              --    if ea(4 downto 0) != "00000" then sp=sp-1
2434
              -- 10 if ea(4) = 1 (sp)=ixl, sp=sp-1
2435
              -- 11 if ea(4) = 1 (sp)=ixh
2436
              --    if ea(3 downto 0) != "0000" then sp=sp-1
2437
              -- 12 if ea(3) = 1 (sp)=dp
2438
              --    if ea(2 downto 0) != "000" then sp=sp-1
2439
              -- 13 if ea(2) = 1 (sp)=accb
2440
              --    if ea(1 downto 0) != "00" then sp=sp-1
2441
              -- 14 if ea(1) = 1 (sp)=acca
2442
              --    if ea(0 downto 0) != "0" then sp=sp-1
2443
              -- 15 if ea(0) = 1 (sp)=cc
2444
              --
2445
              when "0100" =>            -- pshs
2446
                                        --
2447
                left_ctrl    <= sp_left;
2448
                right_ctrl   <= one_right;
2449
                alu_ctrl     <= alu_nop;
2450
                cc_ctrl      <= latch_cc;
2451
                                        -- advance PC
2452
                pc_ctrl      <= incr_pc;
2453
                                        --
2454
                ix_ctrl      <= latch_ix;
2455
                iy_ctrl      <= latch_iy;
2456
                sp_ctrl      <= latch_sp;
2457
                up_ctrl      <= latch_up;
2458
                iv_ctrl      <= latch_iv;
2459
                                        --
2460
                st_ctrl      <= idle_st;
2461
                return_state <= fetch_state;
2462
                next_state   <= pshs_state;
2463
 
2464
              --
2465
              -- puls - pull registers of sp stack
2466
              -- 6809 => 5 cycles + registers
2467
              -- cpu09 => 3 cycles + registers
2468
              --
2469
              when "0101" =>            -- puls
2470
                left_ctrl    <= pc_left;
2471
                right_ctrl   <= one_right;
2472
                alu_ctrl     <= alu_add16;
2473
                cc_ctrl      <= latch_cc;
2474
                                        -- advance PC
2475
                pc_ctrl      <= incr_pc;
2476
                                        --
2477
                ix_ctrl      <= latch_ix;
2478
                iy_ctrl      <= latch_iy;
2479
                sp_ctrl      <= latch_sp;
2480
                up_ctrl      <= latch_up;
2481
                iv_ctrl      <= latch_iv;
2482
                                        --
2483
                st_ctrl      <= idle_st;
2484
                return_state <= fetch_state;
2485
                next_state   <= puls_state;
2486
 
2487
              --
2488
              -- pshu - push registers onto up stack
2489
              -- 6809 => 5 cycles + registers
2490
              -- cpu09 => 3 cycles + registers
2491
              --
2492
              when "0110" =>            -- pshu
2493
                                        -- idle UP
2494
                left_ctrl    <= up_left;
2495
                right_ctrl   <= one_right;
2496
                alu_ctrl     <= alu_nop;
2497
                cc_ctrl      <= latch_cc;
2498
                                        -- advance PC
2499
                pc_ctrl      <= incr_pc;
2500
                                        --
2501
                ix_ctrl      <= latch_ix;
2502
                iy_ctrl      <= latch_iy;
2503
                sp_ctrl      <= latch_sp;
2504
                up_ctrl      <= latch_up;
2505
                iv_ctrl      <= latch_iv;
2506
                                        --
2507
                st_ctrl      <= idle_st;
2508
                return_state <= fetch_state;
2509
                next_state   <= pshu_state;
2510
 
2511
              --
2512
              -- pulu - pull registers of up stack
2513
              -- 6809 => 5 cycles + registers
2514
              -- cpu09 => 3 cycles + registers
2515
              --
2516
              when "0111" =>     -- pulu
2517
                left_ctrl    <= pc_left;
2518
                right_ctrl   <= one_right;
2519
                alu_ctrl     <= alu_add16;
2520
                cc_ctrl      <= latch_cc;
2521
                                        -- advance PC
2522
                pc_ctrl      <= incr_pc;
2523
                                        --
2524
                ix_ctrl      <= latch_ix;
2525
                iy_ctrl      <= latch_iy;
2526
                sp_ctrl      <= latch_sp;
2527
                up_ctrl      <= latch_up;
2528
                iv_ctrl      <= latch_iv;
2529
                                        --
2530
                st_ctrl      <= idle_st;
2531
                return_state <= fetch_state;
2532
                next_state   <= pulu_state;
2533
 
2534
              --
2535
              -- rts - return from subroutine
2536
              -- 6809 => 5 cycles
2537
              -- cpu09 => 4 cycles
2538
              -- 1 op=(pc) / pc=pc+1
2539
              -- 2 decode op
2540
              -- 3 pc_hi = (sp) / sp=sp+1
2541
              -- 4 pc_lo = (sp) / sp=sp+1
2542
              --
2543
              when "1001" =>
2544
                left_ctrl    <= sp_left;
2545
                right_ctrl   <= zero_right;
2546
                alu_ctrl     <= alu_nop;
2547
                cc_ctrl      <= latch_cc;
2548
                                        -- idle PC
2549
                pc_ctrl      <= latch_pc;
2550
                                        --
2551
                ix_ctrl      <= latch_ix;
2552
                iy_ctrl      <= latch_iy;
2553
                sp_ctrl      <= latch_sp;
2554
                up_ctrl      <= latch_up;
2555
                iv_ctrl      <= latch_iv;
2556
                                        --
2557
                st_ctrl      <= push_st;
2558
                return_state <= fetch_state;
2559
                next_state   <= pull_return_hi_state;
2560
 
2561
              --
2562
              -- add accb to index register
2563
              -- *** Note: this is an unsigned addition.
2564
              --           does not affect any condition codes
2565
              -- 6809 => 3 cycles
2566
              -- cpu09 => 2 cycles
2567
              -- 1 op=(pc) / pc=pc+1
2568
              -- 2 alu_left=ix / alu_right=accb / ix=alu_out / pc=pc
2569
              --
2570
              when "1010" =>            -- abx
2571
                left_ctrl    <= ix_left;
2572
                right_ctrl   <= accb_right;
2573
                alu_ctrl     <= alu_abx;
2574
                cc_ctrl      <= latch_cc;
2575
                ix_ctrl      <= load_ix;
2576
                                        --
2577
                pc_ctrl      <= latch_pc;
2578
                iy_ctrl      <= latch_iy;
2579
                sp_ctrl      <= latch_sp;
2580
                up_ctrl      <= latch_up;
2581
                iv_ctrl      <= latch_iv;
2582
                                        --
2583
                st_ctrl      <= idle_st;
2584
                return_state <= fetch_state;
2585
                next_state   <= fetch_state;
2586
 
2587
              when "1011" =>            -- rti
2588
                                        -- idle ALU
2589
                left_ctrl    <= sp_left;
2590
                right_ctrl   <= zero_right;
2591
                alu_ctrl     <= alu_nop;
2592
                cc_ctrl      <= latch_cc;
2593
                                        --
2594
                pc_ctrl      <= latch_pc;
2595
                ix_ctrl      <= latch_ix;
2596
                iy_ctrl      <= latch_iy;
2597
                sp_ctrl      <= latch_sp;
2598
                up_ctrl      <= latch_up;
2599
                iv_ctrl      <= latch_iv;
2600
                                        --
2601
                st_ctrl      <= idle_st;
2602
                return_state <= fetch_state;
2603
                next_state   <= rti_cc_state;
2604
 
2605
              when "1100" =>                       -- cwai #$<cc_mask>
2606
                                                   -- pre decrement sp
2607
                left_ctrl    <= sp_left;
2608
                right_ctrl   <= one_right;
2609
                alu_ctrl     <= alu_sub16;
2610
                cc_ctrl      <= latch_cc;
2611
                sp_ctrl      <= load_sp;
2612
                                                   --
2613
                pc_ctrl      <= incr_pc;
2614
                ix_ctrl      <= latch_ix;
2615
                iy_ctrl      <= latch_iy;
2616
                up_ctrl      <= latch_up;
2617
                iv_ctrl      <= latch_iv;
2618
                                                   --
2619
                st_ctrl      <= push_st;
2620
                return_state <= int_entire_state;  -- set entire flag
2621
                next_state   <= andcc_state;
2622
 
2623
              when "1101" =>            -- mul
2624
                left_ctrl    <= acca_left;
2625
                right_ctrl   <= zero_right;
2626
                alu_ctrl     <= alu_nop;
2627
                cc_ctrl      <= latch_cc;
2628
                                        --
2629
                pc_ctrl      <= latch_pc;
2630
                ix_ctrl      <= latch_ix;
2631
                iy_ctrl      <= latch_iy;
2632
                sp_ctrl      <= latch_sp;
2633
                up_ctrl      <= latch_up;
2634
                iv_ctrl      <= latch_iv;
2635
                                        --
2636
                st_ctrl      <= idle_st;
2637
                return_state <= fetch_state;
2638
                next_state   <= mul_state;
2639
 
2640
              when "1111" =>            -- swi
2641
                                        -- predecrement SP
2642
                left_ctrl    <= sp_left;
2643
                right_ctrl   <= one_right;
2644
                alu_ctrl     <= alu_sub16;
2645
                cc_ctrl      <= latch_cc;
2646
                sp_ctrl      <= load_sp;
2647
                                        --
2648
                pc_ctrl      <= latch_pc;
2649
                ix_ctrl      <= latch_ix;
2650
                iy_ctrl      <= latch_iy;
2651
                up_ctrl      <= latch_up;
2652
                iv_ctrl      <= swi_iv;
2653
                                        --
2654
                st_ctrl      <= idle_st;
2655
                return_state <= fetch_state;
2656
                next_state   <= int_entire_state;
2657
 
2658
              when others =>
2659
                                        -- idle ALU
2660
                left_ctrl    <= pc_left;
2661
                right_ctrl   <= zero_right;
2662
                alu_ctrl     <= alu_nop;
2663
                cc_ctrl      <= latch_cc;
2664
                                        -- idle PC
2665
                pc_ctrl      <= latch_pc;
2666
                                        --
2667
                ix_ctrl      <= latch_ix;
2668
                iy_ctrl      <= latch_iy;
2669
                sp_ctrl      <= latch_sp;
2670
                up_ctrl      <= latch_up;
2671
                iv_ctrl      <= latch_iv;
2672
                                        --
2673
                st_ctrl      <= idle_st;
2674
                return_state <= fetch_state;
2675
                next_state   <= fetch_state;
2676
 
2677
            end case;
2678
          --
2679
          -- Accumulator A Single operand
2680
          -- source = acca, dest = acca
2681
          -- Do not advance PC
2682
          -- Typically 2 cycles 1 bytes
2683
          -- 1 opcode fetch
2684
          -- 2 post byte fetch / instruction decode
2685
          -- Note that there is no post byte
2686
          -- so do not advance PC in decode cycle
2687
          -- Re-run opcode fetch cycle after decode
2688
          --
2689
          when "0100" =>                -- acca single op
2690
            op_ctrl   <= latch_op;
2691
            accb_ctrl <= latch_accb;
2692
            pc_ctrl   <= latch_pc;
2693
            ix_ctrl   <= latch_ix;
2694
            iy_ctrl   <= latch_iy;
2695
            up_ctrl   <= latch_up;
2696
            sp_ctrl   <= latch_sp;
2697
            iv_ctrl   <= latch_iv;
2698
            left_ctrl <= acca_left;
2699
            case op_code(3 downto 0) is
2700
              when "0000" =>            -- neg
2701
                right_ctrl <= zero_right;
2702
                alu_ctrl   <= alu_neg;
2703
                acca_ctrl  <= load_acca;
2704
                cc_ctrl    <= load_cc;
2705
              when "0011" =>            -- com
2706
                right_ctrl <= zero_right;
2707
                alu_ctrl   <= alu_com;
2708
                acca_ctrl  <= load_acca;
2709
                cc_ctrl    <= load_cc;
2710
              when "0100" =>            -- lsr
2711
                right_ctrl <= zero_right;
2712
                alu_ctrl   <= alu_lsr8;
2713
                acca_ctrl  <= load_acca;
2714
                cc_ctrl    <= load_cc;
2715
              when "0110" =>            -- ror
2716
                right_ctrl <= zero_right;
2717
                alu_ctrl   <= alu_ror8;
2718
                acca_ctrl  <= load_acca;
2719
                cc_ctrl    <= load_cc;
2720
              when "0111" =>            -- asr
2721
                right_ctrl <= zero_right;
2722
                alu_ctrl   <= alu_asr8;
2723
                acca_ctrl  <= load_acca;
2724
                cc_ctrl    <= load_cc;
2725
              when "1000" =>            -- asl
2726
                right_ctrl <= zero_right;
2727
                alu_ctrl   <= alu_asl8;
2728
                acca_ctrl  <= load_acca;
2729
                cc_ctrl    <= load_cc;
2730
              when "1001" =>            -- rol
2731
                right_ctrl <= zero_right;
2732
                alu_ctrl   <= alu_rol8;
2733
                acca_ctrl  <= load_acca;
2734
                cc_ctrl    <= load_cc;
2735
              when "1010" =>            -- dec
2736
                right_ctrl <= one_right;
2737
                alu_ctrl   <= alu_dec;
2738
                acca_ctrl  <= load_acca;
2739
                cc_ctrl    <= load_cc;
2740
              when "1011" =>            -- undefined
2741
                right_ctrl <= zero_right;
2742
                alu_ctrl   <= alu_nop;
2743
                acca_ctrl  <= latch_acca;
2744
                cc_ctrl    <= latch_cc;
2745
              when "1100" =>            -- inc
2746
                right_ctrl <= one_right;
2747
                alu_ctrl   <= alu_inc;
2748
                acca_ctrl  <= load_acca;
2749
                cc_ctrl    <= load_cc;
2750
              when "1101" =>            -- tst
2751
                right_ctrl <= zero_right;
2752
                alu_ctrl   <= alu_st8;
2753
                acca_ctrl  <= latch_acca;
2754
                cc_ctrl    <= load_cc;
2755
              when "1110" =>            -- jmp (not defined)
2756
                right_ctrl <= zero_right;
2757
                alu_ctrl   <= alu_nop;
2758
                acca_ctrl  <= latch_acca;
2759
                cc_ctrl    <= latch_cc;
2760
              when "1111" =>            -- clr
2761
                right_ctrl <= zero_right;
2762
                alu_ctrl   <= alu_clr;
2763
                acca_ctrl  <= load_acca;
2764
                cc_ctrl    <= load_cc;
2765
              when others =>
2766
                right_ctrl <= zero_right;
2767
                alu_ctrl   <= alu_nop;
2768
                acca_ctrl  <= latch_acca;
2769
                cc_ctrl    <= latch_cc;
2770
            end case;
2771
            st_ctrl      <= idle_st;
2772
            return_state <= fetch_state;
2773
            next_state   <= fetch_state;
2774
          --
2775
          -- Single Operand accb
2776
          -- source = accb, dest = accb
2777
          -- Typically 2 cycles 1 bytes
2778
          -- 1 opcode fetch
2779
          -- 2 post byte fetch / instruction decode
2780
          -- Note that there is no post byte
2781
          -- so do not advance PC in decode cycle
2782
          -- Re-run opcode fetch cycle after decode
2783
          --
2784
          when "0101" =>
2785
            op_ctrl   <= latch_op;
2786
            acca_ctrl <= latch_acca;
2787
            pc_ctrl   <= latch_pc;
2788
            ix_ctrl   <= latch_ix;
2789
            iy_ctrl   <= latch_iy;
2790
            up_ctrl   <= latch_up;
2791
            sp_ctrl   <= latch_sp;
2792
            iv_ctrl   <= latch_iv;
2793
            left_ctrl <= accb_left;
2794
            case op_code(3 downto 0) is
2795
              when "0000" =>            -- neg
2796
                right_ctrl <= zero_right;
2797
                alu_ctrl   <= alu_neg;
2798
                accb_ctrl  <= load_accb;
2799
                cc_ctrl    <= load_cc;
2800
              when "0011" =>            -- com
2801
                right_ctrl <= zero_right;
2802
                alu_ctrl   <= alu_com;
2803
                accb_ctrl  <= load_accb;
2804
                cc_ctrl    <= load_cc;
2805
              when "0100" =>            -- lsr
2806
                right_ctrl <= zero_right;
2807
                alu_ctrl   <= alu_lsr8;
2808
                accb_ctrl  <= load_accb;
2809
                cc_ctrl    <= load_cc;
2810
              when "0110" =>            -- ror
2811
                right_ctrl <= zero_right;
2812
                alu_ctrl   <= alu_ror8;
2813
                accb_ctrl  <= load_accb;
2814
                cc_ctrl    <= load_cc;
2815
              when "0111" =>            -- asr
2816
                right_ctrl <= zero_right;
2817
                alu_ctrl   <= alu_asr8;
2818
                accb_ctrl  <= load_accb;
2819
                cc_ctrl    <= load_cc;
2820
              when "1000" =>            -- asl
2821
                right_ctrl <= zero_right;
2822
                alu_ctrl   <= alu_asl8;
2823
                accb_ctrl  <= load_accb;
2824
                cc_ctrl    <= load_cc;
2825
              when "1001" =>            -- rol
2826
                right_ctrl <= zero_right;
2827
                alu_ctrl   <= alu_rol8;
2828
                accb_ctrl  <= load_accb;
2829
                cc_ctrl    <= load_cc;
2830
              when "1010" =>            -- dec
2831
                right_ctrl <= one_right;
2832
                alu_ctrl   <= alu_dec;
2833
                accb_ctrl  <= load_accb;
2834
                cc_ctrl    <= load_cc;
2835
              when "1011" =>            -- undefined
2836
                right_ctrl <= zero_right;
2837
                alu_ctrl   <= alu_nop;
2838
                accb_ctrl  <= latch_accb;
2839
                cc_ctrl    <= latch_cc;
2840
              when "1100" =>            -- inc
2841
                right_ctrl <= one_right;
2842
                alu_ctrl   <= alu_inc;
2843
                accb_ctrl  <= load_accb;
2844
                cc_ctrl    <= load_cc;
2845
              when "1101" =>            -- tst
2846
                right_ctrl <= zero_right;
2847
                alu_ctrl   <= alu_st8;
2848
                accb_ctrl  <= latch_accb;
2849
                cc_ctrl    <= load_cc;
2850
              when "1110" =>            -- jmp (undefined)
2851
                right_ctrl <= zero_right;
2852
                alu_ctrl   <= alu_nop;
2853
                accb_ctrl  <= latch_accb;
2854
                cc_ctrl    <= latch_cc;
2855
              when "1111" =>            -- clr
2856
                right_ctrl <= zero_right;
2857
                alu_ctrl   <= alu_clr;
2858
                accb_ctrl  <= load_accb;
2859
                cc_ctrl    <= load_cc;
2860
              when others =>
2861
                right_ctrl <= zero_right;
2862
                alu_ctrl   <= alu_nop;
2863
                accb_ctrl  <= latch_accb;
2864
                cc_ctrl    <= latch_cc;
2865
            end case;
2866
            st_ctrl      <= idle_st;
2867
            return_state <= fetch_state;
2868
            next_state   <= fetch_state;
2869
          --
2870
          -- Single operand indexed
2871
          -- Two byte instruction so advance PC
2872
          -- EA should hold index offset
2873
          --
2874
          when "0110" =>                -- indexed single op
2875
            op_ctrl    <= latch_op;
2876
            acca_ctrl  <= latch_acca;
2877
            accb_ctrl  <= latch_accb;
2878
            ix_ctrl    <= latch_ix;
2879
            iy_ctrl    <= latch_iy;
2880
            up_ctrl    <= latch_up;
2881
            sp_ctrl    <= latch_sp;
2882
            iv_ctrl    <= latch_iv;
2883
                                        -- idle ALU
2884
            left_ctrl  <= pc_left;
2885
            right_ctrl <= one_right;
2886
            alu_ctrl   <= alu_add16;
2887
            cc_ctrl    <= latch_cc;
2888
                                        -- increment the pc
2889
            pc_ctrl    <= incr_pc;
2890
                                        -- next state
2891
            case op_code(3 downto 0) is
2892
              when "1110" =>            -- jmp
2893
                return_state <= jmp_state;
2894
              when "1111" =>            -- clr
2895
                return_state <= single_op_exec_state;
2896
              when others =>
2897
                return_state <= single_op_read_state;
2898
            end case;
2899
            st_ctrl    <= push_st;
2900
            next_state <= indexed_state;
2901
          --
2902
          -- Single operand extended addressing
2903
          -- three byte instruction so advance the PC
2904
          -- Low order EA holds high order address
2905
          --
2906
          when "0111" =>                -- extended single op
2907
            op_ctrl    <= latch_op;
2908
            acca_ctrl  <= latch_acca;
2909
            accb_ctrl  <= latch_accb;
2910
            ix_ctrl    <= latch_ix;
2911
            iy_ctrl    <= latch_iy;
2912
            up_ctrl    <= latch_up;
2913
            sp_ctrl    <= latch_sp;
2914
            iv_ctrl    <= latch_iv;
2915
                                        -- idle ALU
2916
            left_ctrl  <= pc_left;
2917
            right_ctrl <= one_right;
2918
            alu_ctrl   <= alu_add16;
2919
            cc_ctrl    <= latch_cc;
2920
                                        -- increment PC
2921
            pc_ctrl    <= incr_pc;
2922
                                        --
2923
            case op_code(3 downto 0) is
2924
              when "1110" =>            -- jmp
2925
                return_state <= jmp_state;
2926
              when "1111" =>            -- clr
2927
                return_state <= single_op_exec_state;
2928
              when others =>
2929
                return_state <= single_op_read_state;
2930
            end case;
2931
            st_ctrl    <= push_st;
2932
            next_state <= extended_state;
2933
 
2934
          when "1000" =>                  -- acca immediate
2935
            op_ctrl   <= latch_op;
2936
            acca_ctrl <= latch_acca;
2937
            accb_ctrl <= latch_accb;
2938
            ix_ctrl   <= latch_ix;
2939
            iy_ctrl   <= latch_iy;
2940
            up_ctrl   <= latch_up;
2941
            iv_ctrl   <= latch_iv;
2942
            -- increment the pc
2943
            pc_ctrl   <= incr_pc;
2944
            case op_code(3 downto 0) is
2945
              when   "0011" |   -- subd #
2946
                     "1100" |   -- cmpx #
2947
                     "1110" =>  -- ldx #
2948
                                -- idle ALU
2949
                left_ctrl    <= pc_left;
2950
                right_ctrl   <= zero_right;
2951
                alu_ctrl     <= alu_add16;
2952
                cc_ctrl      <= latch_cc;
2953
                sp_ctrl      <= latch_sp;
2954
                                          --
2955
                st_ctrl      <= push_st;
2956
                return_state <= fetch_state;
2957
                next_state   <= imm16_state;
2958
 
2959
              --
2960
              -- bsr offset - Branch to subroutine (2 bytes)
2961
              -- 6809 => 7 cycles
2962
              -- cpu09 => 5 cycles
2963
              -- 1 op=(pc) / pc=pc+1
2964
              -- 2 md_hi=sign(pc) / md_lo=(pc) / sp=sp-1 / pc=pc+1
2965
              -- 3 (sp)=pc_lo / sp=sp-1
2966
              -- 4 (sp)=pc_hi
2967
              -- 5 pc=pc+md
2968
              --
2969
              when "1101" =>            -- bsr
2970
                                        -- pre decrement SP
2971
                left_ctrl    <= sp_left;
2972
                right_ctrl   <= one_right;
2973
                alu_ctrl     <= alu_sub16;
2974
                cc_ctrl      <= latch_cc;
2975
                sp_ctrl      <= load_sp;
2976
                                        --
2977
                st_ctrl      <= push_st;
2978
                return_state <= sbranch_state;
2979
                next_state   <= push_return_lo_state;
2980
 
2981
              when others =>
2982
                                        -- idle ALU
2983
                left_ctrl    <= pc_left;
2984
                right_ctrl   <= zero_right;
2985
                alu_ctrl     <= alu_add16;
2986
                cc_ctrl      <= latch_cc;
2987
                sp_ctrl      <= latch_sp;
2988
                                        --
2989
                st_ctrl      <= idle_st;
2990
                return_state <= fetch_state;
2991
                next_state   <= fetch_state;
2992
            end case;
2993
 
2994
          when "1001" =>                  -- acca direct
2995
            op_ctrl   <= latch_op;
2996
            acca_ctrl <= latch_acca;
2997
            accb_ctrl <= latch_accb;
2998
            ix_ctrl   <= latch_ix;
2999
            iy_ctrl   <= latch_iy;
3000
            up_ctrl   <= latch_up;
3001
            iv_ctrl   <= latch_iv;
3002
                                          -- increment the pc
3003
            pc_ctrl   <= incr_pc;
3004
            case op_code(3 downto 0) is
3005
              when "0011" |               -- subd
3006
                               "1100" |   -- cmpx
3007
                               "1110" =>  -- ldx
3008
                                          -- idle ALU
3009
                left_ctrl    <= pc_left;
3010
                right_ctrl   <= one_right;
3011
                alu_ctrl     <= alu_add16;
3012
                cc_ctrl      <= latch_cc;
3013
                sp_ctrl      <= latch_sp;
3014
                                          --
3015
                st_ctrl      <= idle_st;
3016
                return_state <= fetch_state;
3017
                next_state   <= dual_op_read16_state;
3018
 
3019
              when "0111" =>            -- sta direct
3020
                                        -- idle ALU
3021
                left_ctrl    <= acca_left;
3022
                right_ctrl   <= zero_right;
3023
                alu_ctrl     <= alu_nop;
3024
                cc_ctrl      <= latch_cc;
3025
                sp_ctrl      <= latch_sp;
3026
                                        --
3027
                st_ctrl      <= idle_st;
3028
                return_state <= fetch_state;
3029
                next_state   <= dual_op_write8_state;
3030
 
3031
              when "1111" =>            -- stx direct
3032
                                        -- idle ALU
3033
                left_ctrl    <= ix_left;
3034
                right_ctrl   <= zero_right;
3035
                alu_ctrl     <= alu_nop;
3036
                cc_ctrl      <= latch_cc;
3037
                sp_ctrl      <= latch_sp;
3038
                                        --
3039
                st_ctrl      <= idle_st;
3040
                return_state <= fetch_state;
3041
                next_state   <= dual_op_write16_state;
3042
 
3043
              --
3044
              -- jsr direct - Jump to subroutine in direct page (2 bytes)
3045
              -- 6809 => 7 cycles
3046
              -- cpu09 => 5 cycles
3047
              -- 1 op=(pc) / pc=pc+1
3048
              -- 2 ea_hi=0 / ea_lo=(pc) / sp=sp-1 / pc=pc+1
3049
              -- 3 (sp)=pc_lo / sp=sp-1
3050
              -- 4 (sp)=pc_hi
3051
              -- 5 pc=ea
3052
              --
3053
              when "1101" =>            -- jsr direct
3054
                                        -- pre decrement sp
3055
                left_ctrl    <= sp_left;
3056
                right_ctrl   <= one_right;
3057
                alu_ctrl     <= alu_sub16;
3058
                cc_ctrl      <= latch_cc;
3059
                sp_ctrl      <= load_sp;
3060
                                        --
3061
                st_ctrl      <= push_st;
3062
                return_state <= jmp_state;
3063
                next_state   <= push_return_lo_state;
3064
 
3065
              when others =>
3066
                                        -- idle ALU
3067
                left_ctrl    <= acca_left;
3068
                right_ctrl   <= zero_right;
3069
                alu_ctrl     <= alu_nop;
3070
                cc_ctrl      <= latch_cc;
3071
                sp_ctrl      <= latch_sp;
3072
                                        --
3073
                st_ctrl      <= idle_st;
3074
                return_state <= fetch_state;
3075
                next_state   <= dual_op_read8_state;
3076
            end case;
3077
 
3078
          when "1010" =>                  -- acca indexed
3079
            op_ctrl   <= latch_op;
3080
            acca_ctrl <= latch_acca;
3081
            accb_ctrl <= latch_accb;
3082
            ix_ctrl   <= latch_ix;
3083
            iy_ctrl   <= latch_iy;
3084
            up_ctrl   <= latch_up;
3085
            iv_ctrl   <= latch_iv;
3086
                                          -- increment the pc
3087
            pc_ctrl   <= incr_pc;
3088
            case op_code(3 downto 0) is
3089
              when "0011" |               -- subd
3090
                               "1100" |   -- cmpx
3091
                               "1110" =>  -- ldx
3092
                                          -- idle ALU
3093
                left_ctrl    <= pc_left;
3094
                right_ctrl   <= zero_right;
3095
                alu_ctrl     <= alu_add16;
3096
                cc_ctrl      <= latch_cc;
3097
                sp_ctrl      <= latch_sp;
3098
                                          --
3099
                st_ctrl      <= push_st;
3100
                return_state <= dual_op_read16_state;
3101
                next_state   <= indexed_state;
3102
 
3103
              when "0111" =>            -- staa ,x
3104
                                        -- idle ALU
3105
                left_ctrl    <= acca_left;
3106
                right_ctrl   <= zero_right;
3107
                alu_ctrl     <= alu_nop;
3108
                cc_ctrl      <= latch_cc;
3109
                sp_ctrl      <= latch_sp;
3110
                                        --
3111
                st_ctrl      <= push_st;
3112
                return_state <= dual_op_write8_state;
3113
                next_state   <= indexed_state;
3114
 
3115
              when "1111" =>            -- stx ,x
3116
                                        -- idle ALU
3117
                left_ctrl    <= ix_left;
3118
                right_ctrl   <= zero_right;
3119
                alu_ctrl     <= alu_nop;
3120
                cc_ctrl      <= latch_cc;
3121
                sp_ctrl      <= latch_sp;
3122
                                        --
3123
                st_ctrl      <= push_st;
3124
                return_state <= dual_op_write16_state;
3125
                next_state   <= indexed_state;
3126
 
3127
              when "1101" =>            -- jsr ,x
3128
                                        -- DO NOT pre decrement SP
3129
                left_ctrl    <= sp_left;
3130
                right_ctrl   <= one_right;
3131
                alu_ctrl     <= alu_sub16;
3132
                cc_ctrl      <= latch_cc;
3133
                sp_ctrl      <= latch_sp;
3134
                                        --
3135
                st_ctrl      <= push_st;
3136
                return_state <= jsr_state;
3137
                next_state   <= indexed_state;
3138
 
3139
              when others =>
3140
                                        -- idle ALU
3141
                left_ctrl    <= pc_left;
3142
                right_ctrl   <= one_right;
3143
                alu_ctrl     <= alu_add16;
3144
                cc_ctrl      <= latch_cc;
3145
                sp_ctrl      <= latch_sp;
3146
                                        --
3147
                st_ctrl      <= push_st;
3148
                return_state <= dual_op_read8_state;
3149
                next_state   <= indexed_state;
3150
            end case;
3151
 
3152
          when "1011" =>                  -- acca extended
3153
            op_ctrl   <= latch_op;
3154
            acca_ctrl <= latch_acca;
3155
            accb_ctrl <= latch_accb;
3156
            ix_ctrl   <= latch_ix;
3157
            iy_ctrl   <= latch_iy;
3158
            up_ctrl   <= latch_up;
3159
            iv_ctrl   <= latch_iv;
3160
                                          -- increment the pc
3161
            pc_ctrl   <= incr_pc;
3162
            case op_code(3 downto 0) is
3163
              when "0011" |               -- subd
3164
                               "1100" |   -- cmpx
3165
                               "1110" =>  -- ldx
3166
                                          -- idle ALU
3167
                left_ctrl    <= pc_left;
3168
                right_ctrl   <= one_right;
3169
                alu_ctrl     <= alu_add16;
3170
                cc_ctrl      <= latch_cc;
3171
                sp_ctrl      <= latch_sp;
3172
                                          --
3173
                st_ctrl      <= push_st;
3174
                return_state <= dual_op_read16_state;
3175
                next_state   <= extended_state;
3176
 
3177
              when "0111" =>            -- staa >
3178
                                        -- idle ALU
3179
                left_ctrl    <= acca_left;
3180
                right_ctrl   <= zero_right;
3181
                alu_ctrl     <= alu_nop;
3182
                cc_ctrl      <= latch_cc;
3183
                sp_ctrl      <= latch_sp;
3184
                                        --
3185
                st_ctrl      <= push_st;
3186
                return_state <= dual_op_write8_state;
3187
                next_state   <= extended_state;
3188
 
3189
              when "1111" =>            -- stx >
3190
                                        -- idle ALU
3191
                left_ctrl    <= ix_left;
3192
                right_ctrl   <= zero_right;
3193
                alu_ctrl     <= alu_nop;
3194
                cc_ctrl      <= latch_cc;
3195
                sp_ctrl      <= latch_sp;
3196
                                        --
3197
                st_ctrl      <= push_st;
3198
                return_state <= dual_op_write16_state;
3199
                next_state   <= extended_state;
3200
 
3201
              when "1101" =>            -- jsr >extended
3202
                                        -- DO NOT pre decrement sp
3203
                left_ctrl    <= sp_left;
3204
                right_ctrl   <= one_right;
3205
                alu_ctrl     <= alu_sub16;
3206
                cc_ctrl      <= latch_cc;
3207
                sp_ctrl      <= latch_sp;
3208
                                        --
3209
                st_ctrl      <= push_st;
3210
                return_state <= jsr_state;
3211
                next_state   <= extended_state;
3212
 
3213
              when others =>
3214
                                        -- idle ALU
3215
                left_ctrl    <= acca_left;
3216
                right_ctrl   <= zero_right;
3217
                alu_ctrl     <= alu_st8;
3218
                cc_ctrl      <= latch_cc;
3219
                sp_ctrl      <= latch_sp;
3220
                                        --
3221
                st_ctrl      <= push_st;
3222
                return_state <= dual_op_read8_state;
3223
                next_state   <= extended_state;
3224
            end case;
3225
 
3226
          when "1100" =>                   -- accb immediate
3227
            op_ctrl    <= latch_op;
3228
            acca_ctrl  <= latch_acca;
3229
            accb_ctrl  <= latch_accb;
3230
            ix_ctrl    <= latch_ix;
3231
            iy_ctrl    <= latch_iy;
3232
            up_ctrl    <= latch_up;
3233
            sp_ctrl    <= latch_sp;
3234
            iv_ctrl    <= latch_iv;
3235
            --
3236
            left_ctrl  <= pc_left;
3237
            right_ctrl <= one_right;
3238
            alu_ctrl   <= alu_add16;
3239
            cc_ctrl    <= latch_cc;
3240
            -- increment the pc
3241
            pc_ctrl    <= incr_pc;
3242
            case op_code(3 downto 0) is
3243
              when "0011" |                -- addd #
3244
                   "1100" |   -- ldd #
3245
                   "1110" =>  -- ldu #
3246
                st_ctrl      <= push_st;
3247
                return_state <= fetch_state;
3248
                next_state   <= imm16_state;
3249
 
3250
              when others =>
3251
                st_ctrl      <= idle_st;
3252
                return_state <= fetch_state;
3253
                next_state   <= fetch_state;
3254
 
3255
            end case;
3256
 
3257
 
3258
          when "1101" =>                   -- accb direct
3259
            op_ctrl    <= latch_op;
3260
            acca_ctrl  <= latch_acca;
3261
            accb_ctrl  <= latch_accb;
3262
            ix_ctrl    <= latch_ix;
3263
            iy_ctrl    <= latch_iy;
3264
            up_ctrl    <= latch_up;
3265
            sp_ctrl    <= latch_sp;
3266
            iv_ctrl    <= latch_iv;
3267
                                           -- increment the pc
3268
            pc_ctrl    <= incr_pc;
3269
 
3270
            left_ctrl  <= pc_left;
3271
            right_ctrl <= zero_right;
3272
            alu_ctrl   <= alu_nop;
3273
            cc_ctrl    <= latch_cc;
3274
 
3275
            case op_code(3 downto 0) is
3276
              when "0011" |   -- addd
3277
                   "1100" |   -- ldd
3278
                   "1110" =>  -- ldu
3279
                st_ctrl      <= idle_st;
3280
                return_state <= fetch_state;
3281
                next_state   <= dual_op_read16_state;
3282
 
3283
              when "0111" =>            -- stab direct
3284
                st_ctrl      <= idle_st;
3285
                return_state <= fetch_state;
3286
                next_state   <= dual_op_write8_state;
3287
 
3288
              when "1101" =>            -- std direct
3289
                st_ctrl      <= idle_st;
3290
                return_state <= fetch_state;
3291
                next_state   <= dual_op_write16_state;
3292
 
3293
              when "1111" =>            -- stu direct
3294
                st_ctrl      <= idle_st;
3295
                return_state <= fetch_state;
3296
                next_state   <= dual_op_write16_state;
3297
 
3298
              when others =>
3299
                st_ctrl      <= idle_st;
3300
                return_state <= fetch_state;
3301
                next_state   <= dual_op_read8_state;
3302
            end case;
3303
 
3304
          when "1110" =>                 -- accb indexed
3305
            op_ctrl    <= latch_op;
3306
            acca_ctrl  <= latch_acca;
3307
            accb_ctrl  <= latch_accb;
3308
            ix_ctrl    <= latch_ix;
3309
            iy_ctrl    <= latch_iy;
3310
            up_ctrl    <= latch_up;
3311
            sp_ctrl    <= latch_sp;
3312
            iv_ctrl    <= latch_iv;
3313
                                         -- increment the pc
3314
            pc_ctrl    <= incr_pc;
3315
 
3316
            left_ctrl  <= pc_left;
3317
            right_ctrl <= zero_right;
3318
            alu_ctrl   <= alu_nop;
3319
            cc_ctrl    <= latch_cc;
3320
 
3321
            case op_code(3 downto 0) is
3322
              when "0011" |   -- addd
3323
                   "1100" |   -- ldd
3324
                   "1110" =>  -- ldu
3325
                st_ctrl      <= push_st;
3326
                return_state <= dual_op_read16_state;
3327
                next_state   <= indexed_state;
3328
 
3329
              when "0111" =>            -- stab indexed
3330
                st_ctrl      <= push_st;
3331
                return_state <= dual_op_write8_state;
3332
                next_state   <= indexed_state;
3333
 
3334
              when "1101" =>            -- std indexed
3335
                st_ctrl      <= push_st;
3336
                return_state <= dual_op_write16_state;
3337
                next_state   <= indexed_state;
3338
 
3339
              when "1111" =>            -- stu indexed
3340
                st_ctrl      <= push_st;
3341
                return_state <= dual_op_write16_state;
3342
                next_state   <= indexed_state;
3343
 
3344
              when others =>
3345
                st_ctrl      <= push_st;
3346
                return_state <= dual_op_read8_state;
3347
                next_state   <= indexed_state;
3348
            end case;
3349
 
3350
          when "1111" =>                -- accb extended
3351
            op_ctrl    <= latch_op;
3352
            acca_ctrl  <= latch_acca;
3353
            accb_ctrl  <= latch_accb;
3354
            ix_ctrl    <= latch_ix;
3355
            iy_ctrl    <= latch_iy;
3356
            up_ctrl    <= latch_up;
3357
            sp_ctrl    <= latch_sp;
3358
            iv_ctrl    <= latch_iv;
3359
                                        -- increment the pc
3360
            pc_ctrl    <= incr_pc;
3361
                                        --
3362
            left_ctrl  <= pc_left;
3363
            right_ctrl <= zero_right;
3364
            alu_ctrl   <= alu_nop;
3365
            cc_ctrl    <= latch_cc;
3366
                                        --
3367
            case op_code(3 downto 0) is
3368
              when "0011" |   -- addd
3369
                   "1100" |   -- ldd
3370
                   "1110" =>  -- ldu
3371
                st_ctrl      <= push_st;
3372
                return_state <= dual_op_read16_state;
3373
                next_state   <= extended_state;
3374
 
3375
              when "0111" =>            -- stab extended
3376
                st_ctrl      <= push_st;
3377
                return_state <= dual_op_write8_state;
3378
                next_state   <= extended_state;
3379
 
3380
              when "1101" =>            -- std extended
3381
                st_ctrl      <= push_st;
3382
                return_state <= dual_op_write16_state;
3383
                next_state   <= extended_state;
3384
 
3385
              when "1111" =>            -- stu  extended
3386
                st_ctrl      <= push_st;
3387
                return_state <= dual_op_write16_state;
3388
                next_state   <= extended_state;
3389
 
3390
              when others =>
3391
                st_ctrl      <= push_st;
3392
                return_state <= dual_op_read8_state;
3393
                next_state   <= extended_state;
3394
            end case;
3395
 
3396
          when others =>
3397
            op_ctrl      <= latch_op;
3398
            acca_ctrl    <= latch_acca;
3399
            accb_ctrl    <= latch_accb;
3400
            ix_ctrl      <= latch_ix;
3401
            iy_ctrl      <= latch_iy;
3402
            up_ctrl      <= latch_up;
3403
            sp_ctrl      <= latch_sp;
3404
            iv_ctrl      <= latch_iv;
3405
                                        -- idle the ALU
3406
            left_ctrl    <= pc_left;
3407
            right_ctrl   <= zero_right;
3408
            alu_ctrl     <= alu_nop;
3409
            cc_ctrl      <= latch_cc;
3410
                                        -- idle the pc
3411
            pc_ctrl      <= latch_pc;
3412
                                        --
3413
            st_ctrl      <= idle_st;
3414
            return_state <= fetch_state;
3415
            next_state   <= fetch_state;
3416
        end case;
3417
 
3418
        --
3419
        -- Here to decode prefix 2 instruction
3420
        -- and fetch next byte of intruction
3421
        -- whether it be necessary or not
3422
        --
3423
      when decode2_state =>
3424
        op_ctrl   <= latch_op;
3425
        pre_ctrl  <= latch_pre;
3426
        -- fetch first byte of address or immediate data
3427
        ea_ctrl   <= fetch_first_ea;
3428
        md_ctrl   <= fetch_first_md;
3429
        addr_ctrl <= fetch_ad;
3430
        dout_ctrl <= md_lo_dout;
3431
        nmi_ctrl  <= latch_nmi;
3432
        dp_ctrl   <= latch_dp;
3433
        case op_code(7 downto 4) is
3434
          --
3435
          -- lbcc -- long branch conditional
3436
          -- 6809 => branch 6 cycles, no branch 5 cycles
3437
          -- cpu09 => always 5 cycles
3438
          -- 1 pre=(pc) / pc=pc+1
3439
          -- 2 op=(pc) / pc=pc+1
3440
          -- 3 md_hi=sign(pc) / md_lo=(pc) / pc=pc+1
3441
          -- 4 md_hi=md_lo / md_lo=(pc) / pc=pc+1
3442
          -- 5 if cond pc=pc+md else pc=pc
3443
          --
3444
          when "0010" =>
3445
            acca_ctrl    <= latch_acca;
3446
            accb_ctrl    <= latch_accb;
3447
            ix_ctrl      <= latch_ix;
3448
            iy_ctrl      <= latch_iy;
3449
            sp_ctrl      <= latch_sp;
3450
            up_ctrl      <= latch_up;
3451
            iv_ctrl      <= latch_iv;
3452
                                        -- increment the pc
3453
            left_ctrl    <= pc_left;
3454
            right_ctrl   <= zero_right;
3455
            alu_ctrl     <= alu_nop;
3456
            cc_ctrl      <= latch_cc;
3457
            pc_ctrl      <= incr_pc;
3458
                                        --
3459
            st_ctrl      <= idle_st;
3460
            return_state <= fetch_state;
3461
            next_state   <= lbranch_state;
3462
 
3463
          --
3464
          -- Single byte stack operators
3465
          -- Do not advance PC
3466
          --
3467
          when "0011" =>
3468
            acca_ctrl <= latch_acca;
3469
            accb_ctrl <= latch_accb;
3470
            ix_ctrl   <= latch_ix;
3471
            iy_ctrl   <= latch_iy;
3472
            up_ctrl   <= latch_up;
3473
            pc_ctrl   <= latch_pc;
3474
            case op_code(3 downto 0) is
3475
              when "1111" =>            -- swi 2
3476
                                        -- predecrement sp
3477
                left_ctrl    <= sp_left;
3478
                right_ctrl   <= one_right;
3479
                alu_ctrl     <= alu_sub16;
3480
                cc_ctrl      <= latch_cc;
3481
                sp_ctrl      <= load_sp;
3482
                iv_ctrl      <= swi2_iv;
3483
                                        --
3484
                st_ctrl      <= idle_st;
3485
                return_state <= fetch_state;
3486
                next_state   <= int_entire_state;
3487
 
3488
              when others =>
3489
                left_ctrl    <= sp_left;
3490
                right_ctrl   <= zero_right;
3491
                alu_ctrl     <= alu_nop;
3492
                cc_ctrl      <= latch_cc;
3493
                sp_ctrl      <= latch_sp;
3494
                iv_ctrl      <= latch_iv;
3495
                                        --
3496
                st_ctrl      <= idle_st;
3497
                return_state <= fetch_state;
3498
                next_state   <= fetch_state;
3499
            end case;
3500
 
3501
          when "1000" =>                -- acca immediate
3502
            acca_ctrl  <= latch_acca;
3503
            accb_ctrl  <= latch_accb;
3504
            ix_ctrl    <= latch_ix;
3505
            iy_ctrl    <= latch_iy;
3506
            up_ctrl    <= latch_up;
3507
            sp_ctrl    <= latch_sp;
3508
            iv_ctrl    <= latch_iv;
3509
            -- Idle the ALU
3510
            left_ctrl  <= pc_left;
3511
            right_ctrl <= one_right;
3512
            alu_ctrl   <= alu_add16;
3513
            cc_ctrl    <= latch_cc;
3514
            -- increment the pc
3515
            pc_ctrl    <= incr_pc;
3516
            case op_code(3 downto 0) is
3517
              when "0011" |   -- cmpd #
3518
                   "1100" |   -- cmpy #
3519
                   "1110" =>  -- ldy #
3520
                st_ctrl      <= push_st;
3521
                return_state <= fetch_state;
3522
                next_state   <= imm16_state;
3523
 
3524
              when others =>
3525
                st_ctrl      <= idle_st;
3526
                return_state <= fetch_state;
3527
                next_state   <= fetch_state;
3528
 
3529
            end case;
3530
 
3531
          when "1001" =>                    -- acca direct
3532
            acca_ctrl  <= latch_acca;
3533
            accb_ctrl  <= latch_accb;
3534
            ix_ctrl    <= latch_ix;
3535
            iy_ctrl    <= latch_iy;
3536
            up_ctrl    <= latch_up;
3537
            sp_ctrl    <= latch_sp;
3538
            iv_ctrl    <= latch_iv;
3539
            -- idle the ALU
3540
            left_ctrl  <= pc_left;
3541
            right_ctrl <= zero_right;
3542
            alu_ctrl   <= alu_nop;
3543
            cc_ctrl    <= latch_cc;
3544
            -- increment the pc
3545
            pc_ctrl    <= incr_pc;
3546
            case op_code(3 downto 0) is
3547
              when   "0011" |     -- cmpd <
3548
                     "1100" |     -- cmpy <
3549
                     "1110"   =>  -- ldy <
3550
                st_ctrl      <= idle_st;
3551
                return_state <= fetch_state;
3552
                next_state   <= dual_op_read16_state;
3553
 
3554
              when "1111" =>            -- sty <
3555
                st_ctrl      <= idle_st;
3556
                return_state <= fetch_state;
3557
                next_state   <= dual_op_write16_state;
3558
 
3559
              when others =>
3560
                st_ctrl      <= idle_st;
3561
                return_state <= fetch_state;
3562
                next_state   <= fetch_state;
3563
 
3564
            end case;
3565
 
3566
          when "1010" =>                  -- acca indexed
3567
            acca_ctrl  <= latch_acca;
3568
            accb_ctrl  <= latch_accb;
3569
            ix_ctrl    <= latch_ix;
3570
            iy_ctrl    <= latch_iy;
3571
            up_ctrl    <= latch_up;
3572
            sp_ctrl    <= latch_sp;
3573
            iv_ctrl    <= latch_iv;
3574
                                          -- idle the ALU
3575
            left_ctrl  <= pc_left;
3576
            right_ctrl <= zero_right;
3577
            alu_ctrl   <= alu_nop;
3578
            cc_ctrl    <= latch_cc;
3579
                                          -- increment the pc
3580
            pc_ctrl    <= incr_pc;
3581
            case op_code(3 downto 0) is
3582
              when "0011" |   -- cmpd ,ind
3583
                   "1100" |   -- cmpy ,ind
3584
                   "1110" =>  -- ldy ,ind
3585
                st_ctrl      <= push_st;
3586
                return_state <= dual_op_read16_state;
3587
                next_state   <= indexed_state;
3588
 
3589
              when "1111" =>            -- sty ,ind
3590
                st_ctrl      <= push_st;
3591
                return_state <= dual_op_write16_state;
3592
                next_state   <= indexed_state;
3593
 
3594
              when others =>
3595
                st_ctrl      <= idle_st;
3596
                return_state <= fetch_state;
3597
                next_state   <= fetch_state;
3598
            end case;
3599
 
3600
          when "1011" =>                -- acca extended
3601
            acca_ctrl  <= latch_acca;
3602
            accb_ctrl  <= latch_accb;
3603
            ix_ctrl    <= latch_ix;
3604
            iy_ctrl    <= latch_iy;
3605
            up_ctrl    <= latch_up;
3606
            sp_ctrl    <= latch_sp;
3607
            iv_ctrl    <= latch_iv;
3608
                                        -- idle the ALU
3609
            left_ctrl  <= pc_left;
3610
            right_ctrl <= zero_right;
3611
            alu_ctrl   <= alu_nop;
3612
            cc_ctrl    <= latch_cc;
3613
                                        -- increment the pc
3614
            pc_ctrl    <= incr_pc;
3615
            case op_code(3 downto 0) is
3616
              when "0011" |   -- cmpd <
3617
                   "1100" |   -- cmpy <
3618
                   "1110" =>  -- ldy <
3619
                st_ctrl      <= push_st;
3620
                return_state <= dual_op_read16_state;
3621
                next_state   <= extended_state;
3622
 
3623
              when "1111" =>            -- sty >
3624
                st_ctrl      <= push_st;
3625
                return_state <= dual_op_write16_state;
3626
                next_state   <= extended_state;
3627
 
3628
              when others =>
3629
                st_ctrl      <= idle_st;
3630
                return_state <= fetch_state;
3631
                next_state   <= fetch_state;
3632
 
3633
            end case;
3634
 
3635
          when "1100" =>                -- accb immediate
3636
            acca_ctrl  <= latch_acca;
3637
            accb_ctrl  <= latch_accb;
3638
            ix_ctrl    <= latch_ix;
3639
            iy_ctrl    <= latch_iy;
3640
            up_ctrl    <= latch_up;
3641
            sp_ctrl    <= latch_sp;
3642
            iv_ctrl    <= latch_iv;
3643
                                        -- idle the alu
3644
            left_ctrl  <= pc_left;
3645
            right_ctrl <= zero_right;
3646
            alu_ctrl   <= alu_nop;
3647
            cc_ctrl    <= latch_cc;
3648
                                        -- increment the pc
3649
            pc_ctrl    <= incr_pc;
3650
            case op_code(3 downto 0) is
3651
              when "0011" |   -- undef #
3652
                   "1100" |   -- undef #
3653
                   "1110" =>  -- lds #
3654
                st_ctrl      <= push_st;
3655
                return_state <= fetch_state;
3656
                next_state   <= imm16_state;
3657
 
3658
              when others =>
3659
                st_ctrl      <= idle_st;
3660
                return_state <= fetch_state;
3661
                next_state   <= fetch_state;
3662
 
3663
            end case;
3664
 
3665
          when "1101" =>                                        -- accb direct
3666
            acca_ctrl  <= latch_acca;
3667
            accb_ctrl  <= latch_accb;
3668
            ix_ctrl    <= latch_ix;
3669
            iy_ctrl    <= latch_iy;
3670
            up_ctrl    <= latch_up;
3671
            sp_ctrl    <= latch_sp;
3672
            iv_ctrl    <= latch_iv;
3673
                                                                -- idle the alu
3674
            left_ctrl  <= pc_left;
3675
            right_ctrl <= zero_right;
3676
            alu_ctrl   <= alu_nop;
3677
            cc_ctrl    <= latch_cc;
3678
                                                                -- increment the pc
3679
            pc_ctrl    <= incr_pc;
3680
            case op_code(3 downto 0) is
3681
              when "0011" |     -- undef <
3682
                   "1100" |     -- undef <
3683
                   "1110"   =>  -- lds <
3684
                st_ctrl      <= idle_st;
3685
                return_state <= fetch_state;
3686
                next_state   <= dual_op_read16_state;
3687
 
3688
              when "1111" =>            -- sts <
3689
                st_ctrl      <= idle_st;
3690
                return_state <= fetch_state;
3691
                next_state   <= dual_op_write16_state;
3692
 
3693
              when others =>
3694
                st_ctrl      <= idle_st;
3695
                return_state <= fetch_state;
3696
                next_state   <= fetch_state;
3697
 
3698
            end case;
3699
 
3700
          when "1110" =>                                        -- accb indexed
3701
            acca_ctrl  <= latch_acca;
3702
            accb_ctrl  <= latch_accb;
3703
            ix_ctrl    <= latch_ix;
3704
            iy_ctrl    <= latch_iy;
3705
            up_ctrl    <= latch_up;
3706
            sp_ctrl    <= latch_sp;
3707
            iv_ctrl    <= latch_iv;
3708
                                                                -- idle the alu
3709
            left_ctrl  <= pc_left;
3710
            right_ctrl <= zero_right;
3711
            alu_ctrl   <= alu_nop;
3712
            cc_ctrl    <= latch_cc;
3713
                                                                -- increment the pc
3714
            pc_ctrl    <= incr_pc;
3715
            case op_code(3 downto 0) is
3716
              when "0011" |                                     -- undef ,ind
3717
                   "1100" |   -- undef ,ind
3718
                   "1110" =>  -- lds ,ind
3719
                st_ctrl      <= push_st;
3720
                return_state <= dual_op_read16_state;
3721
                next_state   <= indexed_state;
3722
 
3723
              when "1111" =>            -- sts ,ind
3724
                st_ctrl      <= push_st;
3725
                return_state <= dual_op_write16_state;
3726
                next_state   <= indexed_state;
3727
 
3728
              when others =>
3729
                st_ctrl      <= idle_st;
3730
                return_state <= fetch_state;
3731
                next_state   <= fetch_state;
3732
 
3733
            end case;
3734
 
3735
          when "1111" =>                -- accb extended
3736
            acca_ctrl  <= latch_acca;
3737
            accb_ctrl  <= latch_accb;
3738
            ix_ctrl    <= latch_ix;
3739
            iy_ctrl    <= latch_iy;
3740
            up_ctrl    <= latch_up;
3741
            sp_ctrl    <= latch_sp;
3742
            iv_ctrl    <= latch_iv;
3743
                                        -- idle the alu
3744
            left_ctrl  <= pc_left;
3745
            right_ctrl <= zero_right;
3746
            alu_ctrl   <= alu_nop;
3747
            cc_ctrl    <= latch_cc;
3748
                                        -- increment the pc
3749
            pc_ctrl    <= incr_pc;
3750
            case op_code(3 downto 0) is
3751
              when "0011" |             -- undef >
3752
                   "1100" |   -- undef >
3753
                   "1110" =>  -- lds >
3754
                                     st_ctrl <= push_st;
3755
              return_state <= dual_op_read16_state;
3756
              next_state   <= extended_state;
3757
 
3758
              when "1111" =>            -- sts >
3759
              st_ctrl      <= push_st;
3760
              return_state <= dual_op_write16_state;
3761
              next_state   <= extended_state;
3762
 
3763
              when others =>
3764
              st_ctrl      <= idle_st;
3765
              return_state <= fetch_state;
3766
              next_state   <= fetch_state;
3767
 
3768
            end case;
3769
 
3770
          when others =>
3771
            acca_ctrl    <= latch_acca;
3772
            accb_ctrl    <= latch_accb;
3773
            ix_ctrl      <= latch_ix;
3774
            iy_ctrl      <= latch_iy;
3775
            up_ctrl      <= latch_up;
3776
            sp_ctrl      <= latch_sp;
3777
            iv_ctrl      <= latch_iv;
3778
                                        -- idle the alu
3779
            left_ctrl    <= pc_left;
3780
            right_ctrl   <= zero_right;
3781
            alu_ctrl     <= alu_nop;
3782
            cc_ctrl      <= latch_cc;
3783
                                        -- idle the pc
3784
            pc_ctrl      <= latch_pc;
3785
            st_ctrl      <= idle_st;
3786
            return_state <= fetch_state;
3787
            next_state   <= fetch_state;
3788
        end case;
3789
      --
3790
      -- Here to decode instruction
3791
      -- and fetch next byte of intruction
3792
      -- whether it be necessary or not
3793
      --
3794
      when decode3_state =>
3795
        op_ctrl   <= latch_op;
3796
        pre_ctrl  <= latch_pre;
3797
        ea_ctrl   <= fetch_first_ea;
3798
        md_ctrl   <= fetch_first_md;
3799
        addr_ctrl <= fetch_ad;
3800
        dout_ctrl <= md_lo_dout;
3801
        nmi_ctrl  <= latch_nmi;
3802
        dp_ctrl   <= latch_dp;
3803
        case op_code(7 downto 4) is
3804
          --
3805
          -- Single byte stack operators
3806
          -- Do not advance PC
3807
          --
3808
          when "0011" =>
3809
            acca_ctrl <= latch_acca;
3810
            accb_ctrl <= latch_accb;
3811
            ix_ctrl   <= latch_ix;
3812
            iy_ctrl   <= latch_iy;
3813
            up_ctrl   <= latch_up;
3814
            pc_ctrl   <= latch_pc;
3815
                                        --
3816
            case op_code(3 downto 0) is
3817
              when "1111" =>            -- swi3
3818
                                        -- predecrement sp
3819
                left_ctrl    <= sp_left;
3820
                right_ctrl   <= one_right;
3821
                alu_ctrl     <= alu_sub16;
3822
                cc_ctrl      <= latch_cc;
3823
                sp_ctrl      <= load_sp;
3824
                iv_ctrl      <= swi3_iv;
3825
                                        --
3826
                st_ctrl      <= idle_st;
3827
                return_state <= fetch_state;
3828
                next_state   <= int_entire_state;
3829
              when others =>
3830
                left_ctrl    <= sp_left;
3831
                right_ctrl   <= zero_right;
3832
                alu_ctrl     <= alu_nop;
3833
                cc_ctrl      <= latch_cc;
3834
                sp_ctrl      <= latch_sp;
3835
                iv_ctrl      <= latch_iv;
3836
                                        --
3837
                st_ctrl      <= idle_st;
3838
                return_state <= fetch_state;
3839
                next_state   <= fetch_state;
3840
            end case;
3841
 
3842
          when "1000" =>                -- acca immediate
3843
            acca_ctrl  <= latch_acca;
3844
            accb_ctrl  <= latch_accb;
3845
            ix_ctrl    <= latch_ix;
3846
            iy_ctrl    <= latch_iy;
3847
            up_ctrl    <= latch_up;
3848
            sp_ctrl    <= latch_sp;
3849
            iv_ctrl    <= latch_iv;
3850
            -- idle the alu
3851
            left_ctrl  <= pc_left;
3852
            right_ctrl <= zero_right;
3853
            alu_ctrl   <= alu_nop;
3854
            cc_ctrl    <= latch_cc;
3855
            -- increment the pc
3856
            pc_ctrl    <= incr_pc;
3857
            case op_code(3 downto 0) is
3858
              when "0011" |      -- cmpu #
3859
                   "1100" |      -- cmps #
3860
                   "1110"    =>  -- undef #
3861
                st_ctrl      <= push_st;
3862
                return_state <= fetch_state;
3863
                next_state   <= imm16_state;
3864
              when others =>
3865
                st_ctrl      <= idle_st;
3866
                return_state <= fetch_state;
3867
                next_state   <= fetch_state;
3868
            end case;
3869
 
3870
          when "1001" =>                                        -- acca direct
3871
            acca_ctrl  <= latch_acca;
3872
            accb_ctrl  <= latch_accb;
3873
            ix_ctrl    <= latch_ix;
3874
            iy_ctrl    <= latch_iy;
3875
            up_ctrl    <= latch_up;
3876
            sp_ctrl    <= latch_sp;
3877
            iv_ctrl    <= latch_iv;
3878
                                                                -- idle the alu
3879
            left_ctrl  <= pc_left;
3880
            right_ctrl <= zero_right;
3881
            alu_ctrl   <= alu_nop;
3882
            cc_ctrl    <= latch_cc;
3883
                                                                -- increment the pc
3884
            pc_ctrl    <= incr_pc;
3885
            case op_code(3 downto 0) is
3886
              when "0011" |                                     -- cmpu <
3887
                   "1100" |   -- cmps <
3888
                   "1110" =>  -- undef <
3889
                st_ctrl      <= idle_st;
3890
                return_state <= fetch_state;
3891
                next_state   <= dual_op_read16_state;
3892
 
3893
              when others =>
3894
                st_ctrl      <= idle_st;
3895
                return_state <= fetch_state;
3896
                next_state   <= fetch_state;
3897
 
3898
            end case;
3899
 
3900
          when "1010" =>                                        -- acca indexed
3901
            acca_ctrl  <= latch_acca;
3902
            accb_ctrl  <= latch_accb;
3903
            ix_ctrl    <= latch_ix;
3904
            iy_ctrl    <= latch_iy;
3905
            up_ctrl    <= latch_up;
3906
            sp_ctrl    <= latch_sp;
3907
            iv_ctrl    <= latch_iv;
3908
                                                                -- idle the alu
3909
            left_ctrl  <= pc_left;
3910
            right_ctrl <= zero_right;
3911
            alu_ctrl   <= alu_nop;
3912
            cc_ctrl    <= latch_cc;
3913
                                                                -- increment the pc
3914
            pc_ctrl    <= incr_pc;
3915
            case op_code(3 downto 0) is
3916
              when "0011" |                                     -- cmpu ,X
3917
                   "1100" |   -- cmps ,X
3918
                   "1110" =>  -- undef ,X
3919
                st_ctrl      <= push_st;
3920
                return_state <= dual_op_read16_state;
3921
                next_state   <= indexed_state;
3922
 
3923
              when others =>
3924
                st_ctrl      <= idle_st;
3925
                return_state <= fetch_state;
3926
                next_state   <= fetch_state;
3927
 
3928
            end case;
3929
 
3930
          when "1011" =>                -- acca extended
3931
            acca_ctrl  <= latch_acca;
3932
            accb_ctrl  <= latch_accb;
3933
            ix_ctrl    <= latch_ix;
3934
            iy_ctrl    <= latch_iy;
3935
            up_ctrl    <= latch_up;
3936
            sp_ctrl    <= latch_sp;
3937
            iv_ctrl    <= latch_iv;
3938
                                        -- idle the alu
3939
            left_ctrl  <= pc_left;
3940
            right_ctrl <= zero_right;
3941
            alu_ctrl   <= alu_nop;
3942
            cc_ctrl    <= latch_cc;
3943
                                        -- increment the pc
3944
            pc_ctrl    <= incr_pc;
3945
            case op_code(3 downto 0) is
3946
              when "0011" |   -- cmpu >
3947
                   "1100" |   -- cmps >
3948
                   "1110" =>  -- undef >
3949
                  st_ctrl <= push_st;
3950
                  return_state <= dual_op_read16_state;
3951
                  next_state   <= extended_state;
3952
              when others =>
3953
                  st_ctrl      <= idle_st;
3954
                  return_state <= fetch_state;
3955
                  next_state   <= fetch_state;
3956
            end case;
3957
 
3958
          when others =>
3959
            acca_ctrl    <= latch_acca;
3960
            accb_ctrl    <= latch_accb;
3961
            ix_ctrl      <= latch_ix;
3962
            iy_ctrl      <= latch_iy;
3963
            up_ctrl      <= latch_up;
3964
            sp_ctrl      <= latch_sp;
3965
            iv_ctrl      <= latch_iv;
3966
                                        -- idle the alu
3967
            left_ctrl    <= pc_left;
3968
            right_ctrl   <= zero_right;
3969
            alu_ctrl     <= alu_nop;
3970
            cc_ctrl      <= latch_cc;
3971
                                        -- idle the pc
3972
            pc_ctrl      <= latch_pc;
3973
            st_ctrl      <= idle_st;
3974
            return_state <= fetch_state;
3975
            next_state   <= fetch_state;
3976
        end case;
3977
 
3978
        --
3979
      -- here if ea holds low byte
3980
      -- Direct
3981
      -- Extended
3982
      -- Indexed
3983
      -- read memory location
3984
      --
3985
      when single_op_read_state =>
3986
        op_ctrl      <= latch_op;
3987
        pre_ctrl     <= latch_pre;
3988
        acca_ctrl    <= latch_acca;
3989
        accb_ctrl    <= latch_accb;
3990
        ix_ctrl      <= latch_ix;
3991
        iy_ctrl      <= latch_iy;
3992
        up_ctrl      <= latch_up;
3993
        sp_ctrl      <= latch_sp;
3994
        pc_ctrl      <= latch_pc;
3995
        iv_ctrl      <= latch_iv;
3996
        dp_ctrl      <= latch_dp;
3997
        nmi_ctrl     <= latch_nmi;
3998
                                        -- idle ALU
3999
        left_ctrl    <= ea_left;
4000
        right_ctrl   <= zero_right;
4001
        alu_ctrl     <= alu_nop;
4002
        cc_ctrl      <= latch_cc;
4003
        ea_ctrl      <= latch_ea;
4004
                                        -- read memory into md
4005
        md_ctrl      <= fetch_first_md;
4006
        addr_ctrl    <= read_ad;
4007
        dout_ctrl    <= md_lo_dout;
4008
                                        --
4009
        st_ctrl      <= idle_st;
4010
        return_state <= fetch_state;
4011
        next_state   <= single_op_exec_state;
4012
 
4013
      when single_op_exec_state =>
4014
        op_ctrl      <= latch_op;
4015
        pre_ctrl     <= latch_pre;
4016
        acca_ctrl    <= latch_acca;
4017
        accb_ctrl    <= latch_accb;
4018
        ix_ctrl      <= latch_ix;
4019
        iy_ctrl      <= latch_iy;
4020
        up_ctrl      <= latch_up;
4021
        sp_ctrl      <= latch_sp;
4022
        dp_ctrl      <= latch_dp;
4023
        nmi_ctrl     <= latch_nmi;
4024
        iv_ctrl      <= latch_iv;
4025
        ea_ctrl      <= latch_ea;
4026
                                        -- idle the bus
4027
        addr_ctrl    <= idle_ad;
4028
        dout_ctrl    <= md_lo_dout;
4029
        st_ctrl      <= idle_st;
4030
        return_state <= fetch_state;
4031
        case op_code(3 downto 0) is
4032
          when "0000" =>                -- neg
4033
            left_ctrl  <= md_left;
4034
            right_ctrl <= zero_right;
4035
            alu_ctrl   <= alu_neg;
4036
            cc_ctrl    <= load_cc;
4037
            md_ctrl    <= load_md;
4038
            pc_ctrl    <= latch_pc;
4039
            next_state <= single_op_write_state;
4040
          when "0011" =>                -- com
4041
            left_ctrl  <= md_left;
4042
            right_ctrl <= zero_right;
4043
            alu_ctrl   <= alu_com;
4044
            cc_ctrl    <= load_cc;
4045
            md_ctrl    <= load_md;
4046
            pc_ctrl    <= latch_pc;
4047
            next_state <= single_op_write_state;
4048
          when "0100" =>                -- lsr
4049
            left_ctrl  <= md_left;
4050
            right_ctrl <= zero_right;
4051
            alu_ctrl   <= alu_lsr8;
4052
            cc_ctrl    <= load_cc;
4053
            md_ctrl    <= load_md;
4054
            pc_ctrl    <= latch_pc;
4055
            next_state <= single_op_write_state;
4056
          when "0110" =>                -- ror
4057
            left_ctrl  <= md_left;
4058
            right_ctrl <= zero_right;
4059
            alu_ctrl   <= alu_ror8;
4060
            cc_ctrl    <= load_cc;
4061
            md_ctrl    <= load_md;
4062
            pc_ctrl    <= latch_pc;
4063
            next_state <= single_op_write_state;
4064
          when "0111" =>                -- asr
4065
            left_ctrl  <= md_left;
4066
            right_ctrl <= zero_right;
4067
            alu_ctrl   <= alu_asr8;
4068
            cc_ctrl    <= load_cc;
4069
            md_ctrl    <= load_md;
4070
            pc_ctrl    <= latch_pc;
4071
            next_state <= single_op_write_state;
4072
          when "1000" =>                -- asl
4073
            left_ctrl  <= md_left;
4074
            right_ctrl <= zero_right;
4075
            alu_ctrl   <= alu_asl8;
4076
            cc_ctrl    <= load_cc;
4077
            md_ctrl    <= load_md;
4078
            pc_ctrl    <= latch_pc;
4079
            next_state <= single_op_write_state;
4080
          when "1001" =>                -- rol
4081
            left_ctrl  <= md_left;
4082
            right_ctrl <= zero_right;
4083
            alu_ctrl   <= alu_rol8;
4084
            cc_ctrl    <= load_cc;
4085
            md_ctrl    <= load_md;
4086
            pc_ctrl    <= latch_pc;
4087
            next_state <= single_op_write_state;
4088
          when "1010" =>                -- dec
4089
            left_ctrl  <= md_left;
4090
            right_ctrl <= one_right;
4091
            alu_ctrl   <= alu_dec;
4092
            cc_ctrl    <= load_cc;
4093
            md_ctrl    <= load_md;
4094
            pc_ctrl    <= latch_pc;
4095
            next_state <= single_op_write_state;
4096
          when "1011" =>                -- undefined
4097
            left_ctrl  <= md_left;
4098
            right_ctrl <= zero_right;
4099
            alu_ctrl   <= alu_nop;
4100
            cc_ctrl    <= latch_cc;
4101
            md_ctrl    <= latch_md;
4102
            pc_ctrl    <= latch_pc;
4103
            next_state <= fetch_state;
4104
          when "1100" =>                -- inc
4105
            left_ctrl  <= md_left;
4106
            right_ctrl <= one_right;
4107
            alu_ctrl   <= alu_inc;
4108
            cc_ctrl    <= load_cc;
4109
            md_ctrl    <= load_md;
4110
            pc_ctrl    <= latch_pc;
4111
            next_state <= single_op_write_state;
4112
          when "1101" =>                -- tst
4113
            left_ctrl  <= md_left;
4114
            right_ctrl <= zero_right;
4115
            alu_ctrl   <= alu_st8;
4116
            cc_ctrl    <= load_cc;
4117
            md_ctrl    <= latch_md;
4118
            pc_ctrl    <= latch_pc;
4119
            next_state <= fetch_state;
4120
          when "1110" =>                -- jmp
4121
            left_ctrl  <= md_left;
4122
            right_ctrl <= zero_right;
4123
            alu_ctrl   <= alu_ld16;
4124
            cc_ctrl    <= latch_cc;
4125
            md_ctrl    <= latch_md;
4126
            pc_ctrl    <= load_pc;
4127
            next_state <= fetch_state;
4128
          when "1111" =>                -- clr
4129
            left_ctrl  <= md_left;
4130
            right_ctrl <= zero_right;
4131
            alu_ctrl   <= alu_clr;
4132
            cc_ctrl    <= load_cc;
4133
            md_ctrl    <= load_md;
4134
            pc_ctrl    <= latch_pc;
4135
            next_state <= single_op_write_state;
4136
          when others =>
4137
            left_ctrl  <= md_left;
4138
            right_ctrl <= zero_right;
4139
            alu_ctrl   <= alu_nop;
4140
            cc_ctrl    <= latch_cc;
4141
            md_ctrl    <= latch_md;
4142
            pc_ctrl    <= latch_pc;
4143
            next_state <= fetch_state;
4144
        end case;
4145
      --
4146
      -- single operand 8 bit write
4147
      -- Write low 8 bits of ALU output
4148
      -- EA holds address
4149
      -- MD holds data
4150
      --
4151
      when single_op_write_state =>
4152
        op_ctrl      <= latch_op;
4153
        pre_ctrl     <= latch_pre;
4154
        acca_ctrl    <= latch_acca;
4155
        accb_ctrl    <= latch_accb;
4156
        ix_ctrl      <= latch_ix;
4157
        iy_ctrl      <= latch_iy;
4158
        up_ctrl      <= latch_up;
4159
        sp_ctrl      <= latch_sp;
4160
        pc_ctrl      <= latch_pc;
4161
        md_ctrl      <= latch_md;
4162
        iv_ctrl      <= latch_iv;
4163
        dp_ctrl      <= latch_dp;
4164
        nmi_ctrl     <= latch_nmi;
4165
        ea_ctrl      <= latch_ea;
4166
        -- idle the ALU
4167
        left_ctrl    <= acca_left;
4168
        right_ctrl   <= zero_right;
4169
        alu_ctrl     <= alu_nop;
4170
        cc_ctrl      <= latch_cc;
4171
        -- write ALU low byte output
4172
        addr_ctrl    <= write_ad;
4173
        dout_ctrl    <= md_lo_dout;
4174
        --
4175
        st_ctrl      <= idle_st;
4176
        return_state <= fetch_state;
4177
        next_state   <= fetch_state;
4178
 
4179
      --
4180
      -- here if ea holds address of low byte
4181
      -- read memory location
4182
      --
4183
      when dual_op_read8_state =>
4184
        op_ctrl      <= latch_op;
4185
        pre_ctrl     <= latch_pre;
4186
        acca_ctrl    <= latch_acca;
4187
        accb_ctrl    <= latch_accb;
4188
        ix_ctrl      <= latch_ix;
4189
        iy_ctrl      <= latch_iy;
4190
        up_ctrl      <= latch_up;
4191
        sp_ctrl      <= latch_sp;
4192
        pc_ctrl      <= latch_pc;
4193
        iv_ctrl      <= latch_iv;
4194
        dp_ctrl      <= latch_dp;
4195
        nmi_ctrl     <= latch_nmi;
4196
        left_ctrl    <= ea_left;
4197
                                        -- Leave the ea alone
4198
        right_ctrl   <= zero_right;
4199
        alu_ctrl     <= alu_nop;
4200
        cc_ctrl      <= latch_cc;
4201
        ea_ctrl      <= latch_ea;
4202
        -- read first data byte from ea
4203
        md_ctrl      <= fetch_first_md;
4204
        addr_ctrl    <= read_ad;
4205
        dout_ctrl    <= md_lo_dout;
4206
                                        --
4207
        st_ctrl      <= idle_st;
4208
        return_state <= fetch_state;
4209
        next_state   <= fetch_state;
4210
 
4211
      --
4212
      -- Here to read a 16 bit value into MD
4213
      -- pointed to by the EA register
4214
      -- The first byte is read
4215
      -- and the EA is incremented
4216
      --
4217
      when dual_op_read16_state =>
4218
        op_ctrl      <= latch_op;
4219
        pre_ctrl     <= latch_pre;
4220
        acca_ctrl    <= latch_acca;
4221
        accb_ctrl    <= latch_accb;
4222
        cc_ctrl      <= latch_cc;
4223
        dp_ctrl      <= latch_dp;
4224
        ix_ctrl      <= latch_ix;
4225
        iy_ctrl      <= latch_iy;
4226
        up_ctrl      <= latch_up;
4227
        sp_ctrl      <= latch_sp;
4228
        pc_ctrl      <= latch_pc;
4229
        iv_ctrl      <= latch_iv;
4230
        nmi_ctrl     <= latch_nmi;
4231
                                        -- increment the effective address
4232
        left_ctrl    <= ea_left;
4233
        right_ctrl   <= one_right;
4234
        alu_ctrl     <= alu_add16;
4235
        ea_ctrl      <= load_ea;
4236
                                        -- read the low byte of the 16 bit data
4237
        md_ctrl      <= fetch_first_md;
4238
        addr_ctrl    <= read_ad;
4239
        dout_ctrl    <= md_lo_dout;
4240
                                        --
4241
        st_ctrl      <= idle_st;
4242
        return_state <= fetch_state;
4243
        next_state   <= dual_op_read16_2_state;
4244
 
4245
      --
4246
      -- here to read the second byte
4247
      -- pointed to by EA into MD
4248
      --
4249
      when dual_op_read16_2_state =>
4250
        op_ctrl      <= latch_op;
4251
        pre_ctrl     <= latch_pre;
4252
        acca_ctrl    <= latch_acca;
4253
        accb_ctrl    <= latch_accb;
4254
        cc_ctrl      <= latch_cc;
4255
        dp_ctrl      <= latch_dp;
4256
        ix_ctrl      <= latch_ix;
4257
        iy_ctrl      <= latch_iy;
4258
        up_ctrl      <= latch_up;
4259
        sp_ctrl      <= latch_sp;
4260
        pc_ctrl      <= latch_pc;
4261
        iv_ctrl      <= latch_iv;
4262
        nmi_ctrl     <= latch_nmi;
4263
                                        -- idle the effective address
4264
        left_ctrl    <= ea_left;
4265
        right_ctrl   <= one_right;
4266
        alu_ctrl     <= alu_nop;
4267
        ea_ctrl      <= latch_ea;
4268
                                        -- read the low byte of the 16 bit data
4269
        md_ctrl      <= fetch_next_md;
4270
        addr_ctrl    <= read_ad;
4271
        dout_ctrl    <= md_lo_dout;
4272
                                        --
4273
        st_ctrl      <= idle_st;
4274
        return_state <= fetch_state;
4275
        next_state   <= fetch_state;
4276
 
4277
      --
4278
      -- 16 bit Write state
4279
      -- EA hold address of memory to write to
4280
      -- Advance the effective address in ALU
4281
      -- decode op_code to determine which
4282
      -- register to write
4283
      --
4284
      when dual_op_write16_state =>
4285
        op_ctrl    <= latch_op;
4286
        pre_ctrl   <= latch_pre;
4287
        acca_ctrl  <= latch_acca;
4288
        accb_ctrl  <= latch_accb;
4289
        ix_ctrl    <= latch_ix;
4290
        iy_ctrl    <= latch_iy;
4291
        up_ctrl    <= latch_up;
4292
        sp_ctrl    <= latch_sp;
4293
        pc_ctrl    <= latch_pc;
4294
        md_ctrl    <= latch_md;
4295
        iv_ctrl    <= latch_iv;
4296
        dp_ctrl    <= latch_dp;
4297
        nmi_ctrl   <= latch_nmi;
4298
        -- increment the effective address
4299
        left_ctrl  <= ea_left;
4300
        right_ctrl <= one_right;
4301
        alu_ctrl   <= alu_add16;
4302
        cc_ctrl    <= latch_cc;
4303
        ea_ctrl    <= load_ea;
4304
        -- write the ALU hi byte at ea
4305
        addr_ctrl  <= write_ad;
4306
        if op_code(6) = '0' then
4307
          case op_code(3 downto 0) is
4308
            when "1111" =>              -- stx / sty
4309
              case pre_code is
4310
                when "00010000" =>  -- page 2 -- sty
4311
                  dout_ctrl <= iy_hi_dout;
4312
                when others =>  -- page 1 -- stx
4313
                  dout_ctrl <= ix_hi_dout;
4314
              end case;
4315
            when others =>
4316
              dout_ctrl <= md_hi_dout;
4317
          end case;
4318
        else
4319
          case op_code(3 downto 0) is
4320
            when "1101" =>              -- std
4321
              dout_ctrl <= acca_dout;   -- acca is high byte of ACCD
4322
            when "1111" =>              -- stu / sts
4323
              case pre_code is
4324
                when "00010000" =>  -- page 2 -- sts
4325
                  dout_ctrl <= sp_hi_dout;
4326
                when others =>  -- page 1 -- stu
4327
                  dout_ctrl <= up_hi_dout;
4328
              end case;
4329
            when others =>
4330
              dout_ctrl <= md_hi_dout;
4331
          end case;
4332
        end if;
4333
        st_ctrl      <= idle_st;
4334
        return_state <= fetch_state;
4335
        next_state   <= dual_op_write8_state;
4336
 
4337
      --
4338
      -- Dual operand 8 bit write
4339
      -- Write 8 bit accumulator
4340
      -- or low byte of 16 bit register
4341
      -- EA holds address
4342
      -- decode opcode to determine
4343
      -- which register to apply to the bus
4344
      -- Also set the condition codes here
4345
      --
4346
      when dual_op_write8_state =>
4347
        op_ctrl    <= latch_op;
4348
        pre_ctrl   <= latch_pre;
4349
        acca_ctrl  <= latch_acca;
4350
        accb_ctrl  <= latch_accb;
4351
        ix_ctrl    <= latch_ix;
4352
        iy_ctrl    <= latch_iy;
4353
        up_ctrl    <= latch_up;
4354
        sp_ctrl    <= latch_sp;
4355
        pc_ctrl    <= latch_pc;
4356
        iv_ctrl    <= latch_iv;
4357
        dp_ctrl    <= latch_dp;
4358
        nmi_ctrl   <= latch_nmi;
4359
        md_ctrl    <= latch_md;
4360
        -- idle ALU
4361
        left_ctrl  <= ea_left;
4362
        right_ctrl <= zero_right;
4363
        alu_ctrl   <= alu_nop;
4364
        cc_ctrl    <= latch_cc;
4365
        ea_ctrl    <= latch_ea;
4366
        --
4367
        if op_code(6) = '0' then        -- '0' = acca line
4368
          case op_code(3 downto 0) is
4369
            when "0111" =>              -- sta
4370
              dout_ctrl <= acca_dout;
4371
            when "1111" =>              -- stx / sty
4372
              case pre_code is
4373
                when "00010000" =>  -- page 2 -- sty
4374
                  dout_ctrl <= iy_lo_dout;
4375
                when others =>  -- page 1 -- stx
4376
                  dout_ctrl <= ix_lo_dout;
4377
              end case;
4378
            when others =>
4379
              dout_ctrl <= md_lo_dout;
4380
          end case;
4381
        else                            -- '1' = accb line
4382
          case op_code(3 downto 0) is
4383
            when "0111" =>              -- stb
4384
              dout_ctrl <= accb_dout;
4385
            when "1101" =>              -- std
4386
              dout_ctrl <= accb_dout;   -- accb is low byte of accd
4387
            when "1111" =>              -- stu / sts
4388
              case pre_code is
4389
                when "00010000" =>  -- page 2 -- sts
4390
                  dout_ctrl <= sp_lo_dout;
4391
                when others =>  -- page 1 -- stu
4392
                  dout_ctrl <= up_lo_dout;
4393
              end case;
4394
            when others =>
4395
              dout_ctrl <= md_lo_dout;
4396
          end case;
4397
        end if;
4398
        -- write ALU low byte output
4399
        addr_ctrl    <= write_ad;
4400
        --
4401
        st_ctrl      <= idle_st;
4402
        return_state <= fetch_state;
4403
        next_state   <= fetch_state;
4404
 
4405
      --
4406
      -- 16 bit immediate addressing mode
4407
      --
4408
      when imm16_state =>
4409
        op_ctrl      <= latch_op;
4410
        pre_ctrl     <= latch_pre;
4411
        acca_ctrl    <= latch_acca;
4412
        accb_ctrl    <= latch_accb;
4413
        cc_ctrl      <= latch_cc;
4414
        dp_ctrl      <= latch_dp;
4415
                                        --
4416
        ix_ctrl      <= latch_ix;
4417
        iy_ctrl      <= latch_iy;
4418
        up_ctrl      <= latch_up;
4419
        sp_ctrl      <= latch_sp;
4420
                                        --
4421
        iv_ctrl      <= latch_iv;
4422
        nmi_ctrl     <= latch_nmi;
4423
        ea_ctrl      <= latch_ea;
4424
        -- increment pc
4425
        left_ctrl    <= pc_left;
4426
        right_ctrl   <= zero_right;
4427
        alu_ctrl     <= alu_nop;
4428
        pc_ctrl      <= incr_pc;
4429
        -- fetch next immediate byte
4430
        md_ctrl      <= fetch_next_md;
4431
        addr_ctrl    <= fetch_ad;
4432
        dout_ctrl    <= md_lo_dout;
4433
        -- return to caller
4434
        st_ctrl      <= pull_st;
4435
        return_state <= fetch_state;
4436
        next_state   <= saved_state;
4437
 
4438
      --
4439
      -- md & ea holds 8 bit index offset
4440
      -- calculate the effective memory address
4441
      -- using the alu
4442
      --
4443
      when indexed_state =>
4444
        op_ctrl   <= latch_op;
4445
        pre_ctrl  <= latch_pre;
4446
        acca_ctrl <= latch_acca;
4447
        accb_ctrl <= latch_accb;
4448
        iv_ctrl   <= latch_iv;
4449
        dp_ctrl   <= latch_dp;
4450
        nmi_ctrl  <= latch_nmi;
4451
        dout_ctrl <= md_lo_dout;
4452
        --
4453
        -- decode indexing mode
4454
        --
4455
        if md(7) = '0' then
4456
          ix_ctrl <= latch_ix;
4457
          iy_ctrl <= latch_iy;
4458
          up_ctrl <= latch_up;
4459
          sp_ctrl <= latch_sp;
4460
          case md(6 downto 5) is
4461
            when "00" =>
4462
              left_ctrl <= ix_left;
4463
            when "01" =>
4464
              left_ctrl <= iy_left;
4465
            when "10" =>
4466
              left_ctrl <= up_left;
4467
            when others =>
4468
                                        -- when "11" =>
4469
              left_ctrl <= sp_left;
4470
          end case;
4471
          right_ctrl   <= md_sign5_right;
4472
          alu_ctrl     <= alu_add16;
4473
          cc_ctrl      <= latch_cc;
4474
          ea_ctrl      <= load_ea;
4475
                                        --
4476
          md_ctrl      <= latch_md;
4477
          addr_ctrl    <= idle_ad;
4478
          pc_ctrl      <= latch_pc;
4479
                                        --
4480
          st_ctrl      <= pull_st;
4481
          return_state <= fetch_state;
4482
          next_state   <= saved_state;
4483
 
4484
        else
4485
          case md(3 downto 0) is
4486
            when "0000" =>              -- ,R+
4487
              ix_ctrl <= latch_ix;
4488
              iy_ctrl <= latch_iy;
4489
              up_ctrl <= latch_up;
4490
              sp_ctrl <= latch_sp;
4491
              case md(6 downto 5) is
4492
                when "00" =>
4493
                  left_ctrl <= ix_left;
4494
                when "01" =>
4495
                  left_ctrl <= iy_left;
4496
                when "10" =>
4497
                  left_ctrl <= up_left;
4498
                when others =>
4499
                  left_ctrl <= sp_left;
4500
              end case;
4501
                                        --
4502
              right_ctrl   <= zero_right;
4503
              alu_ctrl     <= alu_st16;
4504
              cc_ctrl      <= latch_cc;
4505
              ea_ctrl      <= load_ea;
4506
                                        --
4507
              md_ctrl      <= latch_md;
4508
              addr_ctrl    <= idle_ad;
4509
              pc_ctrl      <= latch_pc;
4510
                                        --
4511
              st_ctrl      <= idle_st;
4512
              return_state <= fetch_state;
4513
              next_state   <= postincr1_state;
4514
 
4515
            when "0001" =>              -- ,R++
4516
              ix_ctrl <= latch_ix;
4517
              iy_ctrl <= latch_iy;
4518
              up_ctrl <= latch_up;
4519
              sp_ctrl <= latch_sp;
4520
              case md(6 downto 5) is
4521
                when "00" =>
4522
                  left_ctrl <= ix_left;
4523
                when "01" =>
4524
                  left_ctrl <= iy_left;
4525
                when "10" =>
4526
                  left_ctrl <= up_left;
4527
                when others =>
4528
                                        -- when "11" =>
4529
                  left_ctrl <= sp_left;
4530
              end case;
4531
              right_ctrl   <= zero_right;
4532
              alu_ctrl     <= alu_st16;
4533
              cc_ctrl      <= latch_cc;
4534
              ea_ctrl      <= load_ea;
4535
                                        --
4536
              md_ctrl      <= latch_md;
4537
              addr_ctrl    <= idle_ad;
4538
              pc_ctrl      <= latch_pc;
4539
                                        --
4540
              st_ctrl      <= idle_st;
4541
              return_state <= fetch_state;
4542
              next_state   <= postincr2_state;
4543
 
4544
            when "0010" =>              -- ,-R
4545
              case md(6 downto 5) is
4546
                when "00" =>
4547
                  left_ctrl <= ix_left;
4548
                  ix_ctrl   <= load_ix;
4549
                  iy_ctrl   <= latch_iy;
4550
                  up_ctrl   <= latch_up;
4551
                  sp_ctrl   <= latch_sp;
4552
                when "01" =>
4553
                  left_ctrl <= iy_left;
4554
                  ix_ctrl   <= latch_ix;
4555
                  iy_ctrl   <= load_iy;
4556
                  up_ctrl   <= latch_up;
4557
                  sp_ctrl   <= latch_sp;
4558
                when "10" =>
4559
                  left_ctrl <= up_left;
4560
                  ix_ctrl   <= latch_ix;
4561
                  iy_ctrl   <= latch_iy;
4562
                  up_ctrl   <= load_up;
4563
                  sp_ctrl   <= latch_sp;
4564
                when others =>
4565
                                        -- when "11" =>
4566
                  left_ctrl <= sp_left;
4567
                  ix_ctrl   <= latch_ix;
4568
                  iy_ctrl   <= latch_iy;
4569
                  up_ctrl   <= latch_up;
4570
                  sp_ctrl   <= load_sp;
4571
              end case;
4572
              right_ctrl   <= one_right;
4573
              alu_ctrl     <= alu_sub16;
4574
              cc_ctrl      <= latch_cc;
4575
              ea_ctrl      <= load_ea;
4576
                                        --
4577
              md_ctrl      <= latch_md;
4578
              addr_ctrl    <= idle_ad;
4579
              pc_ctrl      <= latch_pc;
4580
                                        --
4581
              st_ctrl      <= pull_st;
4582
              return_state <= fetch_state;
4583
              next_state   <= saved_state;
4584
 
4585
            when "0011" =>  -- ,--R
4586
              case md(6 downto 5) is
4587
                when "00" =>
4588
                  left_ctrl <= ix_left;
4589
                  ix_ctrl   <= load_ix;
4590
                  iy_ctrl   <= latch_iy;
4591
                  up_ctrl   <= latch_up;
4592
                  sp_ctrl   <= latch_sp;
4593
                when "01" =>
4594
                  left_ctrl <= iy_left;
4595
                  ix_ctrl   <= latch_ix;
4596
                  iy_ctrl   <= load_iy;
4597
                  up_ctrl   <= latch_up;
4598
                  sp_ctrl   <= latch_sp;
4599
                when "10" =>
4600
                  left_ctrl <= up_left;
4601
                  ix_ctrl   <= latch_ix;
4602
                  iy_ctrl   <= latch_iy;
4603
                  up_ctrl   <= load_up;
4604
                  sp_ctrl   <= latch_sp;
4605
                when others =>
4606
                                        -- when "11" =>
4607
                  left_ctrl <= sp_left;
4608
                  ix_ctrl   <= latch_ix;
4609
                  iy_ctrl   <= latch_iy;
4610
                  up_ctrl   <= latch_up;
4611
                  sp_ctrl   <= load_sp;
4612
              end case;
4613
              right_ctrl <= two_right;
4614
              alu_ctrl   <= alu_sub16;
4615
              cc_ctrl    <= latch_cc;
4616
              ea_ctrl    <= load_ea;
4617
                                        --
4618
              md_ctrl    <= latch_md;
4619
              addr_ctrl  <= idle_ad;
4620
              pc_ctrl    <= latch_pc;
4621
                                        --
4622
              if md(4) = '0' then
4623
                st_ctrl      <= pull_st;
4624
                return_state <= fetch_state;
4625
                next_state   <= saved_state;
4626
              else
4627
                st_ctrl      <= idle_st;
4628
                return_state <= fetch_state;
4629
                next_state   <= indirect_state;
4630
              end if;
4631
 
4632
            when "0100" =>              -- ,R (zero offset)
4633
              ix_ctrl <= latch_ix;
4634
              iy_ctrl <= latch_iy;
4635
              up_ctrl <= latch_up;
4636
              sp_ctrl <= latch_sp;
4637
              case md(6 downto 5) is
4638
                when "00" =>
4639
                  left_ctrl <= ix_left;
4640
                when "01" =>
4641
                  left_ctrl <= iy_left;
4642
                when "10" =>
4643
                  left_ctrl <= up_left;
4644
                when others =>
4645
                                        -- when "11" =>
4646
                  left_ctrl <= sp_left;
4647
              end case;
4648
              right_ctrl <= zero_right;
4649
              alu_ctrl   <= alu_st16;
4650
              cc_ctrl    <= latch_cc;
4651
              ea_ctrl    <= load_ea;
4652
                                        --
4653
              md_ctrl    <= latch_md;
4654
              addr_ctrl  <= idle_ad;
4655
              pc_ctrl    <= latch_pc;
4656
                                        --
4657
              if md(4) = '0' then
4658
                st_ctrl      <= pull_st;
4659
                return_state <= fetch_state;
4660
                next_state   <= saved_state;
4661
              else
4662
                st_ctrl      <= idle_st;
4663
                return_state <= fetch_state;
4664
                next_state   <= indirect_state;
4665
              end if;
4666
 
4667
            when "0101" =>              -- ACCB,R
4668
              ix_ctrl <= latch_ix;
4669
              iy_ctrl <= latch_iy;
4670
              up_ctrl <= latch_up;
4671
              sp_ctrl <= latch_sp;
4672
              case md(6 downto 5) is
4673
                when "00" =>
4674
                  left_ctrl <= ix_left;
4675
                when "01" =>
4676
                  left_ctrl <= iy_left;
4677
                when "10" =>
4678
                  left_ctrl <= up_left;
4679
                when others =>
4680
                                        -- when "11" =>
4681
                  left_ctrl <= sp_left;
4682
              end case;
4683
              right_ctrl <= accb_right;
4684
              alu_ctrl   <= alu_add16;
4685
              cc_ctrl    <= latch_cc;
4686
              ea_ctrl    <= load_ea;
4687
                                        --
4688
              md_ctrl    <= latch_md;
4689
              addr_ctrl  <= idle_ad;
4690
              pc_ctrl    <= latch_pc;
4691
                                        --
4692
              if md(4) = '0' then
4693
                st_ctrl      <= pull_st;
4694
                return_state <= fetch_state;
4695
                next_state   <= saved_state;
4696
              else
4697
                st_ctrl      <= idle_st;
4698
                return_state <= fetch_state;
4699
                next_state   <= indirect_state;
4700
              end if;
4701
 
4702
            when "0110" =>              -- ACCA,R
4703
              ix_ctrl <= latch_ix;
4704
              iy_ctrl <= latch_iy;
4705
              up_ctrl <= latch_up;
4706
              sp_ctrl <= latch_sp;
4707
              case md(6 downto 5) is
4708
                when "00" =>
4709
                  left_ctrl <= ix_left;
4710
                when "01" =>
4711
                  left_ctrl <= iy_left;
4712
                when "10" =>
4713
                  left_ctrl <= up_left;
4714
                when others =>
4715
                                        -- when "11" =>
4716
                  left_ctrl <= sp_left;
4717
              end case;
4718
              right_ctrl <= acca_right;
4719
              alu_ctrl   <= alu_add16;
4720
              cc_ctrl    <= latch_cc;
4721
              ea_ctrl    <= load_ea;
4722
                                        --
4723
              md_ctrl    <= latch_md;
4724
              addr_ctrl  <= idle_ad;
4725
              pc_ctrl    <= latch_pc;
4726
                                        --
4727
              if md(4) = '0' then
4728
                st_ctrl      <= pull_st;
4729
                return_state <= fetch_state;
4730
                next_state   <= saved_state;
4731
              else
4732
                st_ctrl      <= idle_st;
4733
                return_state <= fetch_state;
4734
                next_state   <= indirect_state;
4735
              end if;
4736
 
4737
            when "0111" =>              -- undefined
4738
              ix_ctrl <= latch_ix;
4739
              iy_ctrl <= latch_iy;
4740
              up_ctrl <= latch_up;
4741
              sp_ctrl <= latch_sp;
4742
              case md(6 downto 5) is
4743
                when "00" =>
4744
                  left_ctrl <= ix_left;
4745
                when "01" =>
4746
                  left_ctrl <= iy_left;
4747
                when "10" =>
4748
                  left_ctrl <= up_left;
4749
                when others =>
4750
                                        -- when "11" =>
4751
                  left_ctrl <= sp_left;
4752
              end case;
4753
              right_ctrl <= zero_right;
4754
              alu_ctrl   <= alu_nop;
4755
              cc_ctrl    <= latch_cc;
4756
              ea_ctrl    <= latch_ea;
4757
                                        --
4758
              md_ctrl    <= latch_md;
4759
              addr_ctrl  <= idle_ad;
4760
              pc_ctrl    <= latch_pc;
4761
                                        --
4762
              if md(4) = '0' then
4763
                st_ctrl      <= pull_st;
4764
                return_state <= fetch_state;
4765
                next_state   <= saved_state;
4766
              else
4767
                st_ctrl      <= idle_st;
4768
                return_state <= fetch_state;
4769
                next_state   <= indirect_state;
4770
              end if;
4771
 
4772
            when "1000" =>                     -- offset8,R
4773
              ix_ctrl      <= latch_ix;
4774
              iy_ctrl      <= latch_iy;
4775
              up_ctrl      <= latch_up;
4776
              sp_ctrl      <= latch_sp;
4777
                                               --
4778
              left_ctrl    <= pc_left;
4779
              right_ctrl   <= zero_right;
4780
              alu_ctrl     <= alu_nop;
4781
              cc_ctrl      <= latch_cc;
4782
              ea_ctrl      <= latch_ea;
4783
                                               --
4784
              md_ctrl      <= fetch_first_md;  -- pick up 8 bit offset
4785
              addr_ctrl    <= fetch_ad;
4786
              pc_ctrl      <= incr_pc;
4787
                                               --
4788
              st_ctrl      <= idle_st;
4789
              return_state <= fetch_state;
4790
              next_state   <= index8_state;
4791
 
4792
            when "1001" =>              -- offset16,R
4793
              ix_ctrl      <= latch_ix;
4794
              iy_ctrl      <= latch_iy;
4795
              up_ctrl      <= latch_up;
4796
              sp_ctrl      <= latch_sp;
4797
                                        --
4798
              left_ctrl    <= pc_left;
4799
              right_ctrl   <= zero_right;
4800
              alu_ctrl     <= alu_nop;
4801
              cc_ctrl      <= latch_cc;
4802
              ea_ctrl      <= latch_ea;
4803
                                        --
4804
              md_ctrl      <= fetch_first_md;  -- pick up first byte of 16 bit offset
4805
              addr_ctrl    <= fetch_ad;
4806
              pc_ctrl      <= incr_pc;
4807
                                        --
4808
              st_ctrl      <= idle_st;
4809
              return_state <= fetch_state;
4810
              next_state   <= index16_state;
4811
 
4812
            when "1010" =>              -- undefined
4813
              ix_ctrl <= latch_ix;
4814
              iy_ctrl <= latch_iy;
4815
              up_ctrl <= latch_up;
4816
              sp_ctrl <= latch_sp;
4817
              case md(6 downto 5) is
4818
                when "00" =>
4819
                  left_ctrl <= ix_left;
4820
                when "01" =>
4821
                  left_ctrl <= iy_left;
4822
                when "10" =>
4823
                  left_ctrl <= up_left;
4824
                when others =>
4825
                                        -- when "11" =>
4826
                  left_ctrl <= sp_left;
4827
              end case;
4828
              right_ctrl <= zero_right;
4829
              alu_ctrl   <= alu_nop;
4830
              cc_ctrl    <= latch_cc;
4831
              ea_ctrl    <= latch_ea;
4832
                                        --
4833
              md_ctrl    <= latch_md;
4834
              addr_ctrl  <= idle_ad;
4835
              pc_ctrl    <= latch_pc;
4836
                                        --
4837
              if md(4) = '0' then
4838
                st_ctrl      <= pull_st;
4839
                return_state <= fetch_state;
4840
                next_state   <= saved_state;
4841
              else
4842
                st_ctrl      <= idle_st;
4843
                return_state <= fetch_state;
4844
                next_state   <= indirect_state;
4845
              end if;
4846
 
4847
            when "1011" =>              -- ACCD,R
4848
              ix_ctrl <= latch_ix;
4849
              iy_ctrl <= latch_iy;
4850
              up_ctrl <= latch_up;
4851
              sp_ctrl <= latch_sp;
4852
              case md(6 downto 5) is
4853
                when "00" =>
4854
                  left_ctrl <= ix_left;
4855
                when "01" =>
4856
                  left_ctrl <= iy_left;
4857
                when "10" =>
4858
                  left_ctrl <= up_left;
4859
                when others =>
4860
                                        -- when "11" =>
4861
                  left_ctrl <= sp_left;
4862
              end case;
4863
              right_ctrl <= accd_right;
4864
              alu_ctrl   <= alu_add16;
4865
              cc_ctrl    <= latch_cc;
4866
              ea_ctrl    <= load_ea;
4867
                                        --
4868
              md_ctrl    <= latch_md;
4869
              addr_ctrl  <= idle_ad;
4870
              pc_ctrl    <= latch_pc;
4871
                                        --
4872
              if md(4) = '0' then
4873
                st_ctrl      <= pull_st;
4874
                return_state <= fetch_state;
4875
                next_state   <= saved_state;
4876
              else
4877
                st_ctrl      <= idle_st;
4878
                return_state <= fetch_state;
4879
                next_state   <= indirect_state;
4880
              end if;
4881
 
4882
            when "1100" =>              -- offset8,PC
4883
              ix_ctrl      <= latch_ix;
4884
              iy_ctrl      <= latch_iy;
4885
              up_ctrl      <= latch_up;
4886
              sp_ctrl      <= latch_sp;
4887
                                        --
4888
              left_ctrl    <= pc_left;
4889
              right_ctrl   <= zero_right;
4890
              alu_ctrl     <= alu_nop;
4891
              cc_ctrl      <= latch_cc;
4892
              ea_ctrl      <= latch_ea;
4893
                                        -- fetch 8 bit offset
4894
              md_ctrl      <= fetch_first_md;
4895
              addr_ctrl    <= fetch_ad;
4896
              pc_ctrl      <= incr_pc;
4897
                                        --
4898
              st_ctrl      <= idle_st;
4899
              return_state <= fetch_state;
4900
              next_state   <= pcrel8_state;
4901
 
4902
            when "1101" =>              -- offset16,PC
4903
              ix_ctrl      <= latch_ix;
4904
              iy_ctrl      <= latch_iy;
4905
              up_ctrl      <= latch_up;
4906
              sp_ctrl      <= latch_sp;
4907
                                        --
4908
              left_ctrl    <= pc_left;
4909
              right_ctrl   <= zero_right;
4910
              alu_ctrl     <= alu_nop;
4911
              cc_ctrl      <= latch_cc;
4912
              ea_ctrl      <= latch_ea;
4913
                                        -- fetch offset
4914
              md_ctrl      <= fetch_first_md;
4915
              addr_ctrl    <= fetch_ad;
4916
              pc_ctrl      <= incr_pc;
4917
                                        --
4918
              st_ctrl      <= idle_st;
4919
              return_state <= fetch_state;
4920
              next_state   <= pcrel16_state;
4921
 
4922
            when "1110" =>              -- undefined
4923
              ix_ctrl <= latch_ix;
4924
              iy_ctrl <= latch_iy;
4925
              up_ctrl <= latch_up;
4926
              sp_ctrl <= latch_sp;
4927
              case md(6 downto 5) is
4928
                when "00" =>
4929
                  left_ctrl <= ix_left;
4930
                when "01" =>
4931
                  left_ctrl <= iy_left;
4932
                when "10" =>
4933
                  left_ctrl <= up_left;
4934
                when others =>
4935
                                        -- when "11" =>
4936
                  left_ctrl <= sp_left;
4937
              end case;
4938
              right_ctrl <= zero_right;
4939
              alu_ctrl   <= alu_nop;
4940
              cc_ctrl    <= latch_cc;
4941
              ea_ctrl    <= load_ea;
4942
                                        --
4943
              md_ctrl    <= latch_md;
4944
              addr_ctrl  <= idle_ad;
4945
              pc_ctrl    <= latch_pc;
4946
                                        --
4947
              if md(4) = '0' then
4948
                st_ctrl      <= pull_st;
4949
                return_state <= fetch_state;
4950
                next_state   <= saved_state;
4951
              else
4952
                st_ctrl      <= idle_st;
4953
                return_state <= fetch_state;
4954
                next_state   <= indirect_state;
4955
              end if;
4956
 
4957
            when others =>  -- when "1111" =>     -- [,address]
4958
              ix_ctrl      <= latch_ix;
4959
              iy_ctrl      <= latch_iy;
4960
              up_ctrl      <= latch_up;
4961
              sp_ctrl      <= latch_sp;
4962
                                        -- idle ALU
4963
              left_ctrl    <= pc_left;
4964
              right_ctrl   <= zero_right;
4965
              alu_ctrl     <= alu_nop;
4966
              cc_ctrl      <= latch_cc;
4967
              ea_ctrl      <= latch_ea;
4968
                                        -- advance PC to pick up address
4969
              md_ctrl      <= fetch_first_md;
4970
              addr_ctrl    <= fetch_ad;
4971
              pc_ctrl      <= incr_pc;
4972
                                        --
4973
              st_ctrl      <= idle_st;
4974
              return_state <= fetch_state;
4975
              next_state   <= indexaddr_state;
4976
          end case;
4977
        end if;
4978
 
4979
        -- load index register with ea plus one
4980
      when postincr1_state =>
4981
        op_ctrl    <= latch_op;
4982
        pre_ctrl   <= latch_pre;
4983
        acca_ctrl  <= latch_acca;
4984
        accb_ctrl  <= latch_accb;
4985
        cc_ctrl    <= latch_cc;
4986
        dp_ctrl    <= latch_dp;
4987
        iv_ctrl    <= latch_iv;
4988
        nmi_ctrl   <= latch_nmi;
4989
        pc_ctrl    <= latch_pc;
4990
        md_ctrl    <= latch_md;
4991
        ea_ctrl    <= latch_ea;
4992
        --
4993
        left_ctrl  <= ea_left;
4994
        right_ctrl <= one_right;
4995
        alu_ctrl   <= alu_add16;
4996
        case md(6 downto 5) is
4997
          when "00" =>
4998
            ix_ctrl <= load_ix;
4999
            iy_ctrl <= latch_iy;
5000
            up_ctrl <= latch_up;
5001
            sp_ctrl <= latch_sp;
5002
          when "01" =>
5003
            ix_ctrl <= latch_ix;
5004
            iy_ctrl <= load_iy;
5005
            up_ctrl <= latch_up;
5006
            sp_ctrl <= latch_sp;
5007
          when "10" =>
5008
            ix_ctrl <= latch_ix;
5009
            iy_ctrl <= latch_iy;
5010
            up_ctrl <= load_up;
5011
            sp_ctrl <= latch_sp;
5012
          when others =>         -- when "11" =>
5013
            ix_ctrl <= latch_ix;
5014
            iy_ctrl <= latch_iy;
5015
            up_ctrl <= latch_up;
5016
            sp_ctrl <= load_sp;
5017
        end case;
5018
        addr_ctrl <= idle_ad;
5019
        dout_ctrl <= md_lo_dout;
5020
        -- return to previous state
5021
        if md(4) = '0' then
5022
          st_ctrl      <= pull_st;
5023
          return_state <= fetch_state;
5024
          next_state   <= saved_state;
5025
        else
5026
          st_ctrl      <= idle_st;
5027
          return_state <= fetch_state;
5028
          next_state   <= indirect_state;
5029
        end if;
5030
 
5031
        -- load index register with ea plus two
5032
      when postincr2_state =>
5033
        op_ctrl    <= latch_op;
5034
        pre_ctrl   <= latch_pre;
5035
        acca_ctrl  <= latch_acca;
5036
        accb_ctrl  <= latch_accb;
5037
        cc_ctrl    <= latch_cc;
5038
        dp_ctrl    <= latch_dp;
5039
        iv_ctrl    <= latch_iv;
5040
        nmi_ctrl   <= latch_nmi;
5041
        pc_ctrl    <= latch_pc;
5042
        md_ctrl    <= latch_md;
5043
        ea_ctrl    <= latch_ea;
5044
        -- increment register by two (address)
5045
        left_ctrl  <= ea_left;
5046
        right_ctrl <= two_right;
5047
        alu_ctrl   <= alu_add16;
5048
        case md(6 downto 5) is
5049
          when "00" =>
5050
            ix_ctrl <= load_ix;
5051
            iy_ctrl <= latch_iy;
5052
            up_ctrl <= latch_up;
5053
            sp_ctrl <= latch_sp;
5054
          when "01" =>
5055
            ix_ctrl <= latch_ix;
5056
            iy_ctrl <= load_iy;
5057
            up_ctrl <= latch_up;
5058
            sp_ctrl <= latch_sp;
5059
          when "10" =>
5060
            ix_ctrl <= latch_ix;
5061
            iy_ctrl <= latch_iy;
5062
            up_ctrl <= load_up;
5063
            sp_ctrl <= latch_sp;
5064
          when others =>
5065
            -- when "11" =>
5066
            ix_ctrl <= latch_ix;
5067
            iy_ctrl <= latch_iy;
5068
            up_ctrl <= latch_up;
5069
            sp_ctrl <= load_sp;
5070
        end case;
5071
        addr_ctrl <= idle_ad;
5072
        dout_ctrl <= md_lo_dout;
5073
        -- return to previous state
5074
        if md(4) = '0' then
5075
          st_ctrl      <= pull_st;
5076
          return_state <= fetch_state;
5077
          next_state   <= saved_state;
5078
        else
5079
          st_ctrl      <= idle_st;
5080
          return_state <= fetch_state;
5081
          next_state   <= indirect_state;
5082
        end if;
5083
      --
5084
      -- ea = index register + md (8 bit signed offset)
5085
      -- ea holds post byte
5086
      --
5087
      when index8_state =>
5088
        op_ctrl   <= latch_op;
5089
        pre_ctrl  <= latch_pre;
5090
        acca_ctrl <= latch_acca;
5091
        accb_ctrl <= latch_accb;
5092
        cc_ctrl   <= latch_cc;
5093
        dp_ctrl   <= latch_dp;
5094
        ix_ctrl   <= latch_ix;
5095
        iy_ctrl   <= latch_iy;
5096
        up_ctrl   <= latch_up;
5097
        sp_ctrl   <= latch_sp;
5098
        iv_ctrl   <= latch_iv;
5099
        nmi_ctrl  <= latch_nmi;
5100
        pc_ctrl   <= latch_pc;
5101
        md_ctrl   <= latch_md;
5102
        case ea(6 downto 5) is
5103
          when "00" =>
5104
            left_ctrl <= ix_left;
5105
          when "01" =>
5106
            left_ctrl <= iy_left;
5107
          when "10" =>
5108
            left_ctrl <= up_left;
5109
          when others =>
5110
            -- when "11" =>
5111
            left_ctrl <= sp_left;
5112
        end case;
5113
        -- ea = index reg + md
5114
        right_ctrl <= md_sign8_right;
5115
        alu_ctrl   <= alu_add16;
5116
        ea_ctrl    <= load_ea;
5117
        -- idle bus
5118
        addr_ctrl  <= idle_ad;
5119
        dout_ctrl  <= md_lo_dout;
5120
        -- return to previous state
5121
        if ea(4) = '0' then
5122
          st_ctrl      <= pull_st;
5123
          return_state <= fetch_state;
5124
          next_state   <= saved_state;
5125
        else
5126
          st_ctrl      <= idle_st;
5127
          return_state <= fetch_state;
5128
          next_state   <= indirect_state;
5129
        end if;
5130
 
5131
        -- fetch low byte of 16 bit indexed offset
5132
      when index16_state =>
5133
        op_ctrl      <= latch_op;
5134
        pre_ctrl     <= latch_pre;
5135
        acca_ctrl    <= latch_acca;
5136
        accb_ctrl    <= latch_accb;
5137
        cc_ctrl      <= latch_cc;
5138
        dp_ctrl      <= latch_dp;
5139
        ix_ctrl      <= latch_ix;
5140
        iy_ctrl      <= latch_iy;
5141
        up_ctrl      <= latch_up;
5142
        sp_ctrl      <= latch_sp;
5143
        iv_ctrl      <= latch_iv;
5144
        nmi_ctrl     <= latch_nmi;
5145
        -- advance pc
5146
        left_ctrl    <= pc_left;
5147
        right_ctrl   <= one_right;
5148
        alu_ctrl     <= alu_add16;
5149
        pc_ctrl      <= incr_pc;
5150
        -- fetch low byte
5151
        ea_ctrl      <= latch_ea;
5152
        md_ctrl      <= fetch_next_md;
5153
        addr_ctrl    <= fetch_ad;
5154
        dout_ctrl    <= md_lo_dout;
5155
        --
5156
        st_ctrl      <= idle_st;
5157
        return_state <= fetch_state;
5158
        next_state   <= index16_2_state;
5159
 
5160
      -- ea = index register + md (16 bit offset)
5161
      -- ea holds post byte
5162
      when index16_2_state =>
5163
        op_ctrl   <= latch_op;
5164
        pre_ctrl  <= latch_pre;
5165
        acca_ctrl <= latch_acca;
5166
        accb_ctrl <= latch_accb;
5167
        cc_ctrl   <= latch_cc;
5168
        dp_ctrl   <= latch_dp;
5169
        ix_ctrl   <= latch_ix;
5170
        iy_ctrl   <= latch_iy;
5171
        up_ctrl   <= latch_up;
5172
        sp_ctrl   <= latch_sp;
5173
        iv_ctrl   <= latch_iv;
5174
        nmi_ctrl  <= latch_nmi;
5175
        pc_ctrl   <= latch_pc;
5176
        md_ctrl   <= latch_md;
5177
        case ea(6 downto 5) is
5178
          when "00" =>
5179
            left_ctrl <= ix_left;
5180
          when "01" =>
5181
            left_ctrl <= iy_left;
5182
          when "10" =>
5183
            left_ctrl <= up_left;
5184
          when others =>
5185
            -- when "11" =>
5186
            left_ctrl <= sp_left;
5187
        end case;
5188
        -- ea = index reg + md
5189
        right_ctrl <= md_right;
5190
        alu_ctrl   <= alu_add16;
5191
        ea_ctrl    <= load_ea;
5192
        -- idle bus
5193
        addr_ctrl  <= idle_ad;
5194
        dout_ctrl  <= md_lo_dout;
5195
        -- return to previous state
5196
        if ea(4) = '0' then
5197
          st_ctrl      <= pull_st;
5198
          return_state <= fetch_state;
5199
          next_state   <= saved_state;
5200
        else
5201
          st_ctrl      <= idle_st;
5202
          return_state <= fetch_state;
5203
          next_state   <= indirect_state;
5204
        end if;
5205
      --
5206
      -- pc relative with 8 bit signed offest
5207
      -- md holds signed offset
5208
      --
5209
      when pcrel8_state =>
5210
        op_ctrl    <= latch_op;
5211
        pre_ctrl   <= latch_pre;
5212
        acca_ctrl  <= latch_acca;
5213
        accb_ctrl  <= latch_accb;
5214
        cc_ctrl    <= latch_cc;
5215
        dp_ctrl    <= latch_dp;
5216
        ix_ctrl    <= latch_ix;
5217
        iy_ctrl    <= latch_iy;
5218
        up_ctrl    <= latch_up;
5219
        sp_ctrl    <= latch_sp;
5220
        iv_ctrl    <= latch_iv;
5221
        nmi_ctrl   <= latch_nmi;
5222
        pc_ctrl    <= latch_pc;
5223
        md_ctrl    <= latch_md;
5224
        -- ea = pc + signed md
5225
        left_ctrl  <= pc_left;
5226
        right_ctrl <= md_sign8_right;
5227
        alu_ctrl   <= alu_add16;
5228
        ea_ctrl    <= load_ea;
5229
        -- idle bus
5230
        addr_ctrl  <= idle_ad;
5231
        dout_ctrl  <= md_lo_dout;
5232
        -- return to previous state
5233
        if ea(4) = '0' then
5234
          st_ctrl      <= pull_st;
5235
          return_state <= fetch_state;
5236
          next_state   <= saved_state;
5237
        else
5238
          st_ctrl      <= idle_st;
5239
          return_state <= fetch_state;
5240
          next_state   <= indirect_state;
5241
        end if;
5242
 
5243
      -- pc relative addressing with 16 bit offset
5244
      -- pick up the low byte of the offset in md
5245
      -- advance the pc
5246
      when pcrel16_state =>
5247
        op_ctrl      <= latch_op;
5248
        pre_ctrl     <= latch_pre;
5249
        acca_ctrl    <= latch_acca;
5250
        accb_ctrl    <= latch_accb;
5251
        cc_ctrl      <= latch_cc;
5252
        dp_ctrl      <= latch_dp;
5253
        ix_ctrl      <= latch_ix;
5254
        iy_ctrl      <= latch_iy;
5255
        up_ctrl      <= latch_up;
5256
        sp_ctrl      <= latch_sp;
5257
        iv_ctrl      <= latch_iv;
5258
        nmi_ctrl     <= latch_nmi;
5259
        ea_ctrl      <= latch_ea;
5260
        -- advance pc
5261
        left_ctrl    <= pc_left;
5262
        right_ctrl   <= zero_right;
5263
        alu_ctrl     <= alu_nop;
5264
        pc_ctrl      <= incr_pc;
5265
        -- fetch low byte
5266
        ea_ctrl      <= latch_ea;
5267
        md_ctrl      <= fetch_next_md;
5268
        addr_ctrl    <= fetch_ad;
5269
        dout_ctrl    <= md_lo_dout;
5270
        --
5271
        st_ctrl      <= idle_st;
5272
        return_state <= fetch_state;
5273
        next_state   <= pcrel16_2_state;
5274
 
5275
      -- pc relative with16 bit signed offest
5276
      -- md holds signed offset
5277
      when pcrel16_2_state =>
5278
        op_ctrl    <= latch_op;
5279
        pre_ctrl   <= latch_pre;
5280
        acca_ctrl  <= latch_acca;
5281
        accb_ctrl  <= latch_accb;
5282
        cc_ctrl    <= latch_cc;
5283
        dp_ctrl    <= latch_dp;
5284
        ix_ctrl    <= latch_ix;
5285
        iy_ctrl    <= latch_iy;
5286
        up_ctrl    <= latch_up;
5287
        sp_ctrl    <= latch_sp;
5288
        iv_ctrl    <= latch_iv;
5289
        nmi_ctrl   <= latch_nmi;
5290
        pc_ctrl    <= latch_pc;
5291
        -- ea = pc +  md
5292
        left_ctrl  <= pc_left;
5293
        right_ctrl <= md_right;
5294
        alu_ctrl   <= alu_add16;
5295
        ea_ctrl    <= load_ea;
5296
        md_ctrl    <= latch_md;
5297
        -- idle bus
5298
        addr_ctrl  <= idle_ad;
5299
        dout_ctrl  <= md_lo_dout;
5300
        -- return to previous state
5301
        if ea(4) = '0' then
5302
          st_ctrl      <= pull_st;
5303
          return_state <= fetch_state;
5304
          next_state   <= saved_state;
5305
        else
5306
          st_ctrl      <= idle_st;
5307
          return_state <= fetch_state;
5308
          next_state   <= indirect_state;
5309
        end if;
5310
 
5311
      -- indexed to address
5312
      -- pick up the low byte of the address
5313
      -- advance the pc
5314
      when indexaddr_state =>
5315
        acca_ctrl    <= latch_acca;
5316
        accb_ctrl    <= latch_accb;
5317
        cc_ctrl      <= latch_cc;
5318
        dp_ctrl      <= latch_dp;
5319
        ix_ctrl      <= latch_ix;
5320
        iy_ctrl      <= latch_iy;
5321
        up_ctrl      <= latch_up;
5322
        sp_ctrl      <= latch_sp;
5323
        iv_ctrl      <= latch_iv;
5324
        op_ctrl      <= latch_op;
5325
        pre_ctrl     <= latch_pre;
5326
        nmi_ctrl     <= latch_nmi;
5327
        -- advance pc
5328
        left_ctrl    <= pc_left;
5329
        right_ctrl   <= zero_right;
5330
        alu_ctrl     <= alu_nop;
5331
        pc_ctrl      <= incr_pc;
5332
        -- fetch low byte
5333
        ea_ctrl      <= latch_ea;
5334
        md_ctrl      <= fetch_next_md;
5335
        addr_ctrl    <= fetch_ad;
5336
        dout_ctrl    <= md_lo_dout;
5337
        --
5338
        st_ctrl      <= idle_st;
5339
        return_state <= fetch_state;
5340
        next_state   <= indexaddr2_state;
5341
 
5342
        -- indexed to absolute address
5343
        -- md holds address
5344
        -- ea hold indexing mode byte
5345
      when indexaddr2_state =>
5346
        op_ctrl    <= latch_op;
5347
        pre_ctrl   <= latch_pre;
5348
        acca_ctrl  <= latch_acca;
5349
        accb_ctrl  <= latch_accb;
5350
        cc_ctrl    <= latch_cc;
5351
        dp_ctrl    <= latch_dp;
5352
        ix_ctrl    <= latch_ix;
5353
        iy_ctrl    <= latch_iy;
5354
        up_ctrl    <= latch_up;
5355
        sp_ctrl    <= latch_sp;
5356
        iv_ctrl    <= latch_iv;
5357
        nmi_ctrl   <= latch_nmi;
5358
        pc_ctrl    <= latch_pc;
5359
        -- ea = md
5360
        left_ctrl  <= pc_left;
5361
        right_ctrl <= md_right;
5362
        alu_ctrl   <= alu_ld16;
5363
        ea_ctrl    <= load_ea;
5364
        md_ctrl    <= latch_md;
5365
        -- idle bus
5366
        addr_ctrl  <= idle_ad;
5367
        dout_ctrl  <= md_lo_dout;
5368
        -- return to previous state
5369
        if ea(4) = '0' then
5370
          st_ctrl      <= pull_st;
5371
          return_state <= fetch_state;
5372
          next_state   <= saved_state;
5373
        else
5374
          st_ctrl      <= idle_st;
5375
          return_state <= fetch_state;
5376
          next_state   <= indirect_state;
5377
        end if;
5378
 
5379
      --
5380
      -- load md with high byte of indirect address
5381
      -- pointed to by ea
5382
      -- increment ea
5383
      --
5384
      when indirect_state =>
5385
        acca_ctrl    <= latch_acca;
5386
        accb_ctrl    <= latch_accb;
5387
        cc_ctrl      <= latch_cc;
5388
        dp_ctrl      <= latch_dp;
5389
        ix_ctrl      <= latch_ix;
5390
        iy_ctrl      <= latch_iy;
5391
        up_ctrl      <= latch_up;
5392
        sp_ctrl      <= latch_sp;
5393
        iv_ctrl      <= latch_iv;
5394
        op_ctrl      <= latch_op;
5395
        pre_ctrl     <= latch_pre;
5396
        nmi_ctrl     <= latch_nmi;
5397
        pc_ctrl      <= latch_pc;
5398
        -- increment ea
5399
        left_ctrl    <= ea_left;
5400
        right_ctrl   <= one_right;
5401
        alu_ctrl     <= alu_add16;
5402
        ea_ctrl      <= load_ea;
5403
        -- fetch high byte
5404
        md_ctrl      <= fetch_first_md;
5405
        addr_ctrl    <= read_ad;
5406
        dout_ctrl    <= md_lo_dout;
5407
        --
5408
        st_ctrl      <= idle_st;
5409
        return_state <= fetch_state;
5410
        next_state   <= indirect2_state;
5411
      --
5412
      -- load md with low byte of indirect address
5413
      -- pointed to by ea
5414
      -- ea has previously been incremented
5415
      --
5416
      when indirect2_state =>
5417
        acca_ctrl    <= latch_acca;
5418
        accb_ctrl    <= latch_accb;
5419
        cc_ctrl      <= latch_cc;
5420
        dp_ctrl      <= latch_dp;
5421
        ix_ctrl      <= latch_ix;
5422
        iy_ctrl      <= latch_iy;
5423
        up_ctrl      <= latch_up;
5424
        sp_ctrl      <= latch_sp;
5425
        iv_ctrl      <= latch_iv;
5426
        op_ctrl      <= latch_op;
5427
        pre_ctrl     <= latch_pre;
5428
        nmi_ctrl     <= latch_nmi;
5429
        pc_ctrl      <= latch_pc;
5430
        -- idle ea
5431
        left_ctrl    <= ea_left;
5432
        right_ctrl   <= zero_right;
5433
        alu_ctrl     <= alu_nop;
5434
        ea_ctrl      <= latch_ea;
5435
        -- fetch high byte
5436
        md_ctrl      <= fetch_next_md;
5437
        addr_ctrl    <= read_ad;
5438
        dout_ctrl    <= md_lo_dout;
5439
        --
5440
        st_ctrl      <= idle_st;
5441
        return_state <= fetch_state;
5442
        next_state   <= indirect3_state;
5443
      --
5444
      -- complete idirect addressing
5445
      -- by loading ea with md
5446
      --
5447
      when indirect3_state =>
5448
        acca_ctrl    <= latch_acca;
5449
        accb_ctrl    <= latch_accb;
5450
        cc_ctrl      <= latch_cc;
5451
        dp_ctrl      <= latch_dp;
5452
        ix_ctrl      <= latch_ix;
5453
        iy_ctrl      <= latch_iy;
5454
        up_ctrl      <= latch_up;
5455
        sp_ctrl      <= latch_sp;
5456
        iv_ctrl      <= latch_iv;
5457
        op_ctrl      <= latch_op;
5458
        pre_ctrl     <= latch_pre;
5459
        nmi_ctrl     <= latch_nmi;
5460
        pc_ctrl      <= latch_pc;
5461
        -- load ea with md
5462
        left_ctrl    <= ea_left;
5463
        right_ctrl   <= md_right;
5464
        alu_ctrl     <= alu_ld16;
5465
        ea_ctrl      <= load_ea;
5466
        -- idle cycle
5467
        md_ctrl      <= latch_md;
5468
        addr_ctrl    <= idle_ad;
5469
        dout_ctrl    <= md_lo_dout;
5470
        -- return to previous state
5471
        st_ctrl      <= pull_st;
5472
        return_state <= fetch_state;
5473
        next_state   <= saved_state;
5474
 
5475
      --
5476
      -- ea holds the low byte of the absolute address
5477
      -- Move ea low byte into ea high byte
5478
      -- load new ea low byte to for absolute 16 bit address
5479
      -- advance the program counter
5480
      --
5481
      when extended_state =>            -- fetch ea low byte
5482
        acca_ctrl    <= latch_acca;
5483
        accb_ctrl    <= latch_accb;
5484
        ix_ctrl      <= latch_ix;
5485
        iy_ctrl      <= latch_iy;
5486
        up_ctrl      <= latch_up;
5487
        sp_ctrl      <= latch_sp;
5488
        md_ctrl      <= latch_md;
5489
        iv_ctrl      <= latch_iv;
5490
        dp_ctrl      <= latch_dp;
5491
        op_ctrl      <= latch_op;
5492
        pre_ctrl     <= latch_pre;
5493
        nmi_ctrl     <= latch_nmi;
5494
                                        -- increment pc
5495
        left_ctrl    <= pc_left;
5496
        right_ctrl   <= zero_right;
5497
        alu_ctrl     <= alu_nop;
5498
        cc_ctrl      <= latch_cc;
5499
        pc_ctrl      <= incr_pc;
5500
                                        -- fetch next effective address bytes
5501
        ea_ctrl      <= fetch_next_ea;
5502
        addr_ctrl    <= fetch_ad;
5503
        dout_ctrl    <= md_lo_dout;
5504
        -- return to previous state
5505
        st_ctrl      <= pull_st;
5506
        return_state <= fetch_state;
5507
        next_state   <= saved_state;
5508
 
5509
      when lea_state =>                 -- here on load effective address
5510
        op_ctrl    <= latch_op;
5511
        acca_ctrl  <= latch_acca;
5512
        accb_ctrl  <= latch_accb;
5513
        dp_ctrl    <= latch_dp;
5514
        iv_ctrl    <= latch_iv;
5515
        pre_ctrl   <= latch_pre;
5516
        nmi_ctrl   <= latch_nmi;
5517
        md_ctrl    <= latch_md;
5518
        ea_ctrl    <= latch_ea;
5519
        pc_ctrl    <= latch_pc;
5520
                                        -- load index register with effective address
5521
        left_ctrl  <= pc_left;
5522
        right_ctrl <= ea_right;
5523
        alu_ctrl   <= alu_lea;
5524
        case op_code(3 downto 0) is
5525
          when "0000" =>                -- leax
5526
            cc_ctrl <= load_cc;
5527
            ix_ctrl <= load_ix;
5528
            iy_ctrl <= latch_iy;
5529
            up_ctrl <= latch_up;
5530
            sp_ctrl <= latch_sp;
5531
          when "0001" =>                -- leay
5532
            cc_ctrl <= load_cc;
5533
            ix_ctrl <= latch_ix;
5534
            iy_ctrl <= load_iy;
5535
            up_ctrl <= latch_up;
5536
            sp_ctrl <= latch_sp;
5537
          when "0010" =>                -- leas
5538
            cc_ctrl <= latch_cc;
5539
            ix_ctrl <= latch_ix;
5540
            iy_ctrl <= latch_iy;
5541
            up_ctrl <= latch_up;
5542
            sp_ctrl <= load_sp;
5543
          when "0011" =>                -- leau
5544
            cc_ctrl <= latch_cc;
5545
            ix_ctrl <= latch_ix;
5546
            iy_ctrl <= latch_iy;
5547
            up_ctrl <= load_up;
5548
            sp_ctrl <= latch_sp;
5549
          when others =>
5550
            cc_ctrl <= latch_cc;
5551
            ix_ctrl <= latch_ix;
5552
            iy_ctrl <= latch_iy;
5553
            up_ctrl <= latch_up;
5554
            sp_ctrl <= latch_sp;
5555
        end case;
5556
                                        -- idle the bus
5557
        addr_ctrl    <= idle_ad;
5558
        dout_ctrl    <= md_lo_dout;
5559
                                        --
5560
        st_ctrl      <= idle_st;
5561
        return_state <= fetch_state;
5562
        next_state   <= fetch_state;
5563
 
5564
      --
5565
      -- jump to subroutine
5566
      -- sp=sp-1
5567
      -- call push_return_lo_state to save pc
5568
      -- return to jmp_state
5569
      --
5570
      when jsr_state =>
5571
        acca_ctrl    <= latch_acca;
5572
        accb_ctrl    <= latch_accb;
5573
        cc_ctrl      <= latch_cc;
5574
        dp_ctrl      <= latch_dp;
5575
        ix_ctrl      <= latch_ix;
5576
        iy_ctrl      <= latch_iy;
5577
        up_ctrl      <= latch_up;
5578
        iv_ctrl      <= latch_iv;
5579
        op_ctrl      <= latch_op;
5580
        pre_ctrl     <= latch_pre;
5581
        nmi_ctrl     <= latch_nmi;
5582
        md_ctrl      <= latch_md;
5583
        ea_ctrl      <= latch_ea;
5584
        pc_ctrl      <= latch_pc;
5585
                                        -- decrement sp
5586
        left_ctrl    <= sp_left;
5587
        right_ctrl   <= one_right;
5588
        alu_ctrl     <= alu_sub16;
5589
        sp_ctrl      <= load_sp;
5590
                                        -- idle bus
5591
        addr_ctrl    <= idle_ad;
5592
        dout_ctrl    <= pc_lo_dout;
5593
                                        -- call push_return_state
5594
        st_ctrl      <= push_st;
5595
        return_state <= jmp_state;
5596
        next_state   <= push_return_lo_state;
5597
 
5598
      --
5599
      -- Load pc with ea
5600
      -- (JMP)
5601
      --
5602
      when jmp_state =>
5603
        acca_ctrl    <= latch_acca;
5604
        accb_ctrl    <= latch_accb;
5605
        cc_ctrl      <= latch_cc;
5606
        dp_ctrl      <= latch_dp;
5607
        ix_ctrl      <= latch_ix;
5608
        iy_ctrl      <= latch_iy;
5609
        up_ctrl      <= latch_up;
5610
        sp_ctrl      <= latch_sp;
5611
        iv_ctrl      <= latch_iv;
5612
        op_ctrl      <= latch_op;
5613
        pre_ctrl     <= latch_pre;
5614
        nmi_ctrl     <= latch_nmi;
5615
        md_ctrl      <= latch_md;
5616
        ea_ctrl      <= latch_ea;
5617
                                        -- load PC with effective address
5618
        left_ctrl    <= pc_left;
5619
        right_ctrl   <= ea_right;
5620
        alu_ctrl     <= alu_ld16;
5621
        pc_ctrl      <= load_pc;
5622
                                        -- idle the bus
5623
        addr_ctrl    <= idle_ad;
5624
        dout_ctrl    <= md_lo_dout;
5625
                                        --
5626
        st_ctrl      <= idle_st;
5627
        return_state <= fetch_state;
5628
        next_state   <= fetch_state;
5629
 
5630
      --
5631
      -- long branch or branch to subroutine
5632
      -- pick up next md byte
5633
      -- md_hi = md_lo
5634
      -- md_lo = (pc)
5635
      -- pc=pc+1
5636
      -- if a lbsr push return address
5637
      -- continue to sbranch_state
5638
      -- to evaluate conditional branches
5639
      --
5640
      when lbranch_state =>
5641
        acca_ctrl  <= latch_acca;
5642
        accb_ctrl  <= latch_accb;
5643
        cc_ctrl    <= latch_cc;
5644
        dp_ctrl    <= latch_dp;
5645
        ix_ctrl    <= latch_ix;
5646
        iy_ctrl    <= latch_iy;
5647
        up_ctrl    <= latch_up;
5648
        sp_ctrl    <= latch_sp;
5649
        iv_ctrl    <= latch_iv;
5650
        op_ctrl    <= latch_op;
5651
        pre_ctrl   <= latch_pre;
5652
        nmi_ctrl   <= latch_nmi;
5653
        ea_ctrl    <= latch_ea;
5654
                                        --
5655
        left_ctrl  <= pc_left;
5656
        right_ctrl <= ea_right;
5657
        alu_ctrl   <= alu_ld16;
5658
        pc_ctrl    <= incr_pc;
5659
                                        -- fetch the next byte into md_lo
5660
        md_ctrl    <= fetch_next_md;
5661
        addr_ctrl  <= fetch_ad;
5662
        dout_ctrl  <= md_lo_dout;
5663
                                        -- if lbsr - push return address
5664
                                        -- then continue on to short branch
5665
        if op_code = "00010111" then
5666
          st_ctrl      <= push_st;
5667
          return_state <= sbranch_state;
5668
          next_state   <= push_return_lo_state;
5669
        else
5670
          st_ctrl      <= idle_st;
5671
          return_state <= fetch_state;
5672
          next_state   <= sbranch_state;
5673
        end if;
5674
 
5675
      --
5676
      -- here to execute conditional branch
5677
      -- short conditional branch md = signed 8 bit offset
5678
      -- long branch md = 16 bit offset
5679
      --
5680
      when sbranch_state =>
5681
        acca_ctrl    <= latch_acca;
5682
        accb_ctrl    <= latch_accb;
5683
        cc_ctrl      <= latch_cc;
5684
        dp_ctrl      <= latch_dp;
5685
        ix_ctrl      <= latch_ix;
5686
        iy_ctrl      <= latch_iy;
5687
        up_ctrl      <= latch_up;
5688
        sp_ctrl      <= latch_sp;
5689
        iv_ctrl      <= latch_iv;
5690
        op_ctrl      <= latch_op;
5691
        pre_ctrl     <= latch_pre;
5692
        nmi_ctrl     <= latch_nmi;
5693
        ea_ctrl      <= latch_ea;
5694
        md_ctrl      <= latch_md;
5695
                                              --
5696
        left_ctrl    <= pc_left;
5697
        right_ctrl   <= md_right;
5698
        alu_ctrl     <= alu_add16;
5699
                                              --
5700
        addr_ctrl    <= idle_ad;
5701
        dout_ctrl    <= md_lo_dout;
5702
                                              --
5703
        st_ctrl      <= idle_st;
5704
        return_state <= fetch_state;
5705
        next_state   <= fetch_state;
5706
        if op_code(7 downto 4) = "0010" then  -- conditional branch
5707
          case op_code(3 downto 0) is
5708
            when "0000" =>                    -- bra
5709
              cond_true := (1 = 1);
5710
            when "0001" =>                    -- brn
5711
              cond_true := (1 = 0);
5712
            when "0010" =>                    -- bhi
5713
              cond_true := ((cc(CBIT) or cc(ZBIT)) = '0');
5714
            when "0011" =>                    -- bls
5715
              cond_true := ((cc(CBIT) or cc(ZBIT)) = '1');
5716
            when "0100" =>                    -- bcc/bhs
5717
              cond_true := (cc(CBIT) = '0');
5718
            when "0101" =>                    -- bcs/blo
5719
              cond_true := (cc(CBIT) = '1');
5720
            when "0110" =>                    -- bne
5721
              cond_true := (cc(ZBIT) = '0');
5722
            when "0111" =>                    -- beq
5723
              cond_true := (cc(ZBIT) = '1');
5724
            when "1000" =>                    -- bvc
5725
              cond_true := (cc(VBIT) = '0');
5726
            when "1001" =>                    -- bvs
5727
              cond_true := (cc(VBIT) = '1');
5728
            when "1010" =>                    -- bpl
5729
              cond_true := (cc(NBIT) = '0');
5730
            when "1011" =>                    -- bmi
5731
              cond_true := (cc(NBIT) = '1');
5732
            when "1100" =>                    -- bge
5733
              cond_true := ((cc(NBIT) xor cc(VBIT)) = '0');
5734
            when "1101" =>                    -- blt
5735
              cond_true := ((cc(NBIT) xor cc(VBIT)) = '1');
5736
            when "1110" =>                    -- bgt
5737
              cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '0');
5738
            when "1111" =>                    -- ble
5739
              cond_true := ((cc(ZBIT) or (cc(NBIT) xor cc(VBIT))) = '1');
5740
            when others =>
5741
              cond_true := (1 = 1);
5742
          end case;
5743
        else
5744
          cond_true := (1 = 1);               -- lbra, lbsr, bsr
5745
        end if;
5746
        if cond_true then
5747
          pc_ctrl <= load_pc;
5748
        else
5749
          pc_ctrl <= latch_pc;
5750
        end if;
5751
 
5752
      --
5753
      -- push return address onto the S stack
5754
      --
5755
      -- (sp) = pc_lo
5756
      -- sp = sp - 1
5757
      --
5758
      when push_return_lo_state =>
5759
        -- default
5760
        acca_ctrl    <= latch_acca;
5761
        accb_ctrl    <= latch_accb;
5762
        ix_ctrl      <= latch_ix;
5763
        iy_ctrl      <= latch_iy;
5764
        up_ctrl      <= latch_up;
5765
        md_ctrl      <= latch_md;
5766
        iv_ctrl      <= latch_iv;
5767
        dp_ctrl      <= latch_dp;
5768
        op_ctrl      <= latch_op;
5769
        pre_ctrl     <= latch_pre;
5770
        nmi_ctrl     <= latch_nmi;
5771
        ea_ctrl      <= latch_ea;
5772
                                        -- decrement the sp
5773
        left_ctrl    <= sp_left;
5774
        right_ctrl   <= one_right;
5775
        alu_ctrl     <= alu_sub16;
5776
        cc_ctrl      <= latch_cc;
5777
        sp_ctrl      <= load_sp;
5778
        -- write PC low
5779
        pc_ctrl      <= latch_pc;
5780
        addr_ctrl    <= pushs_ad;
5781
        dout_ctrl    <= pc_lo_dout;
5782
                                        --
5783
        st_ctrl      <= idle_st;
5784
        return_state <= fetch_state;
5785
        next_state   <= push_return_hi_state;
5786
 
5787
      --
5788
      -- push program counter hi byte onto the stack
5789
      -- (sp) = pc_hi
5790
      -- sp = sp
5791
      -- return to originating state
5792
      --
5793
      when push_return_hi_state =>
5794
        -- default
5795
        acca_ctrl    <= latch_acca;
5796
        accb_ctrl    <= latch_accb;
5797
        ix_ctrl      <= latch_ix;
5798
        iy_ctrl      <= latch_iy;
5799
        up_ctrl      <= latch_up;
5800
        md_ctrl      <= latch_md;
5801
        iv_ctrl      <= latch_iv;
5802
        dp_ctrl      <= latch_dp;
5803
        op_ctrl      <= latch_op;
5804
        pre_ctrl     <= latch_pre;
5805
        nmi_ctrl     <= latch_nmi;
5806
        ea_ctrl      <= latch_ea;
5807
                                        -- idle the SP
5808
        left_ctrl    <= sp_left;
5809
        right_ctrl   <= one_right;
5810
        alu_ctrl     <= alu_sub16;
5811
        cc_ctrl      <= latch_cc;
5812
        sp_ctrl      <= latch_sp;
5813
                                        -- write pc hi bytes
5814
        pc_ctrl      <= latch_pc;
5815
        addr_ctrl    <= pushs_ad;
5816
        dout_ctrl    <= pc_hi_dout;
5817
                                        --
5818
        st_ctrl      <= pull_st;
5819
        return_state <= fetch_state;
5820
        next_state   <= saved_state;
5821
 
5822
      when pull_return_hi_state =>
5823
        -- default
5824
        acca_ctrl    <= latch_acca;
5825
        accb_ctrl    <= latch_accb;
5826
        ix_ctrl      <= latch_ix;
5827
        iy_ctrl      <= latch_iy;
5828
        up_ctrl      <= latch_up;
5829
        md_ctrl      <= latch_md;
5830
        iv_ctrl      <= latch_iv;
5831
        dp_ctrl      <= latch_dp;
5832
        op_ctrl      <= latch_op;
5833
        pre_ctrl     <= latch_pre;
5834
        nmi_ctrl     <= latch_nmi;
5835
        ea_ctrl      <= latch_ea;
5836
                                        -- increment the sp
5837
        left_ctrl    <= sp_left;
5838
        right_ctrl   <= one_right;
5839
        alu_ctrl     <= alu_add16;
5840
        cc_ctrl      <= latch_cc;
5841
        sp_ctrl      <= load_sp;
5842
        -- read pc hi
5843
        pc_ctrl      <= pull_hi_pc;
5844
        addr_ctrl    <= pulls_ad;
5845
        dout_ctrl    <= pc_hi_dout;
5846
                                        --
5847
        st_ctrl      <= idle_st;
5848
        return_state <= fetch_state;
5849
        next_state   <= pull_return_lo_state;
5850
 
5851
      when pull_return_lo_state =>
5852
        -- default
5853
        acca_ctrl    <= latch_acca;
5854
        accb_ctrl    <= latch_accb;
5855
        ix_ctrl      <= latch_ix;
5856
        iy_ctrl      <= latch_iy;
5857
        up_ctrl      <= latch_up;
5858
        md_ctrl      <= latch_md;
5859
        iv_ctrl      <= latch_iv;
5860
        dp_ctrl      <= latch_dp;
5861
        op_ctrl      <= latch_op;
5862
        pre_ctrl     <= latch_pre;
5863
        nmi_ctrl     <= latch_nmi;
5864
        ea_ctrl      <= latch_ea;
5865
                                        -- increment the SP
5866
        left_ctrl    <= sp_left;
5867
        right_ctrl   <= one_right;
5868
        alu_ctrl     <= alu_add16;
5869
        cc_ctrl      <= latch_cc;
5870
        sp_ctrl      <= load_sp;
5871
                                        -- read pc low
5872
        pc_ctrl      <= pull_lo_pc;
5873
        addr_ctrl    <= pulls_ad;
5874
        dout_ctrl    <= pc_lo_dout;
5875
                                        --
5876
        st_ctrl      <= pull_st;
5877
        return_state <= fetch_state;
5878
        next_state   <= saved_state;
5879
 
5880
      when andcc_state =>
5881
        -- default
5882
        acca_ctrl    <= latch_acca;
5883
        accb_ctrl    <= latch_accb;
5884
        ix_ctrl      <= latch_ix;
5885
        iy_ctrl      <= latch_iy;
5886
        up_ctrl      <= latch_up;
5887
        sp_ctrl      <= latch_sp;
5888
        pc_ctrl      <= latch_pc;
5889
        iv_ctrl      <= latch_iv;
5890
        dp_ctrl      <= latch_dp;
5891
        op_ctrl      <= latch_op;
5892
        pre_ctrl     <= latch_pre;
5893
        nmi_ctrl     <= latch_nmi;
5894
        ea_ctrl      <= latch_ea;
5895
        md_ctrl      <= latch_md;
5896
                                        -- AND CC with md
5897
        left_ctrl    <= md_left;
5898
        right_ctrl   <= zero_right;
5899
        alu_ctrl     <= alu_andcc;
5900
        cc_ctrl      <= load_cc;
5901
                                        -- idle bus
5902
        addr_ctrl    <= idle_ad;
5903
        dout_ctrl    <= md_lo_dout;
5904
                                        --
5905
        st_ctrl      <= pull_st;
5906
        return_state <= fetch_state;
5907
        next_state   <= saved_state;
5908
 
5909
      when orcc_state =>
5910
        -- default
5911
        acca_ctrl    <= latch_acca;
5912
        accb_ctrl    <= latch_accb;
5913
        ix_ctrl      <= latch_ix;
5914
        iy_ctrl      <= latch_iy;
5915
        up_ctrl      <= latch_up;
5916
        sp_ctrl      <= latch_sp;
5917
        pc_ctrl      <= latch_pc;
5918
        iv_ctrl      <= latch_iv;
5919
        dp_ctrl      <= latch_dp;
5920
        op_ctrl      <= latch_op;
5921
        pre_ctrl     <= latch_pre;
5922
        nmi_ctrl     <= latch_nmi;
5923
        ea_ctrl      <= latch_ea;
5924
        md_ctrl      <= latch_md;
5925
                                        -- OR CC with md
5926
        left_ctrl    <= md_left;
5927
        right_ctrl   <= zero_right;
5928
        alu_ctrl     <= alu_orcc;
5929
        cc_ctrl      <= load_cc;
5930
                                        -- idle bus
5931
        addr_ctrl    <= idle_ad;
5932
        dout_ctrl    <= md_lo_dout;
5933
                                        --
5934
        st_ctrl      <= pull_st;
5935
        return_state <= fetch_state;
5936
        next_state   <= saved_state;
5937
 
5938
      when tfr_state =>
5939
        -- default
5940
        iv_ctrl  <= latch_iv;
5941
        op_ctrl  <= latch_op;
5942
        pre_ctrl <= latch_pre;
5943
        nmi_ctrl <= latch_nmi;
5944
        ea_ctrl  <= latch_ea;
5945
        md_ctrl  <= latch_md;
5946
                                        -- select source register
5947
        case md(7 downto 4) is
5948
          when "0000" =>
5949
            left_ctrl <= accd_left;
5950
          when "0001" =>
5951
            left_ctrl <= ix_left;
5952
          when "0010" =>
5953
            left_ctrl <= iy_left;
5954
          when "0011" =>
5955
            left_ctrl <= up_left;
5956
          when "0100" =>
5957
            left_ctrl <= sp_left;
5958
          when "0101" =>
5959
            left_ctrl <= pc_left;
5960
          when "1000" =>
5961
            left_ctrl <= acca_left;
5962
          when "1001" =>
5963
            left_ctrl <= accb_left;
5964
          when "1010" =>
5965
            left_ctrl <= cc_left;
5966
          when "1011" =>
5967
            left_ctrl <= dp_left;
5968
          when others =>
5969
            left_ctrl <= md_left;
5970
        end case;
5971
        right_ctrl <= zero_right;
5972
        alu_ctrl   <= alu_tfr;
5973
                                        -- select destination register
5974
        case md(3 downto 0) is
5975
          when "0000" =>                -- accd
5976
            ix_ctrl   <= latch_ix;
5977
            iy_ctrl   <= latch_iy;
5978
            up_ctrl   <= latch_up;
5979
            sp_ctrl   <= latch_sp;
5980
            pc_ctrl   <= latch_pc;
5981
            acca_ctrl <= load_hi_acca;
5982
            accb_ctrl <= load_accb;
5983
            cc_ctrl   <= latch_cc;
5984
            dp_ctrl   <= latch_dp;
5985
          when "0001" =>                -- ix
5986
            ix_ctrl   <= load_ix;
5987
            iy_ctrl   <= latch_iy;
5988
            up_ctrl   <= latch_up;
5989
            sp_ctrl   <= latch_sp;
5990
            pc_ctrl   <= latch_pc;
5991
            acca_ctrl <= latch_acca;
5992
            accb_ctrl <= latch_accb;
5993
            cc_ctrl   <= latch_cc;
5994
            dp_ctrl   <= latch_dp;
5995
          when "0010" =>                -- iy
5996
            ix_ctrl   <= latch_ix;
5997
            iy_ctrl   <= load_iy;
5998
            up_ctrl   <= latch_up;
5999
            sp_ctrl   <= latch_sp;
6000
            pc_ctrl   <= latch_pc;
6001
            acca_ctrl <= latch_acca;
6002
            accb_ctrl <= latch_accb;
6003
            cc_ctrl   <= latch_cc;
6004
            dp_ctrl   <= latch_dp;
6005
          when "0011" =>                -- up
6006
            ix_ctrl   <= latch_ix;
6007
            iy_ctrl   <= latch_iy;
6008
            up_ctrl   <= load_up;
6009
            sp_ctrl   <= latch_sp;
6010
            pc_ctrl   <= latch_pc;
6011
            acca_ctrl <= latch_acca;
6012
            accb_ctrl <= latch_accb;
6013
            cc_ctrl   <= latch_cc;
6014
            dp_ctrl   <= latch_dp;
6015
          when "0100" =>                -- sp
6016
            ix_ctrl   <= latch_ix;
6017
            iy_ctrl   <= latch_iy;
6018
            up_ctrl   <= latch_up;
6019
            sp_ctrl   <= load_sp;
6020
            pc_ctrl   <= latch_pc;
6021
            acca_ctrl <= latch_acca;
6022
            accb_ctrl <= latch_accb;
6023
            cc_ctrl   <= latch_cc;
6024
            dp_ctrl   <= latch_dp;
6025
          when "0101" =>                -- pc
6026
            ix_ctrl   <= latch_ix;
6027
            iy_ctrl   <= latch_iy;
6028
            up_ctrl   <= latch_up;
6029
            sp_ctrl   <= latch_sp;
6030
            pc_ctrl   <= load_pc;
6031
            acca_ctrl <= latch_acca;
6032
            accb_ctrl <= latch_accb;
6033
            cc_ctrl   <= latch_cc;
6034
            dp_ctrl   <= latch_dp;
6035
          when "1000" =>                -- acca
6036
            ix_ctrl   <= latch_ix;
6037
            iy_ctrl   <= latch_iy;
6038
            up_ctrl   <= latch_up;
6039
            sp_ctrl   <= latch_sp;
6040
            pc_ctrl   <= latch_pc;
6041
            acca_ctrl <= load_acca;
6042
            accb_ctrl <= latch_accb;
6043
            cc_ctrl   <= latch_cc;
6044
            dp_ctrl   <= latch_dp;
6045
          when "1001" =>                -- accb
6046
            ix_ctrl   <= latch_ix;
6047
            iy_ctrl   <= latch_iy;
6048
            up_ctrl   <= latch_up;
6049
            sp_ctrl   <= latch_sp;
6050
            pc_ctrl   <= latch_pc;
6051
            acca_ctrl <= latch_acca;
6052
            accb_ctrl <= load_accb;
6053
            cc_ctrl   <= latch_cc;
6054
            dp_ctrl   <= latch_dp;
6055
          when "1010" =>                -- cc
6056
            ix_ctrl   <= latch_ix;
6057
            iy_ctrl   <= latch_iy;
6058
            up_ctrl   <= latch_up;
6059
            sp_ctrl   <= latch_sp;
6060
            pc_ctrl   <= latch_pc;
6061
            acca_ctrl <= latch_acca;
6062
            accb_ctrl <= latch_accb;
6063
            cc_ctrl   <= load_cc;
6064
            dp_ctrl   <= latch_dp;
6065
          when "1011" =>                --dp
6066
            ix_ctrl   <= latch_ix;
6067
            iy_ctrl   <= latch_iy;
6068
            up_ctrl   <= latch_up;
6069
            sp_ctrl   <= latch_sp;
6070
            pc_ctrl   <= latch_pc;
6071
            acca_ctrl <= latch_acca;
6072
            accb_ctrl <= latch_accb;
6073
            cc_ctrl   <= latch_cc;
6074
            dp_ctrl   <= load_dp;
6075
          when others =>
6076
            ix_ctrl   <= latch_ix;
6077
            iy_ctrl   <= latch_iy;
6078
            up_ctrl   <= latch_up;
6079
            sp_ctrl   <= latch_sp;
6080
            pc_ctrl   <= latch_pc;
6081
            acca_ctrl <= latch_acca;
6082
            accb_ctrl <= latch_accb;
6083
            cc_ctrl   <= latch_cc;
6084
            dp_ctrl   <= latch_dp;
6085
        end case;
6086
                                        -- idle bus
6087
        addr_ctrl    <= idle_ad;
6088
        dout_ctrl    <= md_lo_dout;
6089
                                        --
6090
        st_ctrl      <= pull_st;
6091
        return_state <= fetch_state;
6092
        next_state   <= saved_state;
6093
 
6094
      when exg_state =>
6095
        -- default
6096
        iv_ctrl  <= latch_iv;
6097
        op_ctrl  <= latch_op;
6098
        pre_ctrl <= latch_pre;
6099
        nmi_ctrl <= latch_nmi;
6100
        md_ctrl  <= latch_md;
6101
                                        -- save destination register
6102
        case md(3 downto 0) is
6103
          when "0000" =>
6104
            left_ctrl <= accd_left;
6105
          when "0001" =>
6106
            left_ctrl <= ix_left;
6107
          when "0010" =>
6108
            left_ctrl <= iy_left;
6109
          when "0011" =>
6110
            left_ctrl <= up_left;
6111
          when "0100" =>
6112
            left_ctrl <= sp_left;
6113
          when "0101" =>
6114
            left_ctrl <= pc_left;
6115
          when "1000" =>
6116
            left_ctrl <= acca_left;
6117
          when "1001" =>
6118
            left_ctrl <= accb_left;
6119
          when "1010" =>
6120
            left_ctrl <= cc_left;
6121
          when "1011" =>
6122
            left_ctrl <= dp_left;
6123
          when others =>
6124
            left_ctrl <= md_left;
6125
        end case;
6126
        right_ctrl <= zero_right;
6127
        alu_ctrl   <= alu_tfr;
6128
        ea_ctrl    <= load_ea;
6129
 
6130
        ix_ctrl      <= latch_ix;
6131
        iy_ctrl      <= latch_iy;
6132
        up_ctrl      <= latch_up;
6133
        sp_ctrl      <= latch_sp;
6134
        pc_ctrl      <= latch_pc;
6135
        acca_ctrl    <= latch_acca;
6136
        accb_ctrl    <= latch_accb;
6137
        cc_ctrl      <= latch_cc;
6138
        dp_ctrl      <= latch_dp;
6139
                                        -- idle bus
6140
        addr_ctrl    <= idle_ad;
6141
        dout_ctrl    <= md_lo_dout;
6142
                                        -- call tranfer microcode
6143
        st_ctrl      <= push_st;
6144
        return_state <= exg1_state;
6145
        next_state   <= tfr_state;
6146
 
6147
      when exg1_state =>
6148
        -- default
6149
        iv_ctrl    <= latch_iv;
6150
        op_ctrl    <= latch_op;
6151
        pre_ctrl   <= latch_pre;
6152
        nmi_ctrl   <= latch_nmi;
6153
        ea_ctrl    <= latch_ea;
6154
        md_ctrl    <= latch_md;
6155
                                        -- restore destination
6156
        left_ctrl  <= ea_left;
6157
        right_ctrl <= zero_right;
6158
        alu_ctrl   <= alu_tfr;
6159
                                        -- save as source register
6160
        case md(7 downto 4) is
6161
          when "0000" =>                -- accd
6162
            ix_ctrl   <= latch_ix;
6163
            iy_ctrl   <= latch_iy;
6164
            up_ctrl   <= latch_up;
6165
            sp_ctrl   <= latch_sp;
6166
            pc_ctrl   <= latch_pc;
6167
            acca_ctrl <= load_hi_acca;
6168
            accb_ctrl <= load_accb;
6169
            cc_ctrl   <= latch_cc;
6170
            dp_ctrl   <= latch_dp;
6171
          when "0001" =>                -- ix
6172
            ix_ctrl   <= load_ix;
6173
            iy_ctrl   <= latch_iy;
6174
            up_ctrl   <= latch_up;
6175
            sp_ctrl   <= latch_sp;
6176
            pc_ctrl   <= latch_pc;
6177
            acca_ctrl <= latch_acca;
6178
            accb_ctrl <= latch_accb;
6179
            cc_ctrl   <= latch_cc;
6180
            dp_ctrl   <= latch_dp;
6181
          when "0010" =>                -- iy
6182
            ix_ctrl   <= latch_ix;
6183
            iy_ctrl   <= load_iy;
6184
            up_ctrl   <= latch_up;
6185
            sp_ctrl   <= latch_sp;
6186
            pc_ctrl   <= latch_pc;
6187
            acca_ctrl <= latch_acca;
6188
            accb_ctrl <= latch_accb;
6189
            cc_ctrl   <= latch_cc;
6190
            dp_ctrl   <= latch_dp;
6191
          when "0011" =>                -- up
6192
            ix_ctrl   <= latch_ix;
6193
            iy_ctrl   <= latch_iy;
6194
            up_ctrl   <= load_up;
6195
            sp_ctrl   <= latch_sp;
6196
            pc_ctrl   <= latch_pc;
6197
            acca_ctrl <= latch_acca;
6198
            accb_ctrl <= latch_accb;
6199
            cc_ctrl   <= latch_cc;
6200
            dp_ctrl   <= latch_dp;
6201
          when "0100" =>                -- sp
6202
            ix_ctrl   <= latch_ix;
6203
            iy_ctrl   <= latch_iy;
6204
            up_ctrl   <= latch_up;
6205
            sp_ctrl   <= load_sp;
6206
            pc_ctrl   <= latch_pc;
6207
            acca_ctrl <= latch_acca;
6208
            accb_ctrl <= latch_accb;
6209
            cc_ctrl   <= latch_cc;
6210
            dp_ctrl   <= latch_dp;
6211
          when "0101" =>                -- pc
6212
            ix_ctrl   <= latch_ix;
6213
            iy_ctrl   <= latch_iy;
6214
            up_ctrl   <= latch_up;
6215
            sp_ctrl   <= latch_sp;
6216
            pc_ctrl   <= load_pc;
6217
            acca_ctrl <= latch_acca;
6218
            accb_ctrl <= latch_accb;
6219
            cc_ctrl   <= latch_cc;
6220
            dp_ctrl   <= latch_dp;
6221
          when "1000" =>                -- acca
6222
            ix_ctrl   <= latch_ix;
6223
            iy_ctrl   <= latch_iy;
6224
            up_ctrl   <= latch_up;
6225
            sp_ctrl   <= latch_sp;
6226
            pc_ctrl   <= latch_pc;
6227
            acca_ctrl <= load_acca;
6228
            accb_ctrl <= latch_accb;
6229
            cc_ctrl   <= latch_cc;
6230
            dp_ctrl   <= latch_dp;
6231
          when "1001" =>                -- accb
6232
            ix_ctrl   <= latch_ix;
6233
            iy_ctrl   <= latch_iy;
6234
            up_ctrl   <= latch_up;
6235
            sp_ctrl   <= latch_sp;
6236
            pc_ctrl   <= latch_pc;
6237
            acca_ctrl <= latch_acca;
6238
            accb_ctrl <= load_accb;
6239
            cc_ctrl   <= latch_cc;
6240
            dp_ctrl   <= latch_dp;
6241
          when "1010" =>                -- cc
6242
            acca_ctrl <= latch_acca;
6243
            accb_ctrl <= latch_accb;
6244
            ix_ctrl   <= latch_ix;
6245
            iy_ctrl   <= latch_iy;
6246
            up_ctrl   <= latch_up;
6247
            sp_ctrl   <= latch_sp;
6248
            pc_ctrl   <= latch_pc;
6249
            acca_ctrl <= latch_acca;
6250
            accb_ctrl <= latch_accb;
6251
            cc_ctrl   <= load_cc;
6252
            dp_ctrl   <= latch_dp;
6253
          when "1011" =>                --dp
6254
            acca_ctrl <= latch_acca;
6255
            accb_ctrl <= latch_accb;
6256
            ix_ctrl   <= latch_ix;
6257
            iy_ctrl   <= latch_iy;
6258
            up_ctrl   <= latch_up;
6259
            sp_ctrl   <= latch_sp;
6260
            pc_ctrl   <= latch_pc;
6261
            acca_ctrl <= latch_acca;
6262
            accb_ctrl <= latch_accb;
6263
            cc_ctrl   <= latch_cc;
6264
            dp_ctrl   <= load_dp;
6265
          when others =>
6266
            acca_ctrl <= latch_acca;
6267
            accb_ctrl <= latch_accb;
6268
            ix_ctrl   <= latch_ix;
6269
            iy_ctrl   <= latch_iy;
6270
            up_ctrl   <= latch_up;
6271
            sp_ctrl   <= latch_sp;
6272
            pc_ctrl   <= latch_pc;
6273
            acca_ctrl <= latch_acca;
6274
            accb_ctrl <= latch_accb;
6275
            cc_ctrl   <= latch_cc;
6276
            dp_ctrl   <= latch_dp;
6277
        end case;
6278
                                        -- idle bus
6279
        addr_ctrl    <= idle_ad;
6280
        dout_ctrl    <= md_lo_dout;
6281
                                        --
6282
        st_ctrl      <= idle_st;
6283
        return_state <= fetch_state;
6284
        next_state   <= fetch_state;
6285
 
6286
      when mul_state =>
6287
        -- default
6288
        acca_ctrl    <= latch_acca;
6289
        accb_ctrl    <= latch_accb;
6290
        ix_ctrl      <= latch_ix;
6291
        iy_ctrl      <= latch_iy;
6292
        up_ctrl      <= latch_up;
6293
        sp_ctrl      <= latch_sp;
6294
        pc_ctrl      <= latch_pc;
6295
        iv_ctrl      <= latch_iv;
6296
        dp_ctrl      <= latch_dp;
6297
        op_ctrl      <= latch_op;
6298
        pre_ctrl     <= latch_pre;
6299
        nmi_ctrl     <= latch_nmi;
6300
        ea_ctrl      <= latch_ea;
6301
                                        -- move acca to md
6302
        left_ctrl    <= acca_left;
6303
        right_ctrl   <= zero_right;
6304
        alu_ctrl     <= alu_st16;
6305
        cc_ctrl      <= latch_cc;
6306
        md_ctrl      <= load_md;
6307
                                        -- idle bus
6308
        addr_ctrl    <= idle_ad;
6309
        dout_ctrl    <= md_lo_dout;
6310
                                        --
6311
        st_ctrl      <= idle_st;
6312
        return_state <= fetch_state;
6313
        next_state   <= mulea_state;
6314
 
6315
      when mulea_state =>
6316
        -- default
6317
        acca_ctrl    <= latch_acca;
6318
        accb_ctrl    <= latch_accb;
6319
        ix_ctrl      <= latch_ix;
6320
        iy_ctrl      <= latch_iy;
6321
        up_ctrl      <= latch_up;
6322
        sp_ctrl      <= latch_sp;
6323
        pc_ctrl      <= latch_pc;
6324
        iv_ctrl      <= latch_iv;
6325
        dp_ctrl      <= latch_dp;
6326
        op_ctrl      <= latch_op;
6327
        pre_ctrl     <= latch_pre;
6328
        nmi_ctrl     <= latch_nmi;
6329
        md_ctrl      <= latch_md;
6330
                                        -- move accb to ea
6331
        left_ctrl    <= accb_left;
6332
        right_ctrl   <= zero_right;
6333
        alu_ctrl     <= alu_st16;
6334
        cc_ctrl      <= latch_cc;
6335
        ea_ctrl      <= load_ea;
6336
                                        -- idle bus
6337
        addr_ctrl    <= idle_ad;
6338
        dout_ctrl    <= md_lo_dout;
6339
                                        --
6340
        st_ctrl      <= idle_st;
6341
        return_state <= fetch_state;
6342
        next_state   <= muld_state;
6343
 
6344
      when muld_state =>
6345
        -- default
6346
        ix_ctrl      <= latch_ix;
6347
        iy_ctrl      <= latch_iy;
6348
        up_ctrl      <= latch_up;
6349
        sp_ctrl      <= latch_sp;
6350
        pc_ctrl      <= latch_pc;
6351
        iv_ctrl      <= latch_iv;
6352
        dp_ctrl      <= latch_dp;
6353
        op_ctrl      <= latch_op;
6354
        pre_ctrl     <= latch_pre;
6355
        nmi_ctrl     <= latch_nmi;
6356
        ea_ctrl      <= latch_ea;
6357
        md_ctrl      <= latch_md;
6358
                                        -- clear accd
6359
        left_ctrl    <= acca_left;
6360
        right_ctrl   <= zero_right;
6361
        alu_ctrl     <= alu_ld8;
6362
        cc_ctrl      <= latch_cc;
6363
        acca_ctrl    <= load_hi_acca;
6364
        accb_ctrl    <= load_accb;
6365
                                        -- idle bus
6366
        addr_ctrl    <= idle_ad;
6367
        dout_ctrl    <= md_lo_dout;
6368
                                        --
6369
        st_ctrl      <= idle_st;
6370
        return_state <= fetch_state;
6371
        next_state   <= mul0_state;
6372
 
6373
      when mul0_state =>
6374
        -- default
6375
        ix_ctrl   <= latch_ix;
6376
        iy_ctrl   <= latch_iy;
6377
        up_ctrl   <= latch_up;
6378
        sp_ctrl   <= latch_sp;
6379
        pc_ctrl   <= latch_pc;
6380
        iv_ctrl   <= latch_iv;
6381
        dp_ctrl   <= latch_dp;
6382
        op_ctrl   <= latch_op;
6383
        pre_ctrl  <= latch_pre;
6384
        nmi_ctrl  <= latch_nmi;
6385
        ea_ctrl   <= latch_ea;
6386
                                        -- if bit 0 of ea set, add accd to md
6387
        left_ctrl <= accd_left;
6388
        if ea(0) = '1' then
6389
          right_ctrl <= md_right;
6390
        else
6391
          right_ctrl <= zero_right;
6392
        end if;
6393
        alu_ctrl     <= alu_mul;
6394
        cc_ctrl      <= load_cc;
6395
        acca_ctrl    <= load_hi_acca;
6396
        accb_ctrl    <= load_accb;
6397
        md_ctrl      <= shiftl_md;
6398
                                        -- idle bus
6399
        addr_ctrl    <= idle_ad;
6400
        dout_ctrl    <= md_lo_dout;
6401
                                        --
6402
        st_ctrl      <= idle_st;
6403
        return_state <= fetch_state;
6404
        next_state   <= mul1_state;
6405
 
6406
      when mul1_state =>
6407
        -- default
6408
        ix_ctrl   <= latch_ix;
6409
        iy_ctrl   <= latch_iy;
6410
        up_ctrl   <= latch_up;
6411
        sp_ctrl   <= latch_sp;
6412
        pc_ctrl   <= latch_pc;
6413
        iv_ctrl   <= latch_iv;
6414
        dp_ctrl   <= latch_dp;
6415
        op_ctrl   <= latch_op;
6416
        pre_ctrl  <= latch_pre;
6417
        nmi_ctrl  <= latch_nmi;
6418
        ea_ctrl   <= latch_ea;
6419
                                        -- if bit 1 of ea set, add accd to md
6420
        left_ctrl <= accd_left;
6421
        if ea(1) = '1' then
6422
          right_ctrl <= md_right;
6423
        else
6424
          right_ctrl <= zero_right;
6425
        end if;
6426
        alu_ctrl     <= alu_mul;
6427
        cc_ctrl      <= load_cc;
6428
        acca_ctrl    <= load_hi_acca;
6429
        accb_ctrl    <= load_accb;
6430
        md_ctrl      <= shiftl_md;
6431
                                        -- idle bus
6432
        addr_ctrl    <= idle_ad;
6433
        dout_ctrl    <= md_lo_dout;
6434
                                        --
6435
        st_ctrl      <= idle_st;
6436
        return_state <= fetch_state;
6437
        next_state   <= mul2_state;
6438
 
6439
      when mul2_state =>
6440
        -- default
6441
        ix_ctrl   <= latch_ix;
6442
        iy_ctrl   <= latch_iy;
6443
        up_ctrl   <= latch_up;
6444
        sp_ctrl   <= latch_sp;
6445
        pc_ctrl   <= latch_pc;
6446
        iv_ctrl   <= latch_iv;
6447
        dp_ctrl   <= latch_dp;
6448
        op_ctrl   <= latch_op;
6449
        pre_ctrl  <= latch_pre;
6450
        nmi_ctrl  <= latch_nmi;
6451
        ea_ctrl   <= latch_ea;
6452
                                        -- if bit 2 of ea set, add accd to md
6453
        left_ctrl <= accd_left;
6454
        if ea(2) = '1' then
6455
          right_ctrl <= md_right;
6456
        else
6457
          right_ctrl <= zero_right;
6458
        end if;
6459
        alu_ctrl     <= alu_mul;
6460
        cc_ctrl      <= load_cc;
6461
        acca_ctrl    <= load_hi_acca;
6462
        accb_ctrl    <= load_accb;
6463
        md_ctrl      <= shiftl_md;
6464
                                        -- idle bus
6465
        addr_ctrl    <= idle_ad;
6466
        dout_ctrl    <= md_lo_dout;
6467
                                        --
6468
        st_ctrl      <= idle_st;
6469
        return_state <= fetch_state;
6470
        next_state   <= mul3_state;
6471
 
6472
      when mul3_state =>
6473
        -- default
6474
        ix_ctrl   <= latch_ix;
6475
        iy_ctrl   <= latch_iy;
6476
        up_ctrl   <= latch_up;
6477
        sp_ctrl   <= latch_sp;
6478
        pc_ctrl   <= latch_pc;
6479
        iv_ctrl   <= latch_iv;
6480
        dp_ctrl   <= latch_dp;
6481
        op_ctrl   <= latch_op;
6482
        pre_ctrl  <= latch_pre;
6483
        nmi_ctrl  <= latch_nmi;
6484
        ea_ctrl   <= latch_ea;
6485
                                        -- if bit 3 of ea set, add accd to md
6486
        left_ctrl <= accd_left;
6487
        if ea(3) = '1' then
6488
          right_ctrl <= md_right;
6489
        else
6490
          right_ctrl <= zero_right;
6491
        end if;
6492
        alu_ctrl     <= alu_mul;
6493
        cc_ctrl      <= load_cc;
6494
        acca_ctrl    <= load_hi_acca;
6495
        accb_ctrl    <= load_accb;
6496
        md_ctrl      <= shiftl_md;
6497
                                        -- idle bus
6498
        addr_ctrl    <= idle_ad;
6499
        dout_ctrl    <= md_lo_dout;
6500
                                        --
6501
        st_ctrl      <= idle_st;
6502
        return_state <= fetch_state;
6503
        next_state   <= mul4_state;
6504
 
6505
      when mul4_state =>
6506
        -- default
6507
        ix_ctrl   <= latch_ix;
6508
        iy_ctrl   <= latch_iy;
6509
        up_ctrl   <= latch_up;
6510
        sp_ctrl   <= latch_sp;
6511
        pc_ctrl   <= latch_pc;
6512
        iv_ctrl   <= latch_iv;
6513
        dp_ctrl   <= latch_dp;
6514
        op_ctrl   <= latch_op;
6515
        nmi_ctrl  <= latch_nmi;
6516
        pre_ctrl  <= latch_pre;
6517
        ea_ctrl   <= latch_ea;
6518
                                        -- if bit 4 of ea set, add accd to md
6519
        left_ctrl <= accd_left;
6520
        if ea(4) = '1' then
6521
          right_ctrl <= md_right;
6522
        else
6523
          right_ctrl <= zero_right;
6524
        end if;
6525
        alu_ctrl     <= alu_mul;
6526
        cc_ctrl      <= load_cc;
6527
        acca_ctrl    <= load_hi_acca;
6528
        accb_ctrl    <= load_accb;
6529
        md_ctrl      <= shiftl_md;
6530
                                        -- idle bus
6531
        addr_ctrl    <= idle_ad;
6532
        dout_ctrl    <= md_lo_dout;
6533
                                        --
6534
        st_ctrl      <= idle_st;
6535
        return_state <= fetch_state;
6536
        next_state   <= mul5_state;
6537
 
6538
      when mul5_state =>
6539
        -- default
6540
        ix_ctrl   <= latch_ix;
6541
        iy_ctrl   <= latch_iy;
6542
        up_ctrl   <= latch_up;
6543
        sp_ctrl   <= latch_sp;
6544
        pc_ctrl   <= latch_pc;
6545
        iv_ctrl   <= latch_iv;
6546
        dp_ctrl   <= latch_dp;
6547
        op_ctrl   <= latch_op;
6548
        pre_ctrl  <= latch_pre;
6549
        nmi_ctrl  <= latch_nmi;
6550
        ea_ctrl   <= latch_ea;
6551
                                        -- if bit 5 of ea set, add accd to md
6552
        left_ctrl <= accd_left;
6553
        if ea(5) = '1' then
6554
          right_ctrl <= md_right;
6555
        else
6556
          right_ctrl <= zero_right;
6557
        end if;
6558
        alu_ctrl     <= alu_mul;
6559
        cc_ctrl      <= load_cc;
6560
        acca_ctrl    <= load_hi_acca;
6561
        accb_ctrl    <= load_accb;
6562
        md_ctrl      <= shiftl_md;
6563
                                        -- idle bus
6564
        addr_ctrl    <= idle_ad;
6565
        dout_ctrl    <= md_lo_dout;
6566
                                        --
6567
        st_ctrl      <= idle_st;
6568
        return_state <= fetch_state;
6569
        next_state   <= mul6_state;
6570
 
6571
      when mul6_state =>
6572
        -- default
6573
        ix_ctrl   <= latch_ix;
6574
        iy_ctrl   <= latch_iy;
6575
        up_ctrl   <= latch_up;
6576
        sp_ctrl   <= latch_sp;
6577
        pc_ctrl   <= latch_pc;
6578
        iv_ctrl   <= latch_iv;
6579
        dp_ctrl   <= latch_dp;
6580
        op_ctrl   <= latch_op;
6581
        pre_ctrl  <= latch_pre;
6582
        nmi_ctrl  <= latch_nmi;
6583
        ea_ctrl   <= latch_ea;
6584
                                        -- if bit 6 of ea set, add accd to md
6585
        left_ctrl <= accd_left;
6586
        if ea(6) = '1' then
6587
          right_ctrl <= md_right;
6588
        else
6589
          right_ctrl <= zero_right;
6590
        end if;
6591
        alu_ctrl     <= alu_mul;
6592
        cc_ctrl      <= load_cc;
6593
        acca_ctrl    <= load_hi_acca;
6594
        accb_ctrl    <= load_accb;
6595
        md_ctrl      <= shiftl_md;
6596
                                        -- idle bus
6597
        addr_ctrl    <= idle_ad;
6598
        dout_ctrl    <= md_lo_dout;
6599
                                        --
6600
        st_ctrl      <= idle_st;
6601
        return_state <= fetch_state;
6602
        next_state   <= mul7_state;
6603
 
6604
      when mul7_state =>
6605
        -- default
6606
        ix_ctrl   <= latch_ix;
6607
        iy_ctrl   <= latch_iy;
6608
        up_ctrl   <= latch_up;
6609
        sp_ctrl   <= latch_sp;
6610
        pc_ctrl   <= latch_pc;
6611
        iv_ctrl   <= latch_iv;
6612
        dp_ctrl   <= latch_dp;
6613
        op_ctrl   <= latch_op;
6614
        pre_ctrl  <= latch_pre;
6615
        nmi_ctrl  <= latch_nmi;
6616
        ea_ctrl   <= latch_ea;
6617
                                        -- if bit 7 of ea set, add accd to md
6618
        left_ctrl <= accd_left;
6619
        if ea(7) = '1' then
6620
          right_ctrl <= md_right;
6621
        else
6622
          right_ctrl <= zero_right;
6623
        end if;
6624
        alu_ctrl     <= alu_mul;
6625
        cc_ctrl      <= load_cc;
6626
        acca_ctrl    <= load_hi_acca;
6627
        accb_ctrl    <= load_accb;
6628
        md_ctrl      <= shiftl_md;
6629
                                        -- idle bus
6630
        addr_ctrl    <= idle_ad;
6631
        dout_ctrl    <= md_lo_dout;
6632
                                        --
6633
        st_ctrl      <= idle_st;
6634
        return_state <= fetch_state;
6635
        next_state   <= fetch_state;
6636
 
6637
        --
6638
        -- Enter here on pushs
6639
        -- ea holds post byte
6640
        --
6641
      when pshs_state =>
6642
        -- default
6643
        cc_ctrl    <= latch_cc;
6644
        acca_ctrl  <= latch_acca;
6645
        accb_ctrl  <= latch_accb;
6646
        dp_ctrl    <= latch_dp;
6647
        ix_ctrl    <= latch_ix;
6648
        iy_ctrl    <= latch_iy;
6649
        up_ctrl    <= latch_up;
6650
        pc_ctrl    <= latch_pc;
6651
        md_ctrl    <= latch_md;
6652
        iv_ctrl    <= latch_iv;
6653
        dp_ctrl    <= latch_dp;
6654
        op_ctrl    <= latch_op;
6655
        pre_ctrl   <= latch_pre;
6656
        nmi_ctrl   <= latch_nmi;
6657
        ea_ctrl    <= latch_ea;
6658
        -- decrement sp if any registers to be pushed
6659
        left_ctrl  <= sp_left;
6660
        right_ctrl <= one_right;
6661
        alu_ctrl   <= alu_sub16;
6662
        if ea(7 downto 0) = "00000000" then
6663
          sp_ctrl <= latch_sp;
6664
        else
6665
          sp_ctrl <= load_sp;
6666
        end if;
6667
        -- write idle bus
6668
        addr_ctrl    <= idle_ad;
6669
        dout_ctrl    <= md_lo_dout;
6670
        --
6671
        st_ctrl      <= idle_st;
6672
        return_state <= fetch_state;
6673
        if ea(7) = '1' then
6674
          next_state <= pshs_pcl_state;
6675
        elsif ea(6) = '1' then
6676
          next_state <= pshs_upl_state;
6677
        elsif ea(5) = '1' then
6678
          next_state <= pshs_iyl_state;
6679
        elsif ea(4) = '1' then
6680
          next_state <= pshs_ixl_state;
6681
        elsif ea(3) = '1' then
6682
          next_state <= pshs_dp_state;
6683
        elsif ea(2) = '1' then
6684
          next_state <= pshs_accb_state;
6685
        elsif ea(1) = '1' then
6686
          next_state <= pshs_acca_state;
6687
        elsif ea(0) = '1' then
6688
          next_state <= pshs_cc_state;
6689
        else
6690
          next_state <= fetch_state;
6691
        end if;
6692
 
6693
      when pshs_pcl_state =>
6694
        -- default
6695
        cc_ctrl      <= latch_cc;
6696
        acca_ctrl    <= latch_acca;
6697
        accb_ctrl    <= latch_accb;
6698
        dp_ctrl      <= latch_dp;
6699
        ix_ctrl      <= latch_ix;
6700
        iy_ctrl      <= latch_iy;
6701
        up_ctrl      <= latch_up;
6702
        pc_ctrl      <= latch_pc;
6703
        md_ctrl      <= latch_md;
6704
        iv_ctrl      <= latch_iv;
6705
        dp_ctrl      <= latch_dp;
6706
        op_ctrl      <= latch_op;
6707
        pre_ctrl     <= latch_pre;
6708
        nmi_ctrl     <= latch_nmi;
6709
        ea_ctrl      <= latch_ea;
6710
        -- decrement sp
6711
        left_ctrl    <= sp_left;
6712
        right_ctrl   <= one_right;
6713
        alu_ctrl     <= alu_sub16;
6714
        sp_ctrl      <= load_sp;
6715
        -- write pc low
6716
        addr_ctrl    <= pushs_ad;
6717
        dout_ctrl    <= pc_lo_dout;
6718
        --
6719
        st_ctrl      <= idle_st;
6720
        return_state <= fetch_state;
6721
        next_state   <= pshs_pch_state;
6722
 
6723
      when pshs_pch_state =>
6724
        cc_ctrl    <= latch_cc;
6725
        acca_ctrl  <= latch_acca;
6726
        accb_ctrl  <= latch_accb;
6727
        dp_ctrl    <= latch_dp;
6728
        ix_ctrl    <= latch_ix;
6729
        iy_ctrl    <= latch_iy;
6730
        up_ctrl    <= latch_up;
6731
        pc_ctrl    <= latch_pc;
6732
        md_ctrl    <= latch_md;
6733
        iv_ctrl    <= latch_iv;
6734
        dp_ctrl    <= latch_dp;
6735
        op_ctrl    <= latch_op;
6736
        pre_ctrl   <= latch_pre;
6737
        nmi_ctrl   <= latch_nmi;
6738
        ea_ctrl    <= latch_ea;
6739
        -- decrement sp
6740
        left_ctrl  <= sp_left;
6741
        right_ctrl <= one_right;
6742
        alu_ctrl   <= alu_sub16;
6743
        if ea(6 downto 0) = "0000000" then
6744
          sp_ctrl <= latch_sp;
6745
        else
6746
          sp_ctrl <= load_sp;
6747
        end if;
6748
        -- write pc hi
6749
        addr_ctrl    <= pushs_ad;
6750
        dout_ctrl    <= pc_hi_dout;
6751
        --
6752
        st_ctrl      <= idle_st;
6753
        return_state <= fetch_state;
6754
        if ea(6) = '1' then
6755
          next_state <= pshs_upl_state;
6756
        elsif ea(5) = '1' then
6757
          next_state <= pshs_iyl_state;
6758
        elsif ea(4) = '1' then
6759
          next_state <= pshs_ixl_state;
6760
        elsif ea(3) = '1' then
6761
          next_state <= pshs_dp_state;
6762
        elsif ea(2) = '1' then
6763
          next_state <= pshs_accb_state;
6764
        elsif ea(1) = '1' then
6765
          next_state <= pshs_acca_state;
6766
        elsif ea(0) = '1' then
6767
          next_state <= pshs_cc_state;
6768
        else
6769
          next_state <= fetch_state;
6770
        end if;
6771
 
6772
 
6773
      when pshs_upl_state =>
6774
        -- default
6775
        cc_ctrl      <= latch_cc;
6776
        acca_ctrl    <= latch_acca;
6777
        accb_ctrl    <= latch_accb;
6778
        dp_ctrl      <= latch_dp;
6779
        ix_ctrl      <= latch_ix;
6780
        iy_ctrl      <= latch_iy;
6781
        up_ctrl      <= latch_up;
6782
        pc_ctrl      <= latch_pc;
6783
        md_ctrl      <= latch_md;
6784
        iv_ctrl      <= latch_iv;
6785
        op_ctrl      <= latch_op;
6786
        pre_ctrl     <= latch_pre;
6787
        nmi_ctrl     <= latch_nmi;
6788
        ea_ctrl      <= latch_ea;
6789
        -- decrement sp
6790
        left_ctrl    <= sp_left;
6791
        right_ctrl   <= one_right;
6792
        alu_ctrl     <= alu_sub16;
6793
        sp_ctrl      <= load_sp;
6794
        -- write pc low
6795
        addr_ctrl    <= pushs_ad;
6796
        dout_ctrl    <= up_lo_dout;
6797
        --
6798
        st_ctrl      <= idle_st;
6799
        return_state <= fetch_state;
6800
        next_state   <= pshs_uph_state;
6801
 
6802
      when pshs_uph_state =>
6803
        cc_ctrl    <= latch_cc;
6804
        acca_ctrl  <= latch_acca;
6805
        accb_ctrl  <= latch_accb;
6806
        dp_ctrl    <= latch_dp;
6807
        ix_ctrl    <= latch_ix;
6808
        iy_ctrl    <= latch_iy;
6809
        up_ctrl    <= latch_up;
6810
        pc_ctrl    <= latch_pc;
6811
        md_ctrl    <= latch_md;
6812
        iv_ctrl    <= latch_iv;
6813
        op_ctrl    <= latch_op;
6814
        pre_ctrl   <= latch_pre;
6815
        nmi_ctrl   <= latch_nmi;
6816
        ea_ctrl    <= latch_ea;
6817
        -- decrement sp
6818
        left_ctrl  <= sp_left;
6819
        right_ctrl <= one_right;
6820
        alu_ctrl   <= alu_sub16;
6821
        if ea(5 downto 0) = "000000" then
6822
          sp_ctrl <= latch_sp;
6823
        else
6824
          sp_ctrl <= load_sp;
6825
        end if;
6826
        -- write pc hi
6827
        addr_ctrl    <= pushs_ad;
6828
        dout_ctrl    <= up_hi_dout;
6829
        --
6830
        st_ctrl      <= idle_st;
6831
        return_state <= fetch_state;
6832
        if ea(5) = '1' then
6833
          next_state <= pshs_iyl_state;
6834
        elsif ea(4) = '1' then
6835
          next_state <= pshs_ixl_state;
6836
        elsif ea(3) = '1' then
6837
          next_state <= pshs_dp_state;
6838
        elsif ea(2) = '1' then
6839
          next_state <= pshs_accb_state;
6840
        elsif ea(1) = '1' then
6841
          next_state <= pshs_acca_state;
6842
        elsif ea(0) = '1' then
6843
          next_state <= pshs_cc_state;
6844
        else
6845
          next_state <= fetch_state;
6846
        end if;
6847
 
6848
      when pshs_iyl_state =>
6849
        -- default
6850
        cc_ctrl      <= latch_cc;
6851
        acca_ctrl    <= latch_acca;
6852
        accb_ctrl    <= latch_accb;
6853
        dp_ctrl      <= latch_dp;
6854
        ix_ctrl      <= latch_ix;
6855
        iy_ctrl      <= latch_iy;
6856
        up_ctrl      <= latch_up;
6857
        pc_ctrl      <= latch_pc;
6858
        md_ctrl      <= latch_md;
6859
        iv_ctrl      <= latch_iv;
6860
        op_ctrl      <= latch_op;
6861
        pre_ctrl     <= latch_pre;
6862
        nmi_ctrl     <= latch_nmi;
6863
        ea_ctrl      <= latch_ea;
6864
        -- decrement sp
6865
        left_ctrl    <= sp_left;
6866
        right_ctrl   <= one_right;
6867
        alu_ctrl     <= alu_sub16;
6868
        sp_ctrl      <= load_sp;
6869
        -- write iy low
6870
        addr_ctrl    <= pushs_ad;
6871
        dout_ctrl    <= iy_lo_dout;
6872
        --
6873
        st_ctrl      <= idle_st;
6874
        return_state <= fetch_state;
6875
        next_state   <= pshs_iyh_state;
6876
 
6877
      when pshs_iyh_state =>
6878
        -- default registers
6879
        cc_ctrl    <= latch_cc;
6880
        acca_ctrl  <= latch_acca;
6881
        accb_ctrl  <= latch_accb;
6882
        dp_ctrl    <= latch_dp;
6883
        ix_ctrl    <= latch_ix;
6884
        iy_ctrl    <= latch_iy;
6885
        up_ctrl    <= latch_up;
6886
        pc_ctrl    <= latch_pc;
6887
        md_ctrl    <= latch_md;
6888
        iv_ctrl    <= latch_iv;
6889
        op_ctrl    <= latch_op;
6890
        pre_ctrl   <= latch_pre;
6891
        nmi_ctrl   <= latch_nmi;
6892
        ea_ctrl    <= latch_ea;
6893
        -- decrement sp
6894
        left_ctrl  <= sp_left;
6895
        right_ctrl <= one_right;
6896
        alu_ctrl   <= alu_sub16;
6897
        if ea(4 downto 0) = "00000" then
6898
          sp_ctrl <= latch_sp;
6899
        else
6900
          sp_ctrl <= load_sp;
6901
        end if;
6902
        -- write iy hi
6903
        addr_ctrl    <= pushs_ad;
6904
        dout_ctrl    <= iy_hi_dout;
6905
        --
6906
        st_ctrl      <= idle_st;
6907
        return_state <= fetch_state;
6908
        if ea(4) = '1' then
6909
          next_state <= pshs_ixl_state;
6910
        elsif ea(3) = '1' then
6911
          next_state <= pshs_dp_state;
6912
        elsif ea(2) = '1' then
6913
          next_state <= pshs_accb_state;
6914
        elsif ea(1) = '1' then
6915
          next_state <= pshs_acca_state;
6916
        elsif ea(0) = '1' then
6917
          next_state <= pshs_cc_state;
6918
        else
6919
          next_state <= fetch_state;
6920
        end if;
6921
 
6922
      when pshs_ixl_state =>
6923
        -- default
6924
        cc_ctrl      <= latch_cc;
6925
        acca_ctrl    <= latch_acca;
6926
        accb_ctrl    <= latch_accb;
6927
        dp_ctrl      <= latch_dp;
6928
        ix_ctrl      <= latch_ix;
6929
        iy_ctrl      <= latch_iy;
6930
        up_ctrl      <= latch_up;
6931
        pc_ctrl      <= latch_pc;
6932
        md_ctrl      <= latch_md;
6933
        iv_ctrl      <= latch_iv;
6934
        op_ctrl      <= latch_op;
6935
        pre_ctrl     <= latch_pre;
6936
        nmi_ctrl     <= latch_nmi;
6937
        ea_ctrl      <= latch_ea;
6938
        -- decrement sp
6939
        left_ctrl    <= sp_left;
6940
        right_ctrl   <= one_right;
6941
        alu_ctrl     <= alu_sub16;
6942
        sp_ctrl      <= load_sp;
6943
        -- write ix low
6944
        addr_ctrl    <= pushs_ad;
6945
        dout_ctrl    <= ix_lo_dout;
6946
        --
6947
        st_ctrl      <= idle_st;
6948
        return_state <= fetch_state;
6949
        next_state   <= pshs_ixh_state;
6950
 
6951
      when pshs_ixh_state =>
6952
        -- default registers
6953
        cc_ctrl    <= latch_cc;
6954
        acca_ctrl  <= latch_acca;
6955
        accb_ctrl  <= latch_accb;
6956
        dp_ctrl    <= latch_dp;
6957
        ix_ctrl    <= latch_ix;
6958
        iy_ctrl    <= latch_iy;
6959
        up_ctrl    <= latch_up;
6960
        pc_ctrl    <= latch_pc;
6961
        md_ctrl    <= latch_md;
6962
        iv_ctrl    <= latch_iv;
6963
        op_ctrl    <= latch_op;
6964
        pre_ctrl   <= latch_pre;
6965
        nmi_ctrl   <= latch_nmi;
6966
        ea_ctrl    <= latch_ea;
6967
        -- decrement sp
6968
        left_ctrl  <= sp_left;
6969
        right_ctrl <= one_right;
6970
        alu_ctrl   <= alu_sub16;
6971
        if ea(3 downto 0) = "0000" then
6972
          sp_ctrl <= latch_sp;
6973
        else
6974
          sp_ctrl <= load_sp;
6975
        end if;
6976
        -- write ix hi
6977
        addr_ctrl    <= pushs_ad;
6978
        dout_ctrl    <= ix_hi_dout;
6979
        --
6980
        st_ctrl      <= idle_st;
6981
        return_state <= fetch_state;
6982
        if ea(3) = '1' then
6983
          next_state <= pshs_dp_state;
6984
        elsif ea(2) = '1' then
6985
          next_state <= pshs_accb_state;
6986
        elsif ea(1) = '1' then
6987
          next_state <= pshs_acca_state;
6988
        elsif ea(0) = '1' then
6989
          next_state <= pshs_cc_state;
6990
        else
6991
          next_state <= fetch_state;
6992
        end if;
6993
 
6994
      when pshs_dp_state =>
6995
        -- default registers
6996
        cc_ctrl    <= latch_cc;
6997
        acca_ctrl  <= latch_acca;
6998
        accb_ctrl  <= latch_accb;
6999
        dp_ctrl    <= latch_dp;
7000
        ix_ctrl    <= latch_ix;
7001
        iy_ctrl    <= latch_iy;
7002
        up_ctrl    <= latch_up;
7003
        pc_ctrl    <= latch_pc;
7004
        md_ctrl    <= latch_md;
7005
        iv_ctrl    <= latch_iv;
7006
        op_ctrl    <= latch_op;
7007
        pre_ctrl   <= latch_pre;
7008
        nmi_ctrl   <= latch_nmi;
7009
        ea_ctrl    <= latch_ea;
7010
        -- decrement sp
7011
        left_ctrl  <= sp_left;
7012
        right_ctrl <= one_right;
7013
        alu_ctrl   <= alu_sub16;
7014
        if ea(2 downto 0) = "000" then
7015
          sp_ctrl <= latch_sp;
7016
        else
7017
          sp_ctrl <= load_sp;
7018
        end if;
7019
        -- write dp
7020
        addr_ctrl    <= pushs_ad;
7021
        dout_ctrl    <= dp_dout;
7022
        --
7023
        st_ctrl      <= idle_st;
7024
        return_state <= fetch_state;
7025
        if ea(2) = '1' then
7026
          next_state <= pshs_accb_state;
7027
        elsif ea(1) = '1' then
7028
          next_state <= pshs_acca_state;
7029
        elsif ea(0) = '1' then
7030
          next_state <= pshs_cc_state;
7031
        else
7032
          next_state <= fetch_state;
7033
        end if;
7034
 
7035
      when pshs_accb_state =>
7036
        -- default registers
7037
        cc_ctrl    <= latch_cc;
7038
        acca_ctrl  <= latch_acca;
7039
        accb_ctrl  <= latch_accb;
7040
        dp_ctrl    <= latch_dp;
7041
        ix_ctrl    <= latch_ix;
7042
        iy_ctrl    <= latch_iy;
7043
        up_ctrl    <= latch_up;
7044
        pc_ctrl    <= latch_pc;
7045
        md_ctrl    <= latch_md;
7046
        iv_ctrl    <= latch_iv;
7047
        op_ctrl    <= latch_op;
7048
        pre_ctrl   <= latch_pre;
7049
        nmi_ctrl   <= latch_nmi;
7050
        ea_ctrl    <= latch_ea;
7051
        -- decrement sp
7052
        left_ctrl  <= sp_left;
7053
        right_ctrl <= one_right;
7054
        alu_ctrl   <= alu_sub16;
7055
        if ea(1 downto 0) = "00" then
7056
          sp_ctrl <= latch_sp;
7057
        else
7058
          sp_ctrl <= load_sp;
7059
        end if;
7060
        -- write accb
7061
        addr_ctrl    <= pushs_ad;
7062
        dout_ctrl    <= accb_dout;
7063
        --
7064
        st_ctrl      <= idle_st;
7065
        return_state <= fetch_state;
7066
        if ea(1) = '1' then
7067
          next_state <= pshs_acca_state;
7068
        elsif ea(0) = '1' then
7069
          next_state <= pshs_cc_state;
7070
        else
7071
          next_state <= fetch_state;
7072
        end if;
7073
 
7074
      when pshs_acca_state =>
7075
        -- default registers
7076
        cc_ctrl    <= latch_cc;
7077
        acca_ctrl  <= latch_acca;
7078
        accb_ctrl  <= latch_accb;
7079
        dp_ctrl    <= latch_dp;
7080
        ix_ctrl    <= latch_ix;
7081
        iy_ctrl    <= latch_iy;
7082
        up_ctrl    <= latch_up;
7083
        pc_ctrl    <= latch_pc;
7084
        md_ctrl    <= latch_md;
7085
        iv_ctrl    <= latch_iv;
7086
        op_ctrl    <= latch_op;
7087
        pre_ctrl   <= latch_pre;
7088
        nmi_ctrl   <= latch_nmi;
7089
        ea_ctrl    <= latch_ea;
7090
        -- decrement sp
7091
        left_ctrl  <= sp_left;
7092
        right_ctrl <= one_right;
7093
        alu_ctrl   <= alu_sub16;
7094
        if ea(0) = '1' then
7095
          sp_ctrl <= load_sp;
7096
        else
7097
          sp_ctrl <= latch_sp;
7098
        end if;
7099
        -- write acca
7100
        addr_ctrl    <= pushs_ad;
7101
        dout_ctrl    <= acca_dout;
7102
        --
7103
        st_ctrl      <= idle_st;
7104
        return_state <= fetch_state;
7105
        if ea(0) = '1' then
7106
          next_state <= pshs_cc_state;
7107
        else
7108
          next_state <= fetch_state;
7109
        end if;
7110
 
7111
      when pshs_cc_state =>
7112
        -- default registers
7113
        cc_ctrl      <= latch_cc;
7114
        acca_ctrl    <= latch_acca;
7115
        accb_ctrl    <= latch_accb;
7116
        dp_ctrl      <= latch_dp;
7117
        ix_ctrl      <= latch_ix;
7118
        iy_ctrl      <= latch_iy;
7119
        up_ctrl      <= latch_up;
7120
        pc_ctrl      <= latch_pc;
7121
        md_ctrl      <= latch_md;
7122
        iv_ctrl      <= latch_iv;
7123
        op_ctrl      <= latch_op;
7124
        pre_ctrl     <= latch_pre;
7125
        nmi_ctrl     <= latch_nmi;
7126
        ea_ctrl      <= latch_ea;
7127
        -- idle sp
7128
        left_ctrl    <= sp_left;
7129
        right_ctrl   <= one_right;
7130
        alu_ctrl     <= alu_nop;
7131
        sp_ctrl      <= latch_sp;
7132
        -- write cc
7133
        addr_ctrl    <= pushs_ad;
7134
        dout_ctrl    <= cc_dout;
7135
        --
7136
        st_ctrl      <= idle_st;
7137
        return_state <= fetch_state;
7138
        next_state   <= fetch_state;
7139
 
7140
        --
7141
        -- enter here on PULS
7142
        -- ea hold register mask
7143
        --
7144
      when puls_state =>
7145
        -- default registers
7146
        cc_ctrl      <= latch_cc;
7147
        acca_ctrl    <= latch_acca;
7148
        accb_ctrl    <= latch_accb;
7149
        dp_ctrl      <= latch_dp;
7150
        ix_ctrl      <= latch_ix;
7151
        iy_ctrl      <= latch_iy;
7152
        up_ctrl      <= latch_up;
7153
        pc_ctrl      <= latch_pc;
7154
        md_ctrl      <= latch_md;
7155
        iv_ctrl      <= latch_iv;
7156
        op_ctrl      <= latch_op;
7157
        pre_ctrl     <= latch_pre;
7158
        nmi_ctrl     <= latch_nmi;
7159
        ea_ctrl      <= latch_ea;
7160
        -- idle SP
7161
        left_ctrl    <= sp_left;
7162
        right_ctrl   <= one_right;
7163
        alu_ctrl     <= alu_add16;
7164
        sp_ctrl      <= latch_sp;
7165
        -- idle bus
7166
        addr_ctrl    <= idle_ad;
7167
        dout_ctrl    <= md_lo_dout;
7168
        --
7169
        st_ctrl      <= idle_st;
7170
        return_state <= fetch_state;
7171
        if ea(0) = '1' then
7172
          next_state <= puls_cc_state;
7173
        elsif ea(1) = '1' then
7174
          next_state <= puls_acca_state;
7175
        elsif ea(2) = '1' then
7176
          next_state <= puls_accb_state;
7177
        elsif ea(3) = '1' then
7178
          next_state <= puls_dp_state;
7179
        elsif ea(4) = '1' then
7180
          next_state <= puls_ixh_state;
7181
        elsif ea(5) = '1' then
7182
          next_state <= puls_iyh_state;
7183
        elsif ea(6) = '1' then
7184
          next_state <= puls_uph_state;
7185
        elsif ea(7) = '1' then
7186
          next_state <= puls_pch_state;
7187
        else
7188
          next_state <= fetch_state;
7189
        end if;
7190
 
7191
      when puls_cc_state =>
7192
        -- default registers
7193
        acca_ctrl    <= latch_acca;
7194
        accb_ctrl    <= latch_accb;
7195
        dp_ctrl      <= latch_dp;
7196
        ix_ctrl      <= latch_ix;
7197
        iy_ctrl      <= latch_iy;
7198
        up_ctrl      <= latch_up;
7199
        pc_ctrl      <= latch_pc;
7200
        md_ctrl      <= latch_md;
7201
        iv_ctrl      <= latch_iv;
7202
        op_ctrl      <= latch_op;
7203
        pre_ctrl     <= latch_pre;
7204
        nmi_ctrl     <= latch_nmi;
7205
        ea_ctrl      <= latch_ea;
7206
        -- Increment SP
7207
        left_ctrl    <= sp_left;
7208
        right_ctrl   <= one_right;
7209
        alu_ctrl     <= alu_add16;
7210
        sp_ctrl      <= load_sp;
7211
        -- read cc
7212
        cc_ctrl      <= pull_cc;
7213
        addr_ctrl    <= pulls_ad;
7214
        dout_ctrl    <= cc_dout;
7215
        --
7216
        st_ctrl      <= idle_st;
7217
        return_state <= fetch_state;
7218
        if ea(1) = '1' then
7219
          next_state <= puls_acca_state;
7220
        elsif ea(2) = '1' then
7221
          next_state <= puls_accb_state;
7222
        elsif ea(3) = '1' then
7223
          next_state <= puls_dp_state;
7224
        elsif ea(4) = '1' then
7225
          next_state <= puls_ixh_state;
7226
        elsif ea(5) = '1' then
7227
          next_state <= puls_iyh_state;
7228
        elsif ea(6) = '1' then
7229
          next_state <= puls_uph_state;
7230
        elsif ea(7) = '1' then
7231
          next_state <= puls_pch_state;
7232
        else
7233
          next_state <= fetch_state;
7234
        end if;
7235
 
7236
      when puls_acca_state =>
7237
        -- default registers
7238
        cc_ctrl      <= latch_cc;
7239
        accb_ctrl    <= latch_accb;
7240
        dp_ctrl      <= latch_dp;
7241
        ix_ctrl      <= latch_ix;
7242
        iy_ctrl      <= latch_iy;
7243
        up_ctrl      <= latch_up;
7244
        pc_ctrl      <= latch_pc;
7245
        md_ctrl      <= latch_md;
7246
        iv_ctrl      <= latch_iv;
7247
        op_ctrl      <= latch_op;
7248
        pre_ctrl     <= latch_pre;
7249
        nmi_ctrl     <= latch_nmi;
7250
        ea_ctrl      <= latch_ea;
7251
        -- Increment SP
7252
        left_ctrl    <= sp_left;
7253
        right_ctrl   <= one_right;
7254
        alu_ctrl     <= alu_add16;
7255
        sp_ctrl      <= load_sp;
7256
        -- read acca
7257
        acca_ctrl    <= pull_acca;
7258
        addr_ctrl    <= pulls_ad;
7259
        dout_ctrl    <= acca_dout;
7260
        --
7261
        st_ctrl      <= idle_st;
7262
        return_state <= fetch_state;
7263
        if ea(2) = '1' then
7264
          next_state <= puls_accb_state;
7265
        elsif ea(3) = '1' then
7266
          next_state <= puls_dp_state;
7267
        elsif ea(4) = '1' then
7268
          next_state <= puls_ixh_state;
7269
        elsif ea(5) = '1' then
7270
          next_state <= puls_iyh_state;
7271
        elsif ea(6) = '1' then
7272
          next_state <= puls_uph_state;
7273
        elsif ea(7) = '1' then
7274
          next_state <= puls_pch_state;
7275
        else
7276
          next_state <= fetch_state;
7277
        end if;
7278
 
7279
      when puls_accb_state =>
7280
        -- default
7281
        cc_ctrl      <= latch_cc;
7282
        acca_ctrl    <= latch_acca;
7283
        dp_ctrl      <= latch_dp;
7284
        ix_ctrl      <= latch_ix;
7285
        iy_ctrl      <= latch_iy;
7286
        up_ctrl      <= latch_up;
7287
        pc_ctrl      <= latch_pc;
7288
        md_ctrl      <= latch_md;
7289
        iv_ctrl      <= latch_iv;
7290
        op_ctrl      <= latch_op;
7291
        pre_ctrl     <= latch_pre;
7292
        nmi_ctrl     <= latch_nmi;
7293
        ea_ctrl      <= latch_ea;
7294
        -- Increment SP
7295
        left_ctrl    <= sp_left;
7296
        right_ctrl   <= one_right;
7297
        alu_ctrl     <= alu_add16;
7298
        sp_ctrl      <= load_sp;
7299
        -- read accb
7300
        accb_ctrl    <= pull_accb;
7301
        addr_ctrl    <= pulls_ad;
7302
        dout_ctrl    <= accb_dout;
7303
        --
7304
        st_ctrl      <= idle_st;
7305
        return_state <= fetch_state;
7306
        if ea(3) = '1' then
7307
          next_state <= puls_dp_state;
7308
        elsif ea(4) = '1' then
7309
          next_state <= puls_ixh_state;
7310
        elsif ea(5) = '1' then
7311
          next_state <= puls_iyh_state;
7312
        elsif ea(6) = '1' then
7313
          next_state <= puls_uph_state;
7314
        elsif ea(7) = '1' then
7315
          next_state <= puls_pch_state;
7316
        else
7317
          next_state <= fetch_state;
7318
        end if;
7319
 
7320
      when puls_dp_state =>
7321
        -- default
7322
        cc_ctrl      <= latch_cc;
7323
        acca_ctrl    <= latch_acca;
7324
        accb_ctrl    <= latch_accb;
7325
        ix_ctrl      <= latch_ix;
7326
        iy_ctrl      <= latch_iy;
7327
        up_ctrl      <= latch_up;
7328
        pc_ctrl      <= latch_pc;
7329
        md_ctrl      <= latch_md;
7330
        iv_ctrl      <= latch_iv;
7331
        op_ctrl      <= latch_op;
7332
        pre_ctrl     <= latch_pre;
7333
        nmi_ctrl     <= latch_nmi;
7334
        ea_ctrl      <= latch_ea;
7335
        -- idle sp
7336
        left_ctrl    <= sp_left;
7337
        right_ctrl   <= one_right;
7338
        alu_ctrl     <= alu_add16;
7339
        sp_ctrl      <= load_sp;
7340
        -- read dp
7341
        dp_ctrl      <= pull_dp;
7342
        addr_ctrl    <= pulls_ad;
7343
        dout_ctrl    <= dp_dout;
7344
        --
7345
        st_ctrl      <= idle_st;
7346
        return_state <= fetch_state;
7347
        if ea(4) = '1' then
7348
          next_state <= puls_ixh_state;
7349
        elsif ea(5) = '1' then
7350
          next_state <= puls_iyh_state;
7351
        elsif ea(6) = '1' then
7352
          next_state <= puls_uph_state;
7353
        elsif ea(7) = '1' then
7354
          next_state <= puls_pch_state;
7355
        else
7356
          next_state <= fetch_state;
7357
        end if;
7358
 
7359
      when puls_ixh_state =>
7360
        -- default
7361
        cc_ctrl      <= latch_cc;
7362
        acca_ctrl    <= latch_acca;
7363
        accb_ctrl    <= latch_accb;
7364
        dp_ctrl      <= latch_dp;
7365
        iy_ctrl      <= latch_iy;
7366
        up_ctrl      <= latch_up;
7367
        pc_ctrl      <= latch_pc;
7368
        md_ctrl      <= latch_md;
7369
        iv_ctrl      <= latch_iv;
7370
        op_ctrl      <= latch_op;
7371
        pre_ctrl     <= latch_pre;
7372
        nmi_ctrl     <= latch_nmi;
7373
        ea_ctrl      <= latch_ea;
7374
        -- increment sp
7375
        left_ctrl    <= sp_left;
7376
        right_ctrl   <= one_right;
7377
        alu_ctrl     <= alu_add16;
7378
        sp_ctrl      <= load_sp;
7379
        -- pull ix hi
7380
        ix_ctrl      <= pull_hi_ix;
7381
        addr_ctrl    <= pulls_ad;
7382
        dout_ctrl    <= ix_hi_dout;
7383
        --
7384
        st_ctrl      <= idle_st;
7385
        return_state <= fetch_state;
7386
        next_state   <= puls_ixl_state;
7387
 
7388
      when puls_ixl_state =>
7389
        -- default
7390
        cc_ctrl      <= latch_cc;
7391
        acca_ctrl    <= latch_acca;
7392
        accb_ctrl    <= latch_accb;
7393
        dp_ctrl      <= latch_dp;
7394
        iy_ctrl      <= latch_iy;
7395
        up_ctrl      <= latch_up;
7396
        pc_ctrl      <= latch_pc;
7397
        md_ctrl      <= latch_md;
7398
        iv_ctrl      <= latch_iv;
7399
        op_ctrl      <= latch_op;
7400
        pre_ctrl     <= latch_pre;
7401
        nmi_ctrl     <= latch_nmi;
7402
        ea_ctrl      <= latch_ea;
7403
        -- idle sp
7404
        left_ctrl    <= sp_left;
7405
        right_ctrl   <= one_right;
7406
        alu_ctrl     <= alu_add16;
7407
        sp_ctrl      <= load_sp;
7408
        -- read ix low
7409
        ix_ctrl      <= pull_lo_ix;
7410
        addr_ctrl    <= pulls_ad;
7411
        dout_ctrl    <= ix_lo_dout;
7412
        --
7413
        st_ctrl      <= idle_st;
7414
        return_state <= fetch_state;
7415
        if ea(5) = '1' then
7416
          next_state <= puls_iyh_state;
7417
        elsif ea(6) = '1' then
7418
          next_state <= puls_uph_state;
7419
        elsif ea(7) = '1' then
7420
          next_state <= puls_pch_state;
7421
        else
7422
          next_state <= fetch_state;
7423
        end if;
7424
 
7425
      when puls_iyh_state =>
7426
        -- default
7427
        cc_ctrl      <= latch_cc;
7428
        acca_ctrl    <= latch_acca;
7429
        accb_ctrl    <= latch_accb;
7430
        dp_ctrl      <= latch_dp;
7431
        ix_ctrl      <= latch_ix;
7432
        up_ctrl      <= latch_up;
7433
        pc_ctrl      <= latch_pc;
7434
        md_ctrl      <= latch_md;
7435
        iv_ctrl      <= latch_iv;
7436
        op_ctrl      <= latch_op;
7437
        pre_ctrl     <= latch_pre;
7438
        nmi_ctrl     <= latch_nmi;
7439
        ea_ctrl      <= latch_ea;
7440
        -- increment sp
7441
        left_ctrl    <= sp_left;
7442
        right_ctrl   <= one_right;
7443
        alu_ctrl     <= alu_add16;
7444
        sp_ctrl      <= load_sp;
7445
        -- pull iy hi
7446
        iy_ctrl      <= pull_hi_iy;
7447
        addr_ctrl    <= pulls_ad;
7448
        dout_ctrl    <= iy_hi_dout;
7449
        --
7450
        st_ctrl      <= idle_st;
7451
        return_state <= fetch_state;
7452
        next_state   <= puls_iyl_state;
7453
 
7454
      when puls_iyl_state =>
7455
        -- default
7456
        cc_ctrl      <= latch_cc;
7457
        acca_ctrl    <= latch_acca;
7458
        accb_ctrl    <= latch_accb;
7459
        dp_ctrl      <= latch_dp;
7460
        ix_ctrl      <= latch_ix;
7461
        up_ctrl      <= latch_up;
7462
        pc_ctrl      <= latch_pc;
7463
        md_ctrl      <= latch_md;
7464
        iv_ctrl      <= latch_iv;
7465
        op_ctrl      <= latch_op;
7466
        pre_ctrl     <= latch_pre;
7467
        nmi_ctrl     <= latch_nmi;
7468
        ea_ctrl      <= latch_ea;
7469
        -- increment sp
7470
        left_ctrl    <= sp_left;
7471
        right_ctrl   <= one_right;
7472
        alu_ctrl     <= alu_add16;
7473
        sp_ctrl      <= load_sp;
7474
        -- read iy low
7475
        iy_ctrl      <= pull_lo_iy;
7476
        addr_ctrl    <= pulls_ad;
7477
        dout_ctrl    <= iy_lo_dout;
7478
        --
7479
        st_ctrl      <= idle_st;
7480
        return_state <= fetch_state;
7481
        if ea(6) = '1' then
7482
          next_state <= puls_uph_state;
7483
        elsif ea(7) = '1' then
7484
          next_state <= puls_pch_state;
7485
        else
7486
          next_state <= fetch_state;
7487
        end if;
7488
 
7489
      when puls_uph_state =>
7490
        -- default
7491
        cc_ctrl      <= latch_cc;
7492
        acca_ctrl    <= latch_acca;
7493
        accb_ctrl    <= latch_accb;
7494
        dp_ctrl      <= latch_dp;
7495
        ix_ctrl      <= latch_ix;
7496
        iy_ctrl      <= latch_iy;
7497
        pc_ctrl      <= latch_pc;
7498
        md_ctrl      <= latch_md;
7499
        iv_ctrl      <= latch_iv;
7500
        op_ctrl      <= latch_op;
7501
        pre_ctrl     <= latch_pre;
7502
        nmi_ctrl     <= latch_nmi;
7503
        ea_ctrl      <= latch_ea;
7504
        -- increment sp
7505
        left_ctrl    <= sp_left;
7506
        right_ctrl   <= one_right;
7507
        alu_ctrl     <= alu_add16;
7508
        sp_ctrl      <= load_sp;
7509
        -- pull up hi
7510
        up_ctrl      <= pull_hi_up;
7511
        addr_ctrl    <= pulls_ad;
7512
        dout_ctrl    <= up_hi_dout;
7513
        --
7514
        st_ctrl      <= idle_st;
7515
        return_state <= fetch_state;
7516
        next_state   <= puls_upl_state;
7517
 
7518
      when puls_upl_state =>
7519
        -- default
7520
        cc_ctrl      <= latch_cc;
7521
        acca_ctrl    <= latch_acca;
7522
        accb_ctrl    <= latch_accb;
7523
        dp_ctrl      <= latch_dp;
7524
        ix_ctrl      <= latch_ix;
7525
        iy_ctrl      <= latch_iy;
7526
        pc_ctrl      <= latch_pc;
7527
        md_ctrl      <= latch_md;
7528
        iv_ctrl      <= latch_iv;
7529
        op_ctrl      <= latch_op;
7530
        pre_ctrl     <= latch_pre;
7531
        nmi_ctrl     <= latch_nmi;
7532
        ea_ctrl      <= latch_ea;
7533
        -- increment sp
7534
        left_ctrl    <= sp_left;
7535
        right_ctrl   <= one_right;
7536
        alu_ctrl     <= alu_add16;
7537
        sp_ctrl      <= load_sp;
7538
        -- read up low
7539
        up_ctrl      <= pull_lo_up;
7540
        addr_ctrl    <= pulls_ad;
7541
        dout_ctrl    <= up_lo_dout;
7542
        --
7543
        st_ctrl      <= idle_st;
7544
        return_state <= fetch_state;
7545
        if ea(7) = '1' then
7546
          next_state <= puls_pch_state;
7547
        else
7548
          next_state <= fetch_state;
7549
        end if;
7550
 
7551
      when puls_pch_state =>
7552
        -- default
7553
        cc_ctrl      <= latch_cc;
7554
        acca_ctrl    <= latch_acca;
7555
        accb_ctrl    <= latch_accb;
7556
        dp_ctrl      <= latch_dp;
7557
        ix_ctrl      <= latch_ix;
7558
        iy_ctrl      <= latch_iy;
7559
        up_ctrl      <= latch_up;
7560
        md_ctrl      <= latch_md;
7561
        iv_ctrl      <= latch_iv;
7562
        op_ctrl      <= latch_op;
7563
        pre_ctrl     <= latch_pre;
7564
        nmi_ctrl     <= latch_nmi;
7565
        ea_ctrl      <= latch_ea;
7566
        -- increment sp
7567
        left_ctrl    <= sp_left;
7568
        right_ctrl   <= one_right;
7569
        alu_ctrl     <= alu_add16;
7570
        sp_ctrl      <= load_sp;
7571
        -- pull pc hi
7572
        pc_ctrl      <= pull_hi_pc;
7573
        addr_ctrl    <= pulls_ad;
7574
        dout_ctrl    <= pc_hi_dout;
7575
        --
7576
        st_ctrl      <= idle_st;
7577
        return_state <= fetch_state;
7578
        next_state   <= puls_pcl_state;
7579
 
7580
      when puls_pcl_state =>
7581
        -- default
7582
        cc_ctrl      <= latch_cc;
7583
        acca_ctrl    <= latch_acca;
7584
        accb_ctrl    <= latch_accb;
7585
        dp_ctrl      <= latch_dp;
7586
        ix_ctrl      <= latch_ix;
7587
        iy_ctrl      <= latch_iy;
7588
        up_ctrl      <= latch_up;
7589
        md_ctrl      <= latch_md;
7590
        iv_ctrl      <= latch_iv;
7591
        op_ctrl      <= latch_op;
7592
        pre_ctrl     <= latch_pre;
7593
        nmi_ctrl     <= latch_nmi;
7594
        ea_ctrl      <= latch_ea;
7595
        -- increment sp
7596
        left_ctrl    <= sp_left;
7597
        right_ctrl   <= one_right;
7598
        alu_ctrl     <= alu_add16;
7599
        sp_ctrl      <= load_sp;
7600
        -- read pc low
7601
        pc_ctrl      <= pull_lo_pc;
7602
        addr_ctrl    <= pulls_ad;
7603
        dout_ctrl    <= pc_lo_dout;
7604
        --
7605
        st_ctrl      <= idle_st;
7606
        return_state <= fetch_state;
7607
        next_state   <= fetch_state;
7608
 
7609
        --
7610
        -- Enter here on pshu
7611
        -- ea holds post byte
7612
        --
7613
      when pshu_state =>
7614
        -- default
7615
        cc_ctrl    <= latch_cc;
7616
        acca_ctrl  <= latch_acca;
7617
        accb_ctrl  <= latch_accb;
7618
        dp_ctrl    <= latch_dp;
7619
        ix_ctrl    <= latch_ix;
7620
        iy_ctrl    <= latch_iy;
7621
        sp_ctrl    <= latch_sp;
7622
        pc_ctrl    <= latch_pc;
7623
        md_ctrl    <= latch_md;
7624
        iv_ctrl    <= latch_iv;
7625
        dp_ctrl    <= latch_dp;
7626
        op_ctrl    <= latch_op;
7627
        pre_ctrl   <= latch_pre;
7628
        nmi_ctrl   <= latch_nmi;
7629
        ea_ctrl    <= latch_ea;
7630
        -- decrement up if any registers to be pushed
7631
        left_ctrl  <= up_left;
7632
        right_ctrl <= one_right;
7633
        alu_ctrl   <= alu_sub16;
7634
        if ea(7 downto 0) = "00000000" then
7635
          up_ctrl <= latch_up;
7636
        else
7637
          up_ctrl <= load_up;
7638
        end if;
7639
        -- write idle bus
7640
        addr_ctrl    <= idle_ad;
7641
        dout_ctrl    <= md_lo_dout;
7642
        --
7643
        st_ctrl      <= idle_st;
7644
        return_state <= fetch_state;
7645
        if ea(7) = '1' then
7646
          next_state <= pshu_pcl_state;
7647
        elsif ea(6) = '1' then
7648
          next_state <= pshu_spl_state;
7649
        elsif ea(5) = '1' then
7650
          next_state <= pshu_iyl_state;
7651
        elsif ea(4) = '1' then
7652
          next_state <= pshu_ixl_state;
7653
        elsif ea(3) = '1' then
7654
          next_state <= pshu_dp_state;
7655
        elsif ea(2) = '1' then
7656
          next_state <= pshu_accb_state;
7657
        elsif ea(1) = '1' then
7658
          next_state <= pshu_acca_state;
7659
        elsif ea(0) = '1' then
7660
          next_state <= pshu_cc_state;
7661
        else
7662
          next_state <= fetch_state;
7663
        end if;
7664
        --
7665
        -- push PC onto U stack
7666
        --
7667
      when pshu_pcl_state =>
7668
        -- default
7669
        cc_ctrl      <= latch_cc;
7670
        acca_ctrl    <= latch_acca;
7671
        accb_ctrl    <= latch_accb;
7672
        dp_ctrl      <= latch_dp;
7673
        ix_ctrl      <= latch_ix;
7674
        iy_ctrl      <= latch_iy;
7675
        sp_ctrl      <= latch_sp;
7676
        pc_ctrl      <= latch_pc;
7677
        md_ctrl      <= latch_md;
7678
        iv_ctrl      <= latch_iv;
7679
        op_ctrl      <= latch_op;
7680
        pre_ctrl     <= latch_pre;
7681
        nmi_ctrl     <= latch_nmi;
7682
        ea_ctrl      <= latch_ea;
7683
        -- decrement up
7684
        left_ctrl    <= up_left;
7685
        right_ctrl   <= one_right;
7686
        alu_ctrl     <= alu_sub16;
7687
        up_ctrl      <= load_up;
7688
        -- write pc low
7689
        addr_ctrl    <= pushu_ad;
7690
        dout_ctrl    <= pc_lo_dout;
7691
        --
7692
        st_ctrl      <= idle_st;
7693
        return_state <= fetch_state;
7694
        next_state   <= pshu_pch_state;
7695
 
7696
      when pshu_pch_state =>
7697
        cc_ctrl    <= latch_cc;
7698
        acca_ctrl  <= latch_acca;
7699
        accb_ctrl  <= latch_accb;
7700
        dp_ctrl    <= latch_dp;
7701
        ix_ctrl    <= latch_ix;
7702
        iy_ctrl    <= latch_iy;
7703
        sp_ctrl    <= latch_sp;
7704
        pc_ctrl    <= latch_pc;
7705
        md_ctrl    <= latch_md;
7706
        iv_ctrl    <= latch_iv;
7707
        op_ctrl    <= latch_op;
7708
        pre_ctrl   <= latch_pre;
7709
        nmi_ctrl   <= latch_nmi;
7710
        ea_ctrl    <= latch_ea;
7711
        -- decrement up
7712
        left_ctrl  <= up_left;
7713
        right_ctrl <= one_right;
7714
        alu_ctrl   <= alu_sub16;
7715
        if ea(6 downto 0) = "0000000" then
7716
          up_ctrl <= latch_up;
7717
        else
7718
          up_ctrl <= load_up;
7719
        end if;
7720
        -- write pc hi
7721
        addr_ctrl    <= pushu_ad;
7722
        dout_ctrl    <= pc_hi_dout;
7723
        --
7724
        st_ctrl      <= idle_st;
7725
        return_state <= fetch_state;
7726
        if ea(6) = '1' then
7727
          next_state <= pshu_spl_state;
7728
        elsif ea(5) = '1' then
7729
          next_state <= pshu_iyl_state;
7730
        elsif ea(4) = '1' then
7731
          next_state <= pshu_ixl_state;
7732
        elsif ea(3) = '1' then
7733
          next_state <= pshu_dp_state;
7734
        elsif ea(2) = '1' then
7735
          next_state <= pshu_accb_state;
7736
        elsif ea(1) = '1' then
7737
          next_state <= pshu_acca_state;
7738
        elsif ea(0) = '1' then
7739
          next_state <= pshu_cc_state;
7740
        else
7741
          next_state <= fetch_state;
7742
        end if;
7743
 
7744
      when pshu_spl_state =>
7745
        -- default
7746
        cc_ctrl      <= latch_cc;
7747
        acca_ctrl    <= latch_acca;
7748
        accb_ctrl    <= latch_accb;
7749
        dp_ctrl      <= latch_dp;
7750
        ix_ctrl      <= latch_ix;
7751
        iy_ctrl      <= latch_iy;
7752
        sp_ctrl      <= latch_sp;
7753
        pc_ctrl      <= latch_pc;
7754
        md_ctrl      <= latch_md;
7755
        iv_ctrl      <= latch_iv;
7756
        op_ctrl      <= latch_op;
7757
        pre_ctrl     <= latch_pre;
7758
        nmi_ctrl     <= latch_nmi;
7759
        ea_ctrl      <= latch_ea;
7760
        -- decrement sp
7761
        left_ctrl    <= up_left;
7762
        right_ctrl   <= one_right;
7763
        alu_ctrl     <= alu_sub16;
7764
        up_ctrl      <= load_up;
7765
        -- write pc low
7766
        addr_ctrl    <= pushu_ad;
7767
        dout_ctrl    <= sp_lo_dout;
7768
        --
7769
        st_ctrl      <= idle_st;
7770
        return_state <= fetch_state;
7771
        next_state   <= pshu_sph_state;
7772
 
7773
      when pshu_sph_state =>
7774
        cc_ctrl    <= latch_cc;
7775
        acca_ctrl  <= latch_acca;
7776
        accb_ctrl  <= latch_accb;
7777
        dp_ctrl    <= latch_dp;
7778
        ix_ctrl    <= latch_ix;
7779
        iy_ctrl    <= latch_iy;
7780
        sp_ctrl    <= latch_sp;
7781
        pc_ctrl    <= latch_pc;
7782
        md_ctrl    <= latch_md;
7783
        iv_ctrl    <= latch_iv;
7784
        op_ctrl    <= latch_op;
7785
        pre_ctrl   <= latch_pre;
7786
        nmi_ctrl   <= latch_nmi;
7787
        ea_ctrl    <= latch_ea;
7788
        -- decrement sp
7789
        left_ctrl  <= up_left;
7790
        right_ctrl <= one_right;
7791
        alu_ctrl   <= alu_sub16;
7792
        if ea(5 downto 0) = "000000" then
7793
          up_ctrl <= latch_up;
7794
        else
7795
          up_ctrl <= load_up;
7796
        end if;
7797
        -- write sp hi
7798
        addr_ctrl    <= pushu_ad;
7799
        dout_ctrl    <= sp_hi_dout;
7800
        --
7801
        st_ctrl      <= idle_st;
7802
        return_state <= fetch_state;
7803
        if ea(5) = '1' then
7804
          next_state <= pshu_iyl_state;
7805
        elsif ea(4) = '1' then
7806
          next_state <= pshu_ixl_state;
7807
        elsif ea(3) = '1' then
7808
          next_state <= pshu_dp_state;
7809
        elsif ea(2) = '1' then
7810
          next_state <= pshu_accb_state;
7811
        elsif ea(1) = '1' then
7812
          next_state <= pshu_acca_state;
7813
        elsif ea(0) = '1' then
7814
          next_state <= pshu_cc_state;
7815
        else
7816
          next_state <= fetch_state;
7817
        end if;
7818
 
7819
      when pshu_iyl_state =>
7820
        -- default
7821
        cc_ctrl      <= latch_cc;
7822
        acca_ctrl    <= latch_acca;
7823
        accb_ctrl    <= latch_accb;
7824
        dp_ctrl      <= latch_dp;
7825
        ix_ctrl      <= latch_ix;
7826
        iy_ctrl      <= latch_iy;
7827
        sp_ctrl      <= latch_sp;
7828
        pc_ctrl      <= latch_pc;
7829
        md_ctrl      <= latch_md;
7830
        iv_ctrl      <= latch_iv;
7831
        op_ctrl      <= latch_op;
7832
        pre_ctrl     <= latch_pre;
7833
        nmi_ctrl     <= latch_nmi;
7834
        ea_ctrl      <= latch_ea;
7835
        -- decrement sp
7836
        left_ctrl    <= up_left;
7837
        right_ctrl   <= one_right;
7838
        alu_ctrl     <= alu_sub16;
7839
        up_ctrl      <= load_up;
7840
        -- write iy low
7841
        addr_ctrl    <= pushu_ad;
7842
        dout_ctrl    <= iy_lo_dout;
7843
        --
7844
        st_ctrl      <= idle_st;
7845
        return_state <= fetch_state;
7846
        next_state   <= pshu_iyh_state;
7847
 
7848
      when pshu_iyh_state =>
7849
        -- default registers
7850
        cc_ctrl    <= latch_cc;
7851
        acca_ctrl  <= latch_acca;
7852
        accb_ctrl  <= latch_accb;
7853
        dp_ctrl    <= latch_dp;
7854
        ix_ctrl    <= latch_ix;
7855
        iy_ctrl    <= latch_iy;
7856
        sp_ctrl    <= latch_sp;
7857
        pc_ctrl    <= latch_pc;
7858
        md_ctrl    <= latch_md;
7859
        iv_ctrl    <= latch_iv;
7860
        op_ctrl    <= latch_op;
7861
        pre_ctrl   <= latch_pre;
7862
        nmi_ctrl   <= latch_nmi;
7863
        ea_ctrl    <= latch_ea;
7864
        -- decrement sp
7865
        left_ctrl  <= up_left;
7866
        right_ctrl <= one_right;
7867
        alu_ctrl   <= alu_sub16;
7868
        if ea(4 downto 0) = "00000" then
7869
          up_ctrl <= latch_up;
7870
        else
7871
          up_ctrl <= load_up;
7872
        end if;
7873
        -- write iy hi
7874
        addr_ctrl    <= pushu_ad;
7875
        dout_ctrl    <= iy_hi_dout;
7876
        --
7877
        st_ctrl      <= idle_st;
7878
        return_state <= fetch_state;
7879
        if ea(4) = '1' then
7880
          next_state <= pshu_ixl_state;
7881
        elsif ea(3) = '1' then
7882
          next_state <= pshu_dp_state;
7883
        elsif ea(2) = '1' then
7884
          next_state <= pshu_accb_state;
7885
        elsif ea(1) = '1' then
7886
          next_state <= pshu_acca_state;
7887
        elsif ea(0) = '1' then
7888
          next_state <= pshu_cc_state;
7889
        else
7890
          next_state <= fetch_state;
7891
        end if;
7892
 
7893
      when pshu_ixl_state =>
7894
        -- default
7895
        cc_ctrl      <= latch_cc;
7896
        acca_ctrl    <= latch_acca;
7897
        accb_ctrl    <= latch_accb;
7898
        dp_ctrl      <= latch_dp;
7899
        ix_ctrl      <= latch_ix;
7900
        iy_ctrl      <= latch_iy;
7901
        sp_ctrl      <= latch_sp;
7902
        pc_ctrl      <= latch_pc;
7903
        md_ctrl      <= latch_md;
7904
        iv_ctrl      <= latch_iv;
7905
        op_ctrl      <= latch_op;
7906
        pre_ctrl     <= latch_pre;
7907
        nmi_ctrl     <= latch_nmi;
7908
        ea_ctrl      <= latch_ea;
7909
        -- decrement sp
7910
        left_ctrl    <= up_left;
7911
        right_ctrl   <= one_right;
7912
        alu_ctrl     <= alu_sub16;
7913
        up_ctrl      <= load_up;
7914
        -- write ix low
7915
        addr_ctrl    <= pushu_ad;
7916
        dout_ctrl    <= ix_lo_dout;
7917
        --
7918
        st_ctrl      <= idle_st;
7919
        return_state <= fetch_state;
7920
        next_state   <= pshu_ixh_state;
7921
 
7922
      when pshu_ixh_state =>
7923
        -- default registers
7924
        cc_ctrl    <= latch_cc;
7925
        acca_ctrl  <= latch_acca;
7926
        accb_ctrl  <= latch_accb;
7927
        dp_ctrl    <= latch_dp;
7928
        ix_ctrl    <= latch_ix;
7929
        iy_ctrl    <= latch_iy;
7930
        sp_ctrl    <= latch_sp;
7931
        pc_ctrl    <= latch_pc;
7932
        md_ctrl    <= latch_md;
7933
        iv_ctrl    <= latch_iv;
7934
        op_ctrl    <= latch_op;
7935
        pre_ctrl   <= latch_pre;
7936
        nmi_ctrl   <= latch_nmi;
7937
        ea_ctrl    <= latch_ea;
7938
        -- decrement sp
7939
        left_ctrl  <= up_left;
7940
        right_ctrl <= one_right;
7941
        alu_ctrl   <= alu_sub16;
7942
        if ea(3 downto 0) = "0000" then
7943
          up_ctrl <= latch_up;
7944
        else
7945
          up_ctrl <= load_up;
7946
        end if;
7947
        -- write ix hi
7948
        addr_ctrl    <= pushu_ad;
7949
        dout_ctrl    <= ix_hi_dout;
7950
        --
7951
        st_ctrl      <= idle_st;
7952
        return_state <= fetch_state;
7953
        if ea(3) = '1' then
7954
          next_state <= pshu_dp_state;
7955
        elsif ea(2) = '1' then
7956
          next_state <= pshu_accb_state;
7957
        elsif ea(1) = '1' then
7958
          next_state <= pshu_acca_state;
7959
        elsif ea(0) = '1' then
7960
          next_state <= pshu_cc_state;
7961
        else
7962
          next_state <= fetch_state;
7963
        end if;
7964
 
7965
      when pshu_dp_state =>
7966
        -- default registers
7967
        cc_ctrl    <= latch_cc;
7968
        acca_ctrl  <= latch_acca;
7969
        accb_ctrl  <= latch_accb;
7970
        dp_ctrl    <= latch_dp;
7971
        ix_ctrl    <= latch_ix;
7972
        iy_ctrl    <= latch_iy;
7973
        sp_ctrl    <= latch_sp;
7974
        pc_ctrl    <= latch_pc;
7975
        md_ctrl    <= latch_md;
7976
        iv_ctrl    <= latch_iv;
7977
        op_ctrl    <= latch_op;
7978
        pre_ctrl   <= latch_pre;
7979
        nmi_ctrl   <= latch_nmi;
7980
        ea_ctrl    <= latch_ea;
7981
        -- decrement sp
7982
        left_ctrl  <= up_left;
7983
        right_ctrl <= one_right;
7984
        alu_ctrl   <= alu_sub16;
7985
        if ea(2 downto 0) = "000" then
7986
          up_ctrl <= latch_up;
7987
        else
7988
          up_ctrl <= load_up;
7989
        end if;
7990
        -- write accb
7991
        addr_ctrl    <= pushu_ad;
7992
        dout_ctrl    <= dp_dout;
7993
        --
7994
        st_ctrl      <= idle_st;
7995
        return_state <= fetch_state;
7996
        if ea(2) = '1' then
7997
          next_state <= pshu_accb_state;
7998
        elsif ea(1) = '1' then
7999
          next_state <= pshu_acca_state;
8000
        elsif ea(0) = '1' then
8001
          next_state <= pshu_cc_state;
8002
        else
8003
          next_state <= fetch_state;
8004
        end if;
8005
 
8006
      when pshu_accb_state =>
8007
        -- default registers
8008
        cc_ctrl    <= latch_cc;
8009
        acca_ctrl  <= latch_acca;
8010
        accb_ctrl  <= latch_accb;
8011
        dp_ctrl    <= latch_dp;
8012
        ix_ctrl    <= latch_ix;
8013
        iy_ctrl    <= latch_iy;
8014
        sp_ctrl    <= latch_sp;
8015
        pc_ctrl    <= latch_pc;
8016
        md_ctrl    <= latch_md;
8017
        iv_ctrl    <= latch_iv;
8018
        op_ctrl    <= latch_op;
8019
        pre_ctrl   <= latch_pre;
8020
        nmi_ctrl   <= latch_nmi;
8021
        ea_ctrl    <= latch_ea;
8022
        -- decrement up
8023
        left_ctrl  <= up_left;
8024
        right_ctrl <= one_right;
8025
        alu_ctrl   <= alu_sub16;
8026
        if ea(1 downto 0) = "00" then
8027
          up_ctrl <= latch_up;
8028
        else
8029
          up_ctrl <= load_up;
8030
        end if;
8031
        -- write accb
8032
        addr_ctrl    <= pushu_ad;
8033
        dout_ctrl    <= accb_dout;
8034
        --
8035
        st_ctrl      <= idle_st;
8036
        return_state <= fetch_state;
8037
        if ea(1) = '1' then
8038
          next_state <= pshu_acca_state;
8039
        elsif ea(0) = '1' then
8040
          next_state <= pshu_cc_state;
8041
        else
8042
          next_state <= fetch_state;
8043
        end if;
8044
 
8045
      when pshu_acca_state =>
8046
        -- default registers
8047
        cc_ctrl    <= latch_cc;
8048
        acca_ctrl  <= latch_acca;
8049
        accb_ctrl  <= latch_accb;
8050
        dp_ctrl    <= latch_dp;
8051
        ix_ctrl    <= latch_ix;
8052
        iy_ctrl    <= latch_iy;
8053
        sp_ctrl    <= latch_sp;
8054
        pc_ctrl    <= latch_pc;
8055
        md_ctrl    <= latch_md;
8056
        iv_ctrl    <= latch_iv;
8057
        op_ctrl    <= latch_op;
8058
        pre_ctrl   <= latch_pre;
8059
        nmi_ctrl   <= latch_nmi;
8060
        ea_ctrl    <= latch_ea;
8061
        -- decrement sp
8062
        left_ctrl  <= up_left;
8063
        right_ctrl <= one_right;
8064
        alu_ctrl   <= alu_sub16;
8065
        if ea(0) = '0' then
8066
          up_ctrl <= latch_up;
8067
        else
8068
          up_ctrl <= load_up;
8069
        end if;
8070
        -- write acca
8071
        addr_ctrl    <= pushu_ad;
8072
        dout_ctrl    <= acca_dout;
8073
        --
8074
        st_ctrl      <= idle_st;
8075
        return_state <= fetch_state;
8076
        if ea(0) = '1' then
8077
          next_state <= pshu_cc_state;
8078
        else
8079
          next_state <= fetch_state;
8080
        end if;
8081
 
8082
      when pshu_cc_state =>
8083
        -- default registers
8084
        acca_ctrl    <= latch_acca;
8085
        accb_ctrl    <= latch_accb;
8086
        dp_ctrl      <= latch_dp;
8087
        ix_ctrl      <= latch_ix;
8088
        iy_ctrl      <= latch_iy;
8089
        sp_ctrl      <= latch_sp;
8090
        pc_ctrl      <= latch_pc;
8091
        md_ctrl      <= latch_md;
8092
        iv_ctrl      <= latch_iv;
8093
        op_ctrl      <= latch_op;
8094
        pre_ctrl     <= latch_pre;
8095
        nmi_ctrl     <= latch_nmi;
8096
        ea_ctrl      <= latch_ea;
8097
        -- idle up
8098
        left_ctrl    <= up_left;
8099
        right_ctrl   <= one_right;
8100
        cc_ctrl      <= latch_cc;
8101
        alu_ctrl     <= alu_nop;
8102
        up_ctrl      <= latch_up;
8103
        -- write cc
8104
        addr_ctrl    <= pushu_ad;
8105
        dout_ctrl    <= cc_dout;
8106
        --
8107
        st_ctrl      <= idle_st;
8108
        return_state <= fetch_state;
8109
        next_state   <= fetch_state;
8110
 
8111
        --
8112
        -- enter here on PULU
8113
        -- ea hold register mask
8114
        --
8115
      when pulu_state =>
8116
        -- default registers
8117
        cc_ctrl      <= latch_cc;
8118
        acca_ctrl    <= latch_acca;
8119
        accb_ctrl    <= latch_accb;
8120
        dp_ctrl      <= latch_dp;
8121
        ix_ctrl      <= latch_ix;
8122
        iy_ctrl      <= latch_iy;
8123
        sp_ctrl      <= latch_sp;
8124
        pc_ctrl      <= latch_pc;
8125
        md_ctrl      <= latch_md;
8126
        iv_ctrl      <= latch_iv;
8127
        op_ctrl      <= latch_op;
8128
        pre_ctrl     <= latch_pre;
8129
        nmi_ctrl     <= latch_nmi;
8130
        ea_ctrl      <= latch_ea;
8131
        -- idle UP
8132
        left_ctrl    <= up_left;
8133
        right_ctrl   <= one_right;
8134
        alu_ctrl     <= alu_add16;
8135
        up_ctrl      <= latch_up;
8136
        -- idle bus
8137
        addr_ctrl    <= idle_ad;
8138
        dout_ctrl    <= md_lo_dout;
8139
        --
8140
        st_ctrl      <= idle_st;
8141
        return_state <= fetch_state;
8142
        if ea(0) = '1' then
8143
          next_state <= pulu_cc_state;
8144
        elsif ea(1) = '1' then
8145
          next_state <= pulu_acca_state;
8146
        elsif ea(2) = '1' then
8147
          next_state <= pulu_accb_state;
8148
        elsif ea(3) = '1' then
8149
          next_state <= pulu_dp_state;
8150
        elsif ea(4) = '1' then
8151
          next_state <= pulu_ixh_state;
8152
        elsif ea(5) = '1' then
8153
          next_state <= pulu_iyh_state;
8154
        elsif ea(6) = '1' then
8155
          next_state <= pulu_sph_state;
8156
        elsif ea(7) = '1' then
8157
          next_state <= pulu_pch_state;
8158
        else
8159
          next_state <= fetch_state;
8160
        end if;
8161
 
8162
      when pulu_cc_state =>
8163
        -- default registers
8164
        acca_ctrl    <= latch_acca;
8165
        accb_ctrl    <= latch_accb;
8166
        dp_ctrl      <= latch_dp;
8167
        ix_ctrl      <= latch_ix;
8168
        iy_ctrl      <= latch_iy;
8169
        sp_ctrl      <= latch_sp;
8170
        pc_ctrl      <= latch_pc;
8171
        md_ctrl      <= latch_md;
8172
        iv_ctrl      <= latch_iv;
8173
        op_ctrl      <= latch_op;
8174
        pre_ctrl     <= latch_pre;
8175
        nmi_ctrl     <= latch_nmi;
8176
        ea_ctrl      <= latch_ea;
8177
        -- increment up
8178
        left_ctrl    <= up_left;
8179
        right_ctrl   <= one_right;
8180
        alu_ctrl     <= alu_add16;
8181
        up_ctrl      <= load_up;
8182
        -- read cc
8183
        cc_ctrl      <= pull_cc;
8184
        addr_ctrl    <= pullu_ad;
8185
        dout_ctrl    <= cc_dout;
8186
        --
8187
        st_ctrl      <= idle_st;
8188
        return_state <= fetch_state;
8189
        if ea(1) = '1' then
8190
          next_state <= pulu_acca_state;
8191
        elsif ea(2) = '1' then
8192
          next_state <= pulu_accb_state;
8193
        elsif ea(3) = '1' then
8194
          next_state <= pulu_dp_state;
8195
        elsif ea(4) = '1' then
8196
          next_state <= pulu_ixh_state;
8197
        elsif ea(5) = '1' then
8198
          next_state <= pulu_iyh_state;
8199
        elsif ea(6) = '1' then
8200
          next_state <= pulu_sph_state;
8201
        elsif ea(7) = '1' then
8202
          next_state <= pulu_pch_state;
8203
        else
8204
          next_state <= fetch_state;
8205
        end if;
8206
 
8207
      when pulu_acca_state =>
8208
        -- default registers
8209
        cc_ctrl      <= latch_cc;
8210
        accb_ctrl    <= latch_accb;
8211
        dp_ctrl      <= latch_dp;
8212
        ix_ctrl      <= latch_ix;
8213
        iy_ctrl      <= latch_iy;
8214
        sp_ctrl      <= latch_sp;
8215
        pc_ctrl      <= latch_pc;
8216
        md_ctrl      <= latch_md;
8217
        iv_ctrl      <= latch_iv;
8218
        op_ctrl      <= latch_op;
8219
        pre_ctrl     <= latch_pre;
8220
        nmi_ctrl     <= latch_nmi;
8221
        ea_ctrl      <= latch_ea;
8222
        -- increment up
8223
        left_ctrl    <= up_left;
8224
        right_ctrl   <= one_right;
8225
        alu_ctrl     <= alu_add16;
8226
        up_ctrl      <= load_up;
8227
        -- read acca
8228
        acca_ctrl    <= pull_acca;
8229
        addr_ctrl    <= pullu_ad;
8230
        dout_ctrl    <= acca_dout;
8231
        --
8232
        st_ctrl      <= idle_st;
8233
        return_state <= fetch_state;
8234
        if ea(2) = '1' then
8235
          next_state <= pulu_accb_state;
8236
        elsif ea(3) = '1' then
8237
          next_state <= pulu_dp_state;
8238
        elsif ea(4) = '1' then
8239
          next_state <= pulu_ixh_state;
8240
        elsif ea(5) = '1' then
8241
          next_state <= pulu_iyh_state;
8242
        elsif ea(6) = '1' then
8243
          next_state <= pulu_sph_state;
8244
        elsif ea(7) = '1' then
8245
          next_state <= pulu_pch_state;
8246
        else
8247
          next_state <= fetch_state;
8248
        end if;
8249
 
8250
      when pulu_accb_state =>
8251
        -- default
8252
        cc_ctrl      <= latch_cc;
8253
        acca_ctrl    <= latch_acca;
8254
        dp_ctrl      <= latch_dp;
8255
        ix_ctrl      <= latch_ix;
8256
        iy_ctrl      <= latch_iy;
8257
        sp_ctrl      <= latch_sp;
8258
        pc_ctrl      <= latch_pc;
8259
        md_ctrl      <= latch_md;
8260
        iv_ctrl      <= latch_iv;
8261
        op_ctrl      <= latch_op;
8262
        pre_ctrl     <= latch_pre;
8263
        nmi_ctrl     <= latch_nmi;
8264
        ea_ctrl      <= latch_ea;
8265
        -- increment up
8266
        left_ctrl    <= up_left;
8267
        right_ctrl   <= one_right;
8268
        alu_ctrl     <= alu_add16;
8269
        up_ctrl      <= load_up;
8270
        -- read accb
8271
        accb_ctrl    <= pull_accb;
8272
        addr_ctrl    <= pullu_ad;
8273
        dout_ctrl    <= accb_dout;
8274
        --
8275
        st_ctrl      <= idle_st;
8276
        return_state <= fetch_state;
8277
        if ea(3) = '1' then
8278
          next_state <= pulu_dp_state;
8279
        elsif ea(4) = '1' then
8280
          next_state <= pulu_ixh_state;
8281
        elsif ea(5) = '1' then
8282
          next_state <= pulu_iyh_state;
8283
        elsif ea(6) = '1' then
8284
          next_state <= pulu_sph_state;
8285
        elsif ea(7) = '1' then
8286
          next_state <= pulu_pch_state;
8287
        else
8288
          next_state <= fetch_state;
8289
        end if;
8290
 
8291
      when pulu_dp_state =>
8292
        -- default
8293
        cc_ctrl      <= latch_cc;
8294
        acca_ctrl    <= latch_acca;
8295
        accb_ctrl    <= latch_accb;
8296
        ix_ctrl      <= latch_ix;
8297
        iy_ctrl      <= latch_iy;
8298
        sp_ctrl      <= latch_sp;
8299
        pc_ctrl      <= latch_pc;
8300
        md_ctrl      <= latch_md;
8301
        iv_ctrl      <= latch_iv;
8302
        op_ctrl      <= latch_op;
8303
        pre_ctrl     <= latch_pre;
8304
        nmi_ctrl     <= latch_nmi;
8305
        ea_ctrl      <= latch_ea;
8306
        -- increment up
8307
        left_ctrl    <= up_left;
8308
        right_ctrl   <= one_right;
8309
        alu_ctrl     <= alu_add16;
8310
        up_ctrl      <= load_up;
8311
        -- read dp
8312
        dp_ctrl      <= pull_dp;
8313
        addr_ctrl    <= pullu_ad;
8314
        dout_ctrl    <= dp_dout;
8315
        --
8316
        st_ctrl      <= idle_st;
8317
        return_state <= fetch_state;
8318
        if ea(4) = '1' then
8319
          next_state <= pulu_ixh_state;
8320
        elsif ea(5) = '1' then
8321
          next_state <= pulu_iyh_state;
8322
        elsif ea(6) = '1' then
8323
          next_state <= pulu_sph_state;
8324
        elsif ea(7) = '1' then
8325
          next_state <= pulu_pch_state;
8326
        else
8327
          next_state <= fetch_state;
8328
        end if;
8329
 
8330
      when pulu_ixh_state =>
8331
        -- default
8332
        cc_ctrl      <= latch_cc;
8333
        acca_ctrl    <= latch_acca;
8334
        accb_ctrl    <= latch_accb;
8335
        dp_ctrl      <= latch_dp;
8336
        iy_ctrl      <= latch_iy;
8337
        sp_ctrl      <= latch_sp;
8338
        pc_ctrl      <= latch_pc;
8339
        md_ctrl      <= latch_md;
8340
        iv_ctrl      <= latch_iv;
8341
        op_ctrl      <= latch_op;
8342
        pre_ctrl     <= latch_pre;
8343
        nmi_ctrl     <= latch_nmi;
8344
        ea_ctrl      <= latch_ea;
8345
        -- increment up
8346
        left_ctrl    <= up_left;
8347
        right_ctrl   <= one_right;
8348
        alu_ctrl     <= alu_add16;
8349
        up_ctrl      <= load_up;
8350
        -- pull ix hi
8351
        ix_ctrl      <= pull_hi_ix;
8352
        addr_ctrl    <= pullu_ad;
8353
        dout_ctrl    <= ix_hi_dout;
8354
        --
8355
        st_ctrl      <= idle_st;
8356
        return_state <= fetch_state;
8357
        next_state   <= pulu_ixl_state;
8358
 
8359
      when pulu_ixl_state =>
8360
        -- default
8361
        cc_ctrl      <= latch_cc;
8362
        acca_ctrl    <= latch_acca;
8363
        accb_ctrl    <= latch_accb;
8364
        dp_ctrl      <= latch_dp;
8365
        iy_ctrl      <= latch_iy;
8366
        sp_ctrl      <= latch_sp;
8367
        pc_ctrl      <= latch_pc;
8368
        md_ctrl      <= latch_md;
8369
        iv_ctrl      <= latch_iv;
8370
        op_ctrl      <= latch_op;
8371
        pre_ctrl     <= latch_pre;
8372
        nmi_ctrl     <= latch_nmi;
8373
        ea_ctrl      <= latch_ea;
8374
        -- increment up
8375
        left_ctrl    <= up_left;
8376
        right_ctrl   <= one_right;
8377
        alu_ctrl     <= alu_add16;
8378
        up_ctrl      <= load_up;
8379
        -- read ix low
8380
        ix_ctrl      <= pull_lo_ix;
8381
        addr_ctrl    <= pullu_ad;
8382
        dout_ctrl    <= ix_lo_dout;
8383
        --
8384
        st_ctrl      <= idle_st;
8385
        return_state <= fetch_state;
8386
        if ea(5) = '1' then
8387
          next_state <= pulu_iyh_state;
8388
        elsif ea(6) = '1' then
8389
          next_state <= pulu_sph_state;
8390
        elsif ea(7) = '1' then
8391
          next_state <= pulu_pch_state;
8392
        else
8393
          next_state <= fetch_state;
8394
        end if;
8395
 
8396
      when pulu_iyh_state =>
8397
        -- default
8398
        cc_ctrl      <= latch_cc;
8399
        acca_ctrl    <= latch_acca;
8400
        accb_ctrl    <= latch_accb;
8401
        dp_ctrl      <= latch_dp;
8402
        ix_ctrl      <= latch_ix;
8403
        sp_ctrl      <= latch_sp;
8404
        pc_ctrl      <= latch_pc;
8405
        md_ctrl      <= latch_md;
8406
        iv_ctrl      <= latch_iv;
8407
        op_ctrl      <= latch_op;
8408
        pre_ctrl     <= latch_pre;
8409
        nmi_ctrl     <= latch_nmi;
8410
        ea_ctrl      <= latch_ea;
8411
        -- increment up
8412
        left_ctrl    <= up_left;
8413
        right_ctrl   <= one_right;
8414
        alu_ctrl     <= alu_add16;
8415
        up_ctrl      <= load_up;
8416
        -- pull iy hi
8417
        iy_ctrl      <= pull_hi_iy;
8418
        addr_ctrl    <= pullu_ad;
8419
        dout_ctrl    <= iy_hi_dout;
8420
        --
8421
        st_ctrl      <= idle_st;
8422
        return_state <= fetch_state;
8423
        next_state   <= pulu_iyl_state;
8424
 
8425
      when pulu_iyl_state =>
8426
        -- default
8427
        cc_ctrl      <= latch_cc;
8428
        acca_ctrl    <= latch_acca;
8429
        accb_ctrl    <= latch_accb;
8430
        dp_ctrl      <= latch_dp;
8431
        ix_ctrl      <= latch_ix;
8432
        sp_ctrl      <= latch_sp;
8433
        pc_ctrl      <= latch_pc;
8434
        md_ctrl      <= latch_md;
8435
        iv_ctrl      <= latch_iv;
8436
        op_ctrl      <= latch_op;
8437
        pre_ctrl     <= latch_pre;
8438
        nmi_ctrl     <= latch_nmi;
8439
        ea_ctrl      <= latch_ea;
8440
        -- increment up
8441
        left_ctrl    <= up_left;
8442
        right_ctrl   <= one_right;
8443
        alu_ctrl     <= alu_add16;
8444
        up_ctrl      <= load_up;
8445
        -- read iy low
8446
        iy_ctrl      <= pull_lo_iy;
8447
        addr_ctrl    <= pullu_ad;
8448
        dout_ctrl    <= iy_lo_dout;
8449
        --
8450
        st_ctrl      <= idle_st;
8451
        return_state <= fetch_state;
8452
        if ea(6) = '1' then
8453
          next_state <= pulu_sph_state;
8454
        elsif ea(7) = '1' then
8455
          next_state <= pulu_pch_state;
8456
        else
8457
          next_state <= fetch_state;
8458
        end if;
8459
 
8460
      when pulu_sph_state =>
8461
        -- default
8462
        cc_ctrl      <= latch_cc;
8463
        acca_ctrl    <= latch_acca;
8464
        accb_ctrl    <= latch_accb;
8465
        dp_ctrl      <= latch_dp;
8466
        ix_ctrl      <= latch_ix;
8467
        iy_ctrl      <= latch_iy;
8468
        pc_ctrl      <= latch_pc;
8469
        md_ctrl      <= latch_md;
8470
        iv_ctrl      <= latch_iv;
8471
        op_ctrl      <= latch_op;
8472
        pre_ctrl     <= latch_pre;
8473
        nmi_ctrl     <= latch_nmi;
8474
        ea_ctrl      <= latch_ea;
8475
        -- increment up
8476
        left_ctrl    <= up_left;
8477
        right_ctrl   <= one_right;
8478
        alu_ctrl     <= alu_add16;
8479
        up_ctrl      <= load_up;
8480
        -- pull sp hi
8481
        sp_ctrl      <= pull_hi_sp;
8482
        addr_ctrl    <= pullu_ad;
8483
        dout_ctrl    <= up_hi_dout;
8484
        --
8485
        st_ctrl      <= idle_st;
8486
        return_state <= fetch_state;
8487
        next_state   <= pulu_spl_state;
8488
 
8489
      when pulu_spl_state =>
8490
        -- default
8491
        cc_ctrl      <= latch_cc;
8492
        acca_ctrl    <= latch_acca;
8493
        accb_ctrl    <= latch_accb;
8494
        dp_ctrl      <= latch_dp;
8495
        ix_ctrl      <= latch_ix;
8496
        iy_ctrl      <= latch_iy;
8497
        pc_ctrl      <= latch_pc;
8498
        md_ctrl      <= latch_md;
8499
        iv_ctrl      <= latch_iv;
8500
        op_ctrl      <= latch_op;
8501
        pre_ctrl     <= latch_pre;
8502
        nmi_ctrl     <= latch_nmi;
8503
        ea_ctrl      <= latch_ea;
8504
        -- increment up
8505
        left_ctrl    <= up_left;
8506
        right_ctrl   <= one_right;
8507
        alu_ctrl     <= alu_add16;
8508
        up_ctrl      <= load_up;
8509
        -- read sp low
8510
        sp_ctrl      <= pull_lo_sp;
8511
        addr_ctrl    <= pullu_ad;
8512
        dout_ctrl    <= up_lo_dout;
8513
        --
8514
        st_ctrl      <= idle_st;
8515
        return_state <= fetch_state;
8516
        if ea(7) = '1' then
8517
          next_state <= pulu_pch_state;
8518
        else
8519
          next_state <= fetch_state;
8520
        end if;
8521
 
8522
      when pulu_pch_state =>
8523
        -- default
8524
        cc_ctrl      <= latch_cc;
8525
        acca_ctrl    <= latch_acca;
8526
        accb_ctrl    <= latch_accb;
8527
        dp_ctrl      <= latch_dp;
8528
        ix_ctrl      <= latch_ix;
8529
        iy_ctrl      <= latch_iy;
8530
        sp_ctrl      <= latch_sp;
8531
        md_ctrl      <= latch_md;
8532
        iv_ctrl      <= latch_iv;
8533
        op_ctrl      <= latch_op;
8534
        pre_ctrl     <= latch_pre;
8535
        nmi_ctrl     <= latch_nmi;
8536
        ea_ctrl      <= latch_ea;
8537
        -- increment up
8538
        left_ctrl    <= up_left;
8539
        right_ctrl   <= one_right;
8540
        alu_ctrl     <= alu_add16;
8541
        up_ctrl      <= load_up;
8542
        -- pull pc hi
8543
        pc_ctrl      <= pull_hi_pc;
8544
        addr_ctrl    <= pullu_ad;
8545
        dout_ctrl    <= pc_hi_dout;
8546
        --
8547
        st_ctrl      <= idle_st;
8548
        return_state <= fetch_state;
8549
        next_state   <= pulu_pcl_state;
8550
 
8551
      when pulu_pcl_state =>
8552
        -- default
8553
        cc_ctrl      <= latch_cc;
8554
        acca_ctrl    <= latch_acca;
8555
        accb_ctrl    <= latch_accb;
8556
        dp_ctrl      <= latch_dp;
8557
        ix_ctrl      <= latch_ix;
8558
        iy_ctrl      <= latch_iy;
8559
        sp_ctrl      <= latch_sp;
8560
        md_ctrl      <= latch_md;
8561
        iv_ctrl      <= latch_iv;
8562
        op_ctrl      <= latch_op;
8563
        pre_ctrl     <= latch_pre;
8564
        nmi_ctrl     <= latch_nmi;
8565
        ea_ctrl      <= latch_ea;
8566
        -- increment up
8567
        left_ctrl    <= up_left;
8568
        right_ctrl   <= one_right;
8569
        alu_ctrl     <= alu_add16;
8570
        up_ctrl      <= load_up;
8571
        -- read pc low
8572
        pc_ctrl      <= pull_lo_pc;
8573
        addr_ctrl    <= pullu_ad;
8574
        dout_ctrl    <= pc_lo_dout;
8575
        --
8576
        st_ctrl      <= idle_st;
8577
        return_state <= fetch_state;
8578
        next_state   <= fetch_state;
8579
 
8580
        --
8581
        -- pop the Condition codes
8582
        --
8583
      when rti_cc_state =>
8584
        -- default registers
8585
        acca_ctrl    <= latch_acca;
8586
        accb_ctrl    <= latch_accb;
8587
        dp_ctrl      <= latch_dp;
8588
        ix_ctrl      <= latch_ix;
8589
        iy_ctrl      <= latch_iy;
8590
        up_ctrl      <= latch_up;
8591
        pc_ctrl      <= latch_pc;
8592
        md_ctrl      <= latch_md;
8593
        iv_ctrl      <= latch_iv;
8594
        op_ctrl      <= latch_op;
8595
        pre_ctrl     <= latch_pre;
8596
        nmi_ctrl     <= latch_nmi;
8597
        ea_ctrl      <= latch_ea;
8598
        -- increment sp
8599
        left_ctrl    <= sp_left;
8600
        right_ctrl   <= one_right;
8601
        alu_ctrl     <= alu_add16;
8602
        sp_ctrl      <= load_sp;
8603
        -- read cc
8604
        cc_ctrl      <= pull_cc;
8605
        addr_ctrl    <= pulls_ad;
8606
        dout_ctrl    <= cc_dout;
8607
        --
8608
        st_ctrl      <= idle_st;
8609
        return_state <= fetch_state;
8610
        next_state   <= rti_entire_state;
8611
 
8612
        --
8613
        -- Added RTI cycle 11th July 2006 John Kent.
8614
        -- test the "Entire" Flag
8615
        -- that has just been popped off the stack
8616
        --
8617
      when rti_entire_state =>
8618
        -- default registers
8619
        acca_ctrl    <= latch_acca;
8620
        accb_ctrl    <= latch_accb;
8621
        dp_ctrl      <= latch_dp;
8622
        ix_ctrl      <= latch_ix;
8623
        iy_ctrl      <= latch_iy;
8624
        up_ctrl      <= latch_up;
8625
        pc_ctrl      <= latch_pc;
8626
        md_ctrl      <= latch_md;
8627
        iv_ctrl      <= latch_iv;
8628
        op_ctrl      <= latch_op;
8629
        pre_ctrl     <= latch_pre;
8630
        nmi_ctrl     <= latch_nmi;
8631
        ea_ctrl      <= latch_ea;
8632
        -- idle sp
8633
        left_ctrl    <= sp_left;
8634
        right_ctrl   <= one_right;
8635
        alu_ctrl     <= alu_nop;
8636
        sp_ctrl      <= latch_sp;
8637
        -- idle cc
8638
        cc_ctrl      <= latch_cc;
8639
        addr_ctrl    <= idle_ad;
8640
        dout_ctrl    <= cc_dout;
8641
        --
8642
        st_ctrl      <= idle_st;
8643
        return_state <= fetch_state;
8644
        --
8645
        -- The Entire flag must be recovered from the stack
8646
        -- before testing.
8647
        --
8648
        if cc(EBIT) = '1' then
8649
          next_state <= rti_acca_state;
8650
        else
8651
          next_state <= rti_pch_state;
8652
        end if;
8653
 
8654
      when rti_acca_state =>
8655
        -- default registers
8656
        cc_ctrl      <= latch_cc;
8657
        accb_ctrl    <= latch_accb;
8658
        dp_ctrl      <= latch_dp;
8659
        ix_ctrl      <= latch_ix;
8660
        iy_ctrl      <= latch_iy;
8661
        up_ctrl      <= latch_up;
8662
        pc_ctrl      <= latch_pc;
8663
        md_ctrl      <= latch_md;
8664
        iv_ctrl      <= latch_iv;
8665
        op_ctrl      <= latch_op;
8666
        pre_ctrl     <= latch_pre;
8667
        nmi_ctrl     <= latch_nmi;
8668
        ea_ctrl      <= latch_ea;
8669
        -- increment sp
8670
        left_ctrl    <= sp_left;
8671
        right_ctrl   <= one_right;
8672
        alu_ctrl     <= alu_add16;
8673
        sp_ctrl      <= load_sp;
8674
        -- read acca
8675
        acca_ctrl    <= pull_acca;
8676
        addr_ctrl    <= pulls_ad;
8677
        dout_ctrl    <= acca_dout;
8678
        --
8679
        st_ctrl      <= idle_st;
8680
        return_state <= fetch_state;
8681
        next_state   <= rti_accb_state;
8682
 
8683
      when rti_accb_state =>
8684
        -- default registers
8685
        cc_ctrl      <= latch_cc;
8686
        acca_ctrl    <= latch_acca;
8687
        dp_ctrl      <= latch_dp;
8688
        ix_ctrl      <= latch_ix;
8689
        iy_ctrl      <= latch_iy;
8690
        up_ctrl      <= latch_up;
8691
        pc_ctrl      <= latch_pc;
8692
        md_ctrl      <= latch_md;
8693
        iv_ctrl      <= latch_iv;
8694
        op_ctrl      <= latch_op;
8695
        pre_ctrl     <= latch_pre;
8696
        nmi_ctrl     <= latch_nmi;
8697
        ea_ctrl      <= latch_ea;
8698
        -- increment sp
8699
        left_ctrl    <= sp_left;
8700
        right_ctrl   <= one_right;
8701
        alu_ctrl     <= alu_add16;
8702
        sp_ctrl      <= load_sp;
8703
        -- read accb
8704
        accb_ctrl    <= pull_accb;
8705
        addr_ctrl    <= pulls_ad;
8706
        dout_ctrl    <= accb_dout;
8707
        --
8708
        st_ctrl      <= idle_st;
8709
        return_state <= fetch_state;
8710
        next_state   <= rti_dp_state;
8711
 
8712
      when rti_dp_state =>
8713
        -- default registers
8714
        cc_ctrl      <= latch_cc;
8715
        acca_ctrl    <= latch_acca;
8716
        accb_ctrl    <= latch_accb;
8717
        ix_ctrl      <= latch_ix;
8718
        iy_ctrl      <= latch_iy;
8719
        up_ctrl      <= latch_up;
8720
        pc_ctrl      <= latch_pc;
8721
        md_ctrl      <= latch_md;
8722
        iv_ctrl      <= latch_iv;
8723
        op_ctrl      <= latch_op;
8724
        pre_ctrl     <= latch_pre;
8725
        nmi_ctrl     <= latch_nmi;
8726
        ea_ctrl      <= latch_ea;
8727
        -- increment sp
8728
        left_ctrl    <= sp_left;
8729
        right_ctrl   <= one_right;
8730
        alu_ctrl     <= alu_add16;
8731
        sp_ctrl      <= load_sp;
8732
        -- read dp
8733
        dp_ctrl      <= pull_dp;
8734
        addr_ctrl    <= pulls_ad;
8735
        dout_ctrl    <= dp_dout;
8736
        --
8737
        st_ctrl      <= idle_st;
8738
        return_state <= fetch_state;
8739
        next_state   <= rti_ixh_state;
8740
 
8741
      when rti_ixh_state =>
8742
        -- default
8743
        cc_ctrl      <= latch_cc;
8744
        acca_ctrl    <= latch_acca;
8745
        accb_ctrl    <= latch_accb;
8746
        dp_ctrl      <= latch_dp;
8747
        iy_ctrl      <= latch_iy;
8748
        up_ctrl      <= latch_up;
8749
        pc_ctrl      <= latch_pc;
8750
        md_ctrl      <= latch_md;
8751
        iv_ctrl      <= latch_iv;
8752
        op_ctrl      <= latch_op;
8753
        pre_ctrl     <= latch_pre;
8754
        nmi_ctrl     <= latch_nmi;
8755
        ea_ctrl      <= latch_ea;
8756
        -- increment sp
8757
        left_ctrl    <= sp_left;
8758
        right_ctrl   <= one_right;
8759
        alu_ctrl     <= alu_add16;
8760
        sp_ctrl      <= load_sp;
8761
        -- read ix hi
8762
        ix_ctrl      <= pull_hi_ix;
8763
        addr_ctrl    <= pulls_ad;
8764
        dout_ctrl    <= ix_hi_dout;
8765
        --
8766
        st_ctrl      <= idle_st;
8767
        return_state <= fetch_state;
8768
        next_state   <= rti_ixl_state;
8769
 
8770
      when rti_ixl_state =>
8771
        -- default
8772
        cc_ctrl      <= latch_cc;
8773
        acca_ctrl    <= latch_acca;
8774
        accb_ctrl    <= latch_accb;
8775
        dp_ctrl      <= latch_dp;
8776
        iy_ctrl      <= latch_iy;
8777
        up_ctrl      <= latch_up;
8778
        pc_ctrl      <= latch_pc;
8779
        md_ctrl      <= latch_md;
8780
        iv_ctrl      <= latch_iv;
8781
        op_ctrl      <= latch_op;
8782
        pre_ctrl     <= latch_pre;
8783
        nmi_ctrl     <= latch_nmi;
8784
        ea_ctrl      <= latch_ea;
8785
        -- increment sp
8786
        left_ctrl    <= sp_left;
8787
        right_ctrl   <= one_right;
8788
        alu_ctrl     <= alu_add16;
8789
        sp_ctrl      <= load_sp;
8790
        -- read ix low
8791
        ix_ctrl      <= pull_lo_ix;
8792
        addr_ctrl    <= pulls_ad;
8793
        dout_ctrl    <= ix_lo_dout;
8794
        --
8795
        st_ctrl      <= idle_st;
8796
        return_state <= fetch_state;
8797
        next_state   <= rti_iyh_state;
8798
 
8799
      when rti_iyh_state =>
8800
        -- default
8801
        cc_ctrl      <= latch_cc;
8802
        acca_ctrl    <= latch_acca;
8803
        accb_ctrl    <= latch_accb;
8804
        dp_ctrl      <= latch_dp;
8805
        ix_ctrl      <= latch_ix;
8806
        up_ctrl      <= latch_up;
8807
        pc_ctrl      <= latch_pc;
8808
        md_ctrl      <= latch_md;
8809
        iv_ctrl      <= latch_iv;
8810
        op_ctrl      <= latch_op;
8811
        pre_ctrl     <= latch_pre;
8812
        nmi_ctrl     <= latch_nmi;
8813
        ea_ctrl      <= latch_ea;
8814
        -- increment sp
8815
        left_ctrl    <= sp_left;
8816
        right_ctrl   <= one_right;
8817
        alu_ctrl     <= alu_add16;
8818
        sp_ctrl      <= load_sp;
8819
        -- read iy hi
8820
        iy_ctrl      <= pull_hi_iy;
8821
        addr_ctrl    <= pulls_ad;
8822
        dout_ctrl    <= iy_hi_dout;
8823
        --
8824
        st_ctrl      <= idle_st;
8825
        return_state <= fetch_state;
8826
        next_state   <= rti_iyl_state;
8827
 
8828
      when rti_iyl_state =>
8829
        -- default
8830
        cc_ctrl      <= latch_cc;
8831
        acca_ctrl    <= latch_acca;
8832
        accb_ctrl    <= latch_accb;
8833
        dp_ctrl      <= latch_dp;
8834
        ix_ctrl      <= latch_ix;
8835
        up_ctrl      <= latch_up;
8836
        pc_ctrl      <= latch_pc;
8837
        md_ctrl      <= latch_md;
8838
        iv_ctrl      <= latch_iv;
8839
        op_ctrl      <= latch_op;
8840
        pre_ctrl     <= latch_pre;
8841
        nmi_ctrl     <= latch_nmi;
8842
        ea_ctrl      <= latch_ea;
8843
        -- increment sp
8844
        left_ctrl    <= sp_left;
8845
        right_ctrl   <= one_right;
8846
        alu_ctrl     <= alu_add16;
8847
        sp_ctrl      <= load_sp;
8848
        -- read iy low
8849
        iy_ctrl      <= pull_lo_iy;
8850
        addr_ctrl    <= pulls_ad;
8851
        dout_ctrl    <= iy_lo_dout;
8852
        --
8853
        st_ctrl      <= idle_st;
8854
        return_state <= fetch_state;
8855
        next_state   <= rti_uph_state;
8856
 
8857
 
8858
      when rti_uph_state =>
8859
        -- default
8860
        cc_ctrl      <= latch_cc;
8861
        acca_ctrl    <= latch_acca;
8862
        accb_ctrl    <= latch_accb;
8863
        dp_ctrl      <= latch_dp;
8864
        ix_ctrl      <= latch_ix;
8865
        iy_ctrl      <= latch_iy;
8866
        pc_ctrl      <= latch_pc;
8867
        md_ctrl      <= latch_md;
8868
        iv_ctrl      <= latch_iv;
8869
        op_ctrl      <= latch_op;
8870
        pre_ctrl     <= latch_pre;
8871
        nmi_ctrl     <= latch_nmi;
8872
        ea_ctrl      <= latch_ea;
8873
        -- increment sp
8874
        left_ctrl    <= sp_left;
8875
        right_ctrl   <= one_right;
8876
        alu_ctrl     <= alu_add16;
8877
        sp_ctrl      <= load_sp;
8878
        -- read up hi
8879
        up_ctrl      <= pull_hi_up;
8880
        addr_ctrl    <= pulls_ad;
8881
        dout_ctrl    <= up_hi_dout;
8882
        --
8883
        st_ctrl      <= idle_st;
8884
        return_state <= fetch_state;
8885
        next_state   <= rti_upl_state;
8886
 
8887
      when rti_upl_state =>
8888
        -- default
8889
        cc_ctrl      <= latch_cc;
8890
        acca_ctrl    <= latch_acca;
8891
        accb_ctrl    <= latch_accb;
8892
        dp_ctrl      <= latch_dp;
8893
        iy_ctrl      <= latch_iy;
8894
        ix_ctrl      <= latch_ix;
8895
        pc_ctrl      <= latch_pc;
8896
        md_ctrl      <= latch_md;
8897
        iv_ctrl      <= latch_iv;
8898
        op_ctrl      <= latch_op;
8899
        pre_ctrl     <= latch_pre;
8900
        nmi_ctrl     <= latch_nmi;
8901
        ea_ctrl      <= latch_ea;
8902
        -- increment sp
8903
        left_ctrl    <= sp_left;
8904
        right_ctrl   <= one_right;
8905
        alu_ctrl     <= alu_add16;
8906
        sp_ctrl      <= load_sp;
8907
        -- read up low
8908
        up_ctrl      <= pull_lo_up;
8909
        addr_ctrl    <= pulls_ad;
8910
        dout_ctrl    <= up_lo_dout;
8911
        --
8912
        st_ctrl      <= idle_st;
8913
        return_state <= fetch_state;
8914
        next_state   <= rti_pch_state;
8915
 
8916
      when rti_pch_state =>
8917
        -- default
8918
        cc_ctrl      <= latch_cc;
8919
        acca_ctrl    <= latch_acca;
8920
        accb_ctrl    <= latch_accb;
8921
        dp_ctrl      <= latch_dp;
8922
        ix_ctrl      <= latch_ix;
8923
        iy_ctrl      <= latch_iy;
8924
        up_ctrl      <= latch_up;
8925
        pc_ctrl      <= latch_pc;
8926
        md_ctrl      <= latch_md;
8927
        iv_ctrl      <= latch_iv;
8928
        op_ctrl      <= latch_op;
8929
        pre_ctrl     <= latch_pre;
8930
        nmi_ctrl     <= latch_nmi;
8931
        ea_ctrl      <= latch_ea;
8932
        -- increment sp
8933
        left_ctrl    <= sp_left;
8934
        right_ctrl   <= one_right;
8935
        alu_ctrl     <= alu_add16;
8936
        sp_ctrl      <= load_sp;
8937
        -- pull pc hi
8938
        pc_ctrl      <= pull_hi_pc;
8939
        addr_ctrl    <= pulls_ad;
8940
        dout_ctrl    <= pc_hi_dout;
8941
        --
8942
        st_ctrl      <= idle_st;
8943
        return_state <= fetch_state;
8944
        next_state   <= rti_pcl_state;
8945
 
8946
      when rti_pcl_state =>
8947
        -- default
8948
        cc_ctrl      <= latch_cc;
8949
        acca_ctrl    <= latch_acca;
8950
        accb_ctrl    <= latch_accb;
8951
        dp_ctrl      <= latch_dp;
8952
        ix_ctrl      <= latch_ix;
8953
        iy_ctrl      <= latch_iy;
8954
        up_ctrl      <= latch_up;
8955
        md_ctrl      <= latch_md;
8956
        iv_ctrl      <= latch_iv;
8957
        op_ctrl      <= latch_op;
8958
        pre_ctrl     <= latch_pre;
8959
        nmi_ctrl     <= latch_nmi;
8960
        ea_ctrl      <= latch_ea;
8961
        -- increment sp
8962
        left_ctrl    <= sp_left;
8963
        right_ctrl   <= one_right;
8964
        alu_ctrl     <= alu_add16;
8965
        sp_ctrl      <= load_sp;
8966
        -- pull pc low
8967
        pc_ctrl      <= pull_lo_pc;
8968
        addr_ctrl    <= pulls_ad;
8969
        dout_ctrl    <= pc_lo_dout;
8970
        --
8971
        st_ctrl      <= idle_st;
8972
        return_state <= fetch_state;
8973
        next_state   <= fetch_state;
8974
 
8975
        --
8976
        -- here on IRQ, NMI or FIRQ interrupt
8977
        -- pre decrement the sp
8978
        --
8979
      when int_decr_state =>
8980
        -- default
8981
        cc_ctrl      <= latch_cc;
8982
        acca_ctrl    <= latch_acca;
8983
        accb_ctrl    <= latch_accb;
8984
        dp_ctrl      <= latch_dp;
8985
        ix_ctrl      <= latch_ix;
8986
        iy_ctrl      <= latch_iy;
8987
        up_ctrl      <= latch_up;
8988
        pc_ctrl      <= latch_pc;
8989
        md_ctrl      <= latch_md;
8990
        iv_ctrl      <= latch_iv;
8991
        op_ctrl      <= latch_op;
8992
        pre_ctrl     <= latch_pre;
8993
        nmi_ctrl     <= latch_nmi;
8994
        ea_ctrl      <= latch_ea;
8995
        -- decrement sp
8996
        left_ctrl    <= sp_left;
8997
        right_ctrl   <= one_right;
8998
        alu_ctrl     <= alu_sub16;
8999
        sp_ctrl      <= load_sp;
9000
        -- idle bus
9001
        addr_ctrl    <= idle_ad;
9002
        dout_ctrl    <= pc_lo_dout;
9003
        --
9004
        st_ctrl      <= idle_st;
9005
        return_state <= fetch_state;
9006
        next_state   <= int_entire_state;
9007
 
9008
      --
9009
      -- set Entire Flag on SWI, SWI2, SWI3 and CWAI, IRQ and NMI
9010
      -- clear Entire Flag on FIRQ
9011
      -- before stacking all registers
9012
      --
9013
      when int_entire_state =>
9014
        -- default
9015
        acca_ctrl  <= latch_acca;
9016
        accb_ctrl  <= latch_accb;
9017
        dp_ctrl    <= latch_dp;
9018
        ix_ctrl    <= latch_ix;
9019
        iy_ctrl    <= latch_iy;
9020
        up_ctrl    <= latch_up;
9021
        sp_ctrl    <= latch_sp;
9022
        pc_ctrl    <= latch_pc;
9023
        md_ctrl    <= latch_md;
9024
        iv_ctrl    <= latch_iv;
9025
        op_ctrl    <= latch_op;
9026
        pre_ctrl   <= latch_pre;
9027
        nmi_ctrl   <= latch_nmi;
9028
        ea_ctrl    <= latch_ea;
9029
        --
9030
        left_ctrl  <= sp_left;
9031
        right_ctrl <= zero_right;
9032
        if iv = FIRQ_VEC then
9033
          -- clear entire flag
9034
          alu_ctrl <= alu_cle;
9035
        else
9036
          -- set entire flag
9037
          alu_ctrl <= alu_see;
9038
        end if;
9039
        cc_ctrl      <= load_cc;
9040
        -- idle bus
9041
        addr_ctrl    <= idle_ad;
9042
        dout_ctrl    <= pc_lo_dout;
9043
        --
9044
        st_ctrl      <= idle_st;
9045
        return_state <= fetch_state;
9046
        next_state   <= int_pcl_state;
9047
 
9048
      when int_pcl_state =>
9049
        -- default
9050
        cc_ctrl      <= latch_cc;
9051
        acca_ctrl    <= latch_acca;
9052
        accb_ctrl    <= latch_accb;
9053
        dp_ctrl      <= latch_dp;
9054
        ix_ctrl      <= latch_ix;
9055
        iy_ctrl      <= latch_iy;
9056
        up_ctrl      <= latch_up;
9057
        pc_ctrl      <= latch_pc;
9058
        md_ctrl      <= latch_md;
9059
        iv_ctrl      <= latch_iv;
9060
        op_ctrl      <= latch_op;
9061
        pre_ctrl     <= latch_pre;
9062
        nmi_ctrl     <= latch_nmi;
9063
        ea_ctrl      <= latch_ea;
9064
        -- decrement sp
9065
        left_ctrl    <= sp_left;
9066
        right_ctrl   <= one_right;
9067
        alu_ctrl     <= alu_sub16;
9068
        sp_ctrl      <= load_sp;
9069
        -- write pc low
9070
        addr_ctrl    <= pushs_ad;
9071
        dout_ctrl    <= pc_lo_dout;
9072
        --
9073
        st_ctrl      <= idle_st;
9074
        return_state <= fetch_state;
9075
        next_state   <= int_pch_state;
9076
 
9077
      when int_pch_state =>
9078
        -- default
9079
        cc_ctrl      <= latch_cc;
9080
        acca_ctrl    <= latch_acca;
9081
        accb_ctrl    <= latch_accb;
9082
        dp_ctrl      <= latch_dp;
9083
        ix_ctrl      <= latch_ix;
9084
        iy_ctrl      <= latch_iy;
9085
        up_ctrl      <= latch_up;
9086
        pc_ctrl      <= latch_pc;
9087
        md_ctrl      <= latch_md;
9088
        iv_ctrl      <= latch_iv;
9089
        op_ctrl      <= latch_op;
9090
        pre_ctrl     <= latch_pre;
9091
        nmi_ctrl     <= latch_nmi;
9092
        ea_ctrl      <= latch_ea;
9093
        -- decrement sp
9094
        left_ctrl    <= sp_left;
9095
        right_ctrl   <= one_right;
9096
        alu_ctrl     <= alu_sub16;
9097
        sp_ctrl      <= load_sp;
9098
        -- write pc hi
9099
        addr_ctrl    <= pushs_ad;
9100
        dout_ctrl    <= pc_hi_dout;
9101
        --
9102
        st_ctrl      <= idle_st;
9103
        return_state <= fetch_state;
9104
        if cc(EBIT) = '1' then
9105
          next_state <= int_upl_state;
9106
        else
9107
          next_state <= int_cc_state;
9108
        end if;
9109
 
9110
      when int_upl_state =>
9111
        -- default
9112
        cc_ctrl      <= latch_cc;
9113
        acca_ctrl    <= latch_acca;
9114
        accb_ctrl    <= latch_accb;
9115
        dp_ctrl      <= latch_dp;
9116
        ix_ctrl      <= latch_ix;
9117
        iy_ctrl      <= latch_iy;
9118
        up_ctrl      <= latch_up;
9119
        pc_ctrl      <= latch_pc;
9120
        md_ctrl      <= latch_md;
9121
        iv_ctrl      <= latch_iv;
9122
        op_ctrl      <= latch_op;
9123
        pre_ctrl     <= latch_pre;
9124
        nmi_ctrl     <= latch_nmi;
9125
        ea_ctrl      <= latch_ea;
9126
        -- decrement sp
9127
        left_ctrl    <= sp_left;
9128
        right_ctrl   <= one_right;
9129
        alu_ctrl     <= alu_sub16;
9130
        sp_ctrl      <= load_sp;
9131
        -- write up low
9132
        addr_ctrl    <= pushs_ad;
9133
        dout_ctrl    <= up_lo_dout;
9134
        --
9135
        st_ctrl      <= idle_st;
9136
        return_state <= fetch_state;
9137
        next_state   <= int_uph_state;
9138
 
9139
      when int_uph_state =>
9140
        -- default
9141
        cc_ctrl      <= latch_cc;
9142
        acca_ctrl    <= latch_acca;
9143
        accb_ctrl    <= latch_accb;
9144
        dp_ctrl      <= latch_dp;
9145
        ix_ctrl      <= latch_ix;
9146
        iy_ctrl      <= latch_iy;
9147
        up_ctrl      <= latch_up;
9148
        pc_ctrl      <= latch_pc;
9149
        md_ctrl      <= latch_md;
9150
        iv_ctrl      <= latch_iv;
9151
        op_ctrl      <= latch_op;
9152
        pre_ctrl     <= latch_pre;
9153
        nmi_ctrl     <= latch_nmi;
9154
        ea_ctrl      <= latch_ea;
9155
        -- decrement sp
9156
        left_ctrl    <= sp_left;
9157
        right_ctrl   <= one_right;
9158
        alu_ctrl     <= alu_sub16;
9159
        sp_ctrl      <= load_sp;
9160
        -- write ix hi
9161
        addr_ctrl    <= pushs_ad;
9162
        dout_ctrl    <= up_hi_dout;
9163
        --
9164
        st_ctrl      <= idle_st;
9165
        return_state <= fetch_state;
9166
        next_state   <= int_iyl_state;
9167
 
9168
      when int_iyl_state =>
9169
        -- default
9170
        cc_ctrl      <= latch_cc;
9171
        acca_ctrl    <= latch_acca;
9172
        accb_ctrl    <= latch_accb;
9173
        dp_ctrl      <= latch_dp;
9174
        ix_ctrl      <= latch_ix;
9175
        iy_ctrl      <= latch_iy;
9176
        up_ctrl      <= latch_up;
9177
        pc_ctrl      <= latch_pc;
9178
        md_ctrl      <= latch_md;
9179
        iv_ctrl      <= latch_iv;
9180
        op_ctrl      <= latch_op;
9181
        pre_ctrl     <= latch_pre;
9182
        nmi_ctrl     <= latch_nmi;
9183
        ea_ctrl      <= latch_ea;
9184
        -- decrement sp
9185
        left_ctrl    <= sp_left;
9186
        right_ctrl   <= one_right;
9187
        alu_ctrl     <= alu_sub16;
9188
        sp_ctrl      <= load_sp;
9189
        -- write ix low
9190
        addr_ctrl    <= pushs_ad;
9191
        dout_ctrl    <= iy_lo_dout;
9192
        --
9193
        st_ctrl      <= idle_st;
9194
        return_state <= fetch_state;
9195
        next_state   <= int_iyh_state;
9196
 
9197
      when int_iyh_state =>
9198
        -- default
9199
        cc_ctrl      <= latch_cc;
9200
        acca_ctrl    <= latch_acca;
9201
        accb_ctrl    <= latch_accb;
9202
        dp_ctrl      <= latch_dp;
9203
        ix_ctrl      <= latch_ix;
9204
        iy_ctrl      <= latch_iy;
9205
        up_ctrl      <= latch_up;
9206
        pc_ctrl      <= latch_pc;
9207
        md_ctrl      <= latch_md;
9208
        iv_ctrl      <= latch_iv;
9209
        op_ctrl      <= latch_op;
9210
        pre_ctrl     <= latch_pre;
9211
        nmi_ctrl     <= latch_nmi;
9212
        ea_ctrl      <= latch_ea;
9213
        -- decrement sp
9214
        left_ctrl    <= sp_left;
9215
        right_ctrl   <= one_right;
9216
        alu_ctrl     <= alu_sub16;
9217
        sp_ctrl      <= load_sp;
9218
        -- write ix hi
9219
        addr_ctrl    <= pushs_ad;
9220
        dout_ctrl    <= iy_hi_dout;
9221
        --
9222
        st_ctrl      <= idle_st;
9223
        return_state <= fetch_state;
9224
        next_state   <= int_ixl_state;
9225
 
9226
      when int_ixl_state =>
9227
        -- default
9228
        cc_ctrl      <= latch_cc;
9229
        acca_ctrl    <= latch_acca;
9230
        accb_ctrl    <= latch_accb;
9231
        dp_ctrl      <= latch_dp;
9232
        ix_ctrl      <= latch_ix;
9233
        iy_ctrl      <= latch_iy;
9234
        up_ctrl      <= latch_up;
9235
        pc_ctrl      <= latch_pc;
9236
        md_ctrl      <= latch_md;
9237
        iv_ctrl      <= latch_iv;
9238
        op_ctrl      <= latch_op;
9239
        pre_ctrl     <= latch_pre;
9240
        nmi_ctrl     <= latch_nmi;
9241
        ea_ctrl      <= latch_ea;
9242
        -- decrement sp
9243
        left_ctrl    <= sp_left;
9244
        right_ctrl   <= one_right;
9245
        alu_ctrl     <= alu_sub16;
9246
        sp_ctrl      <= load_sp;
9247
        -- write ix low
9248
        addr_ctrl    <= pushs_ad;
9249
        dout_ctrl    <= ix_lo_dout;
9250
        --
9251
        st_ctrl      <= idle_st;
9252
        return_state <= fetch_state;
9253
        next_state   <= int_ixh_state;
9254
 
9255
      when int_ixh_state =>
9256
        -- default
9257
        cc_ctrl      <= latch_cc;
9258
        acca_ctrl    <= latch_acca;
9259
        accb_ctrl    <= latch_accb;
9260
        dp_ctrl      <= latch_dp;
9261
        ix_ctrl      <= latch_ix;
9262
        iy_ctrl      <= latch_iy;
9263
        up_ctrl      <= latch_up;
9264
        pc_ctrl      <= latch_pc;
9265
        md_ctrl      <= latch_md;
9266
        iv_ctrl      <= latch_iv;
9267
        op_ctrl      <= latch_op;
9268
        pre_ctrl     <= latch_pre;
9269
        nmi_ctrl     <= latch_nmi;
9270
        ea_ctrl      <= latch_ea;
9271
        -- decrement sp
9272
        left_ctrl    <= sp_left;
9273
        right_ctrl   <= one_right;
9274
        alu_ctrl     <= alu_sub16;
9275
        sp_ctrl      <= load_sp;
9276
        -- write ix hi
9277
        addr_ctrl    <= pushs_ad;
9278
        dout_ctrl    <= ix_hi_dout;
9279
        --
9280
        st_ctrl      <= idle_st;
9281
        return_state <= fetch_state;
9282
        next_state   <= int_dp_state;
9283
 
9284
      when int_dp_state =>
9285
        -- default
9286
        cc_ctrl      <= latch_cc;
9287
        acca_ctrl    <= latch_acca;
9288
        accb_ctrl    <= latch_accb;
9289
        dp_ctrl      <= latch_dp;
9290
        ix_ctrl      <= latch_ix;
9291
        iy_ctrl      <= latch_iy;
9292
        up_ctrl      <= latch_up;
9293
        pc_ctrl      <= latch_pc;
9294
        md_ctrl      <= latch_md;
9295
        iv_ctrl      <= latch_iv;
9296
        op_ctrl      <= latch_op;
9297
        pre_ctrl     <= latch_pre;
9298
        nmi_ctrl     <= latch_nmi;
9299
        ea_ctrl      <= latch_ea;
9300
        -- decrement sp
9301
        left_ctrl    <= sp_left;
9302
        right_ctrl   <= one_right;
9303
        alu_ctrl     <= alu_sub16;
9304
        sp_ctrl      <= load_sp;
9305
        -- write accb
9306
        addr_ctrl    <= pushs_ad;
9307
        dout_ctrl    <= dp_dout;
9308
        --
9309
        st_ctrl      <= idle_st;
9310
        return_state <= fetch_state;
9311
        next_state   <= int_accb_state;
9312
 
9313
      when int_accb_state =>
9314
        -- default
9315
        cc_ctrl      <= latch_cc;
9316
        acca_ctrl    <= latch_acca;
9317
        accb_ctrl    <= latch_accb;
9318
        dp_ctrl      <= latch_dp;
9319
        ix_ctrl      <= latch_ix;
9320
        iy_ctrl      <= latch_iy;
9321
        up_ctrl      <= latch_up;
9322
        pc_ctrl      <= latch_pc;
9323
        md_ctrl      <= latch_md;
9324
        iv_ctrl      <= latch_iv;
9325
        op_ctrl      <= latch_op;
9326
        pre_ctrl     <= latch_pre;
9327
        nmi_ctrl     <= latch_nmi;
9328
        ea_ctrl      <= latch_ea;
9329
        -- decrement sp
9330
        left_ctrl    <= sp_left;
9331
        right_ctrl   <= one_right;
9332
        alu_ctrl     <= alu_sub16;
9333
        sp_ctrl      <= load_sp;
9334
        -- write accb
9335
        addr_ctrl    <= pushs_ad;
9336
        dout_ctrl    <= accb_dout;
9337
        --
9338
        st_ctrl      <= idle_st;
9339
        return_state <= fetch_state;
9340
        next_state   <= int_acca_state;
9341
 
9342
      when int_acca_state =>
9343
        -- default
9344
        cc_ctrl      <= latch_cc;
9345
        acca_ctrl    <= latch_acca;
9346
        accb_ctrl    <= latch_accb;
9347
        dp_ctrl      <= latch_dp;
9348
        ix_ctrl      <= latch_ix;
9349
        iy_ctrl      <= latch_iy;
9350
        up_ctrl      <= latch_up;
9351
        pc_ctrl      <= latch_pc;
9352
        md_ctrl      <= latch_md;
9353
        iv_ctrl      <= latch_iv;
9354
        op_ctrl      <= latch_op;
9355
        pre_ctrl     <= latch_pre;
9356
        nmi_ctrl     <= latch_nmi;
9357
        ea_ctrl      <= latch_ea;
9358
        -- decrement sp
9359
        left_ctrl    <= sp_left;
9360
        right_ctrl   <= one_right;
9361
        alu_ctrl     <= alu_sub16;
9362
        sp_ctrl      <= load_sp;
9363
        -- write acca
9364
        addr_ctrl    <= pushs_ad;
9365
        dout_ctrl    <= acca_dout;
9366
        --
9367
        st_ctrl      <= idle_st;
9368
        return_state <= fetch_state;
9369
        next_state   <= int_cc_state;
9370
 
9371
      when int_cc_state =>
9372
        -- default
9373
        cc_ctrl      <= latch_cc;
9374
        acca_ctrl    <= latch_acca;
9375
        accb_ctrl    <= latch_accb;
9376
        dp_ctrl      <= latch_dp;
9377
        ix_ctrl      <= latch_ix;
9378
        iy_ctrl      <= latch_iy;
9379
        up_ctrl      <= latch_up;
9380
        pc_ctrl      <= latch_pc;
9381
        md_ctrl      <= latch_md;
9382
        op_ctrl      <= latch_op;
9383
        pre_ctrl     <= latch_pre;
9384
        nmi_ctrl     <= latch_nmi;
9385
        iv_ctrl      <= latch_iv;
9386
        ea_ctrl      <= latch_ea;
9387
        -- idle sp
9388
        left_ctrl    <= sp_left;
9389
        right_ctrl   <= zero_right;
9390
        alu_ctrl     <= alu_nop;
9391
        sp_ctrl      <= latch_sp;
9392
        -- write cc
9393
        addr_ctrl    <= pushs_ad;
9394
        dout_ctrl    <= cc_dout;
9395
        nmi_ctrl     <= latch_nmi;
9396
        --
9397
        st_ctrl      <= idle_st;
9398
        return_state <= fetch_state;
9399
        case iv is
9400
          when NMI_VEC =>
9401
            next_state <= int_mask_state;
9402
          when SWI_VEC =>
9403
            next_state <= int_mask_state;
9404
          when IRQ_VEC =>
9405
            next_state <= int_mask_state;
9406
          when SWI2_VEC =>
9407
            next_state <= vect_hi_state;
9408
          when FIRQ_VEC =>
9409
            next_state <= int_mask_state;
9410
          when SWI3_VEC =>
9411
            next_state <= vect_hi_state;
9412
          when others =>
9413
            if op_code = "00111100" then   -- CWAI
9414
              next_state <= int_cwai_state;
9415
            else
9416
              next_state <= rti_cc_state;  -- spurious interrupt, do a RTI
9417
            end if;
9418
        end case;
9419
 
9420
        --
9421
        -- wait here for an inteerupt
9422
        --
9423
      when int_cwai_state =>
9424
        -- default
9425
        acca_ctrl    <= latch_acca;
9426
        accb_ctrl    <= latch_accb;
9427
        dp_ctrl      <= latch_dp;
9428
        ix_ctrl      <= latch_ix;
9429
        iy_ctrl      <= latch_iy;
9430
        up_ctrl      <= latch_up;
9431
        pc_ctrl      <= latch_pc;
9432
        md_ctrl      <= latch_md;
9433
        op_ctrl      <= latch_op;
9434
        pre_ctrl     <= latch_pre;
9435
        ea_ctrl      <= latch_ea;
9436
        --
9437
        left_ctrl    <= sp_left;
9438
        right_ctrl   <= one_right;
9439
        alu_ctrl     <= alu_nop;
9440
        cc_ctrl      <= latch_cc;
9441
        sp_ctrl      <= latch_sp;
9442
        -- idle bus
9443
        addr_ctrl    <= idle_ad;
9444
        dout_ctrl    <= cc_dout;
9445
        --
9446
        st_ctrl      <= idle_st;
9447
        return_state <= fetch_state;
9448
        --
9449
        if (nmi_req = '1') and (nmi_ack = '0') then
9450
          iv_ctrl    <= nmi_iv;
9451
          nmi_ctrl   <= set_nmi;
9452
          next_state <= vect_hi_state;
9453
        else
9454
          --
9455
          -- nmi request is not cleared until nmi input goes low
9456
          --
9457
          if (nmi_req = '0') and (nmi_ack = '1') then
9458
            nmi_ctrl <= reset_nmi;
9459
          else
9460
            nmi_ctrl <= latch_nmi;
9461
          end if;
9462
                                        --
9463
                                        -- IRQ is level sensitive
9464
                                        --
9465
          if (irq = '1') and (cc(IBIT) = '0') then
9466
            iv_ctrl    <= irq_iv;
9467
            next_state <= int_mask_state;
9468
          elsif (firq = '1') and (cc(FBIT) = '0') then
9469
                                        --
9470
                                        -- FIRQ is level sensitive
9471
                                        --
9472
            iv_ctrl    <= firq_iv;
9473
            next_state <= int_mask_state;
9474
          else
9475
            iv_ctrl    <= latch_iv;
9476
            next_state <= int_cwai_state;
9477
          end if;
9478
        end if;
9479
 
9480
      when int_mask_state =>
9481
        -- default
9482
        acca_ctrl  <= latch_acca;
9483
        accb_ctrl  <= latch_accb;
9484
        dp_ctrl    <= latch_dp;
9485
        ix_ctrl    <= latch_ix;
9486
        iy_ctrl    <= latch_iy;
9487
        up_ctrl    <= latch_up;
9488
        pc_ctrl    <= latch_pc;
9489
        md_ctrl    <= latch_md;
9490
        iv_ctrl    <= latch_iv;
9491
        op_ctrl    <= latch_op;
9492
        pre_ctrl   <= latch_pre;
9493
        nmi_ctrl   <= latch_nmi;
9494
        ea_ctrl    <= latch_ea;
9495
        -- Mask IRQ and FIRQ
9496
        left_ctrl  <= sp_left;
9497
        right_ctrl <= zero_right;
9498
        --
9499
        -- FIRQ can interrupt an IRQ service routine
9500
        --
9501
        if iv = IRQ_VEC then
9502
          alu_ctrl <= alu_sei;
9503
        else
9504
          alu_ctrl <= alu_seif;
9505
        end if;
9506
        cc_ctrl      <= load_cc;
9507
        sp_ctrl      <= latch_sp;
9508
        -- idle bus cycle
9509
        addr_ctrl    <= idle_ad;
9510
        dout_ctrl    <= md_lo_dout;
9511
        --
9512
        st_ctrl      <= idle_st;
9513
        return_state <= fetch_state;
9514
        next_state   <= vect_hi_state;
9515
 
9516
      --
9517
      -- According to the 6809 programming manual:
9518
      -- If an interrupt is received and is masked
9519
      -- or lasts for less than three cycles, the PC
9520
      -- will advance to the next instruction.
9521
      -- If an interrupt is unmasked and lasts
9522
      -- for more than three cycles, an interrupt
9523
      -- will be generated.
9524
      -- Note that I don't wait 3 clock cycles.
9525
      -- John Kent 11th July 2006
9526
      --
9527
      when sync_state =>
9528
        cc_ctrl      <= latch_cc;
9529
        acca_ctrl    <= latch_acca;
9530
        accb_ctrl    <= latch_accb;
9531
        dp_ctrl      <= latch_dp;
9532
        ix_ctrl      <= latch_ix;
9533
        iy_ctrl      <= latch_iy;
9534
        up_ctrl      <= latch_up;
9535
        sp_ctrl      <= latch_sp;
9536
        pc_ctrl      <= latch_pc;
9537
        md_ctrl      <= latch_md;
9538
        op_ctrl      <= latch_op;
9539
        pre_ctrl     <= latch_pre;
9540
        ea_ctrl      <= latch_ea;
9541
        --
9542
        left_ctrl    <= pc_left;
9543
        right_ctrl   <= one_right;
9544
        alu_ctrl     <= alu_nop;
9545
        -- idle bus
9546
        addr_ctrl    <= idle_ad;
9547
        dout_ctrl    <= cc_dout;
9548
        --
9549
        st_ctrl      <= idle_st;
9550
        return_state <= fetch_state;
9551
        --
9552
        if (nmi_req = '1') and (nmi_ack = '0') then
9553
          iv_ctrl    <= nmi_iv;
9554
          nmi_ctrl   <= set_nmi;
9555
          next_state <= int_decr_state;
9556
        else
9557
          --
9558
          -- nmi request is not cleared until nmi input goes low
9559
                              --
9560
          if (nmi_req = '0') and (nmi_ack = '1') then
9561
            nmi_ctrl <= reset_nmi;
9562
          else
9563
            nmi_ctrl <= latch_nmi;
9564
          end if;
9565
          --
9566
          -- IRQ is level sensitive
9567
          --
9568
          if (irq = '1') then
9569
            iv_ctrl <= irq_iv;
9570
            if (cc(IBIT) = '0') then
9571
              next_state <= int_decr_state;
9572
            else
9573
              next_state <= fetch_state;
9574
            end if;
9575
          elsif (firq = '1') then
9576
            --
9577
            -- FIRQ is level sensitive
9578
            --
9579
            iv_ctrl <= firq_iv;
9580
            if (cc(FBIT) = '0') then
9581
              next_state <= int_decr_state;
9582
            else
9583
              next_state <= fetch_state;
9584
            end if;
9585
          else
9586
            iv_ctrl    <= latch_iv;
9587
            next_state <= sync_state;
9588
          end if;
9589
        end if;
9590
 
9591
 
9592
      when halt_state =>
9593
        -- default
9594
        cc_ctrl    <= latch_cc;
9595
        acca_ctrl  <= latch_acca;
9596
        accb_ctrl  <= latch_accb;
9597
        dp_ctrl    <= latch_dp;
9598
        ix_ctrl    <= latch_ix;
9599
        iy_ctrl    <= latch_iy;
9600
        up_ctrl    <= latch_up;
9601
        pc_ctrl    <= latch_pc;
9602
        md_ctrl    <= latch_md;
9603
        iv_ctrl    <= latch_iv;
9604
        op_ctrl    <= latch_op;
9605
        pre_ctrl   <= latch_pre;
9606
        nmi_ctrl   <= latch_nmi;
9607
        ea_ctrl    <= latch_ea;
9608
        -- idle ALU
9609
        left_ctrl  <= acca_left;
9610
        right_ctrl <= zero_right;
9611
        alu_ctrl   <= alu_nop;
9612
        sp_ctrl    <= latch_sp;
9613
        -- idle bus cycle
9614
        addr_ctrl  <= idle_ad;
9615
        dout_ctrl  <= md_lo_dout;
9616
        --
9617
        if halt = '1' then   -- there was a bug there : if halt <= '1'
9618
          st_ctrl      <= idle_st;
9619
          return_state <= fetch_state;
9620
          next_state   <= halt_state;
9621
        else
9622
          st_ctrl      <= pull_st;
9623
          return_state <= fetch_state;
9624
          next_state   <= saved_state;
9625
        end if;
9626
 
9627
      when others =>                    -- halt on undefine states
9628
        -- default
9629
        cc_ctrl      <= latch_cc;
9630
        acca_ctrl    <= latch_acca;
9631
        accb_ctrl    <= latch_accb;
9632
        dp_ctrl      <= latch_dp;
9633
        ix_ctrl      <= latch_ix;
9634
        iy_ctrl      <= latch_iy;
9635
        up_ctrl      <= latch_up;
9636
        sp_ctrl      <= latch_sp;
9637
        pc_ctrl      <= latch_pc;
9638
        md_ctrl      <= latch_md;
9639
        iv_ctrl      <= latch_iv;
9640
        op_ctrl      <= latch_op;
9641
        pre_ctrl     <= latch_pre;
9642
        nmi_ctrl     <= latch_nmi;
9643
        ea_ctrl      <= latch_ea;
9644
        -- do nothing in ALU
9645
        left_ctrl    <= acca_left;
9646
        right_ctrl   <= zero_right;
9647
        alu_ctrl     <= alu_nop;
9648
        -- idle bus cycle
9649
        addr_ctrl    <= idle_ad;
9650
        dout_ctrl    <= md_lo_dout;
9651
        --
9652
        st_ctrl      <= idle_st;
9653
        return_state <= fetch_state;
9654
        next_state   <= error_state;
9655
    end case;
9656
  end process;
9657
 
9658
end CPU_ARCH;
9659
 

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