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[/] [System09/] [branches/] [mkfiles_rev1/] [rtl/] [VHDL/] [ioport.vhd] - Blame information for rev 162

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1 19 dilbert57
--===========================================================================----
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--
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--  S Y N T H E Z I A B L E    ioport - 2 x 8 bit parallel I/O port
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--
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--  www.OpenCores.Org - September 2003
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--  This core adheres to the GNU public license  
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--
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-- File name      : ioport.vhd
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--
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-- Purpose        : dual 8 bit I/O module for System09
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--
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-- Uses           : None
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--
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-- Author         : John E. Kent      
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--                  dilbert57@opencores.org      
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--
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--===========================================================================----
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--
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-- Revision History:
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--===========================================================================--
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--
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-- Version 0.1 - 11 Oct 2002
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--   Used a loop counter for data direction & read port signals
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-- Version 0.2 - 5 Sept 2003
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--   Reduced to 2 x 8 bit ports
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-- Version 1.0 - 6 Sept 2003 - John Kent
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--   Realeased to open Cores
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--   changed Clock Edge
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-- Version 1.1 - 25 Feb 2007 - John Kent
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--   modified sensitivity lists
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--
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--===========================================================================
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--
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library ieee;
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  use ieee.std_logic_1164.all;
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  use ieee.std_logic_unsigned.all;
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entity ioport is
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr      : in  std_logic_vector(1 downto 0);
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    data_in   : in  std_logic_vector(7 downto 0);
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         data_out  : out std_logic_vector(7 downto 0);
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         porta_io  : inout std_logic_vector(7 downto 0);
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         portb_io  : inout std_logic_vector(7 downto 0)
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         );
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end;
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architecture rtl of ioport is
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signal porta_ddr : std_logic_vector(7 downto 0);
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signal portb_ddr : std_logic_vector(7 downto 0);
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signal porta_data : std_logic_vector(7 downto 0);
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signal portb_data : std_logic_vector(7 downto 0);
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begin
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--------------------------------
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--
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-- read I/O port
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--
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--------------------------------
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ioport_read : process( addr,
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                     porta_ddr, portb_ddr,
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                                                        porta_data, portb_data,
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                                                   porta_io, portb_io )
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variable count : integer;
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begin
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      case addr is
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             when "00" =>
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                    for count in 0 to 7 loop
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            if porta_ddr(count) = '1' then
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              data_out(count) <= porta_data(count);
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            else
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              data_out(count) <= porta_io(count);
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            end if;
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                         end loop;
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                  when "01" =>
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                    for count in 0 to 7 loop
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            if portb_ddr(count) = '1' then
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              data_out(count) <= portb_data(count);
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            else
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              data_out(count) <= portb_io(count);
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            end if;
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                         end loop;
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             when "10" =>
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                    data_out <= porta_ddr;
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                  when "11" =>
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                    data_out <= portb_ddr;
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                  when others =>
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                    null;
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                end case;
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end process;
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---------------------------------
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--
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-- Write I/O ports
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--
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---------------------------------
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ioport_write : process( clk, rst, addr, cs, rw, data_in,
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                        porta_data, portb_data,
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                                                                porta_ddr, portb_ddr )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      porta_data <= "00000000";
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      portb_data <= "00000000";
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      porta_ddr <= "00000000";
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      portb_ddr <= "00000000";
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    elsif cs = '1' and rw = '0' then
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      case addr is
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             when "00" =>
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                    porta_data <= data_in;
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                    portb_data <= portb_data;
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                    porta_ddr  <= porta_ddr;
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                    portb_ddr  <= portb_ddr;
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                  when "01" =>
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                    porta_data <= porta_data;
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                    portb_data <= data_in;
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                    porta_ddr  <= porta_ddr;
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                    portb_ddr  <= portb_ddr;
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                  when "10" =>
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                    porta_data <= porta_data;
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                    portb_data <= portb_data;
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                    porta_ddr  <= data_in;
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                    portb_ddr  <= portb_ddr;
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                  when "11" =>
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                    porta_data <= porta_data;
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                    portb_data <= portb_data;
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                    porta_ddr  <= porta_ddr;
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                    portb_ddr  <= data_in;
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                  when others =>
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                    null;
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                end case;
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         else
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                    porta_data <= porta_data;
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                    portb_data <= portb_data;
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                    porta_ddr  <= porta_ddr;
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                    portb_ddr  <= portb_ddr;
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         end if;
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  end if;
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end process;
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---------------------------------
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--
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-- direction control port a
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--
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---------------------------------
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porta_direction : process ( porta_data, porta_ddr )
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variable count : integer;
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begin
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  for count in 0 to 7 loop
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    if porta_ddr(count) = '1' then
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      porta_io(count) <= porta_data(count);
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    else
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      porta_io(count) <= 'Z';
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    end if;
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  end loop;
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end process;
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---------------------------------
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--
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-- direction control port b
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--
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---------------------------------
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portb_direction : process ( portb_data, portb_ddr )
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variable count : integer;
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begin
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  for count in 0 to 7 loop
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    if portb_ddr(count) = '1' then
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      portb_io(count) <= portb_data(count);
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    else
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      portb_io(count) <= 'Z';
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    end if;
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  end loop;
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end process;
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---------------------------------
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end rtl;
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