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--
-- Flex9 O/S Initialised 8KByte RAM
--
-- v1.0 - 22 December 2006 - John Kent
-- v1.1 -  1 February 2008 - David Burnette
--        reworked to use autogenerated block ram utility
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
        use unisim.vcomponents.all;
 
entity flex_ram is
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (12 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end flex_ram;
 
architecture rtl of flex_ram is
 
  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal cs2    : std_logic;
  signal cs3    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal dp2    : std_logic;
  signal dp3    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
  signal rdata2 : std_logic_vector(7 downto 0);
  signal rdata3 : std_logic_vector(7 downto 0);
 
component FLEX9_C000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_C800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
 
begin
 
   addr_c000 : FLEX9_C000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs0,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata0
    );
 
   addr_c800 : FLEX9_C800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs1,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata1
    );
   addr_d000 : FLEX9_D000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs2,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata2
    );
   addr_d800 : FLEX9_D800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs3,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata3
    );
 
my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
begin
         we    <= not rw;
         case addr(12 downto 11) is
         when "00" =>
                cs0   <= cs;
                cs1   <= '0';
                cs2   <= '0';
                cs3   <= '0';
                rdata <= rdata0;
    when "01" =>
                cs0   <= '0';
                cs1   <= cs;
                cs2   <= '0';
                cs3   <= '0';
                rdata <= rdata1;
         when "10" =>
                cs0   <= '0';
                cs1   <= '0';
                cs2   <= cs;
                cs3   <= '0';
                rdata <= rdata2;
    when "11" =>
                cs0   <= '0';
                cs1   <= '0';
                cs2   <= '0';
                cs3   <= cs;
                rdata <= rdata3;
    when others =>
                null;
    end case;
 
end process;
 
end architecture rtl;
 

Line No.	Rev	Author	Line
1	28	davidgb	`--`
2			`-- Flex9 O/S Initialised 8KByte RAM`
3			`--`
4			`-- v1.0 - 22 December 2006 - John Kent`
5			`-- v1.1 - 1 February 2008 - David Burnette`
6			`-- reworked to use autogenerated block ram utility`
7
8			`library IEEE;`
9			`use IEEE.STD_LOGIC_1164.ALL;`
10			`use IEEE.STD_LOGIC_ARITH.ALL;`
11			`library unisim;`
12			`use unisim.vcomponents.all;`
13
14			`entity flex_ram is`
15			`Port (`
16			`clk : in std_logic;`
17			`rst : in std_logic;`
18			`cs : in std_logic;`
19			`rw : in std_logic;`
20			`addr : in std_logic_vector (12 downto 0);`
21			`rdata : out std_logic_vector (7 downto 0);`
22			`wdata : in std_logic_vector (7 downto 0)`
23			`);`
24			`end flex_ram;`
25
26			`architecture rtl of flex_ram is`
27
28			`signal we : std_logic;`
29			`signal cs0 : std_logic;`
30			`signal cs1 : std_logic;`
31			`signal cs2 : std_logic;`
32			`signal cs3 : std_logic;`
33			`signal dp0 : std_logic;`
34			`signal dp1 : std_logic;`
35			`signal dp2 : std_logic;`
36			`signal dp3 : std_logic;`
37			`signal rdata0 : std_logic_vector(7 downto 0);`
38			`signal rdata1 : std_logic_vector(7 downto 0);`
39			`signal rdata2 : std_logic_vector(7 downto 0);`
40			`signal rdata3 : std_logic_vector(7 downto 0);`
41
42			`component FLEX9_C000`
43			`Port (`
44			`clk : in std_logic;`
45			`rst : in std_logic;`
46			`cs : in std_logic;`
47			`rw : in std_logic;`
48			`addr : in std_logic_vector (10 downto 0);`
49			`rdata : out std_logic_vector (7 downto 0);`
50			`wdata : in std_logic_vector (7 downto 0)`
51			`);`
52			`end component;`
53			`component FLEX9_C800`
54			`Port (`
55			`clk : in std_logic;`
56			`rst : in std_logic;`
57			`cs : in std_logic;`
58			`rw : in std_logic;`
59			`addr : in std_logic_vector (10 downto 0);`
60			`rdata : out std_logic_vector (7 downto 0);`
61			`wdata : in std_logic_vector (7 downto 0)`
62			`);`
63			`end component;`
64			`component FLEX9_D000`
65			`Port (`
66			`clk : in std_logic;`
67			`rst : in std_logic;`
68			`cs : in std_logic;`
69			`rw : in std_logic;`
70			`addr : in std_logic_vector (10 downto 0);`
71			`rdata : out std_logic_vector (7 downto 0);`
72			`wdata : in std_logic_vector (7 downto 0)`
73			`);`
74			`end component;`
75			`component FLEX9_D800`
76			`Port (`
77			`clk : in std_logic;`
78			`rst : in std_logic;`
79			`cs : in std_logic;`
80			`rw : in std_logic;`
81			`addr : in std_logic_vector (10 downto 0);`
82			`rdata : out std_logic_vector (7 downto 0);`
83			`wdata : in std_logic_vector (7 downto 0)`
84			`);`
85			`end component;`
86
87			`begin`
88
89			`addr_c000 : FLEX9_C000 port map (`
90			`clk => clk,`
91			`rst => rst,`
92			`cs => cs0,`
93			`rw => rw,`
94			`addr => addr(10 downto 0),`
95			`wdata => wdata,`
96			`rdata => rdata0`
97			`);`
98
99			`addr_c800 : FLEX9_C800 port map (`
100			`clk => clk,`
101			`rst => rst,`
102			`cs => cs1,`
103			`rw => rw,`
104			`addr => addr(10 downto 0),`
105			`wdata => wdata,`
106			`rdata => rdata1`
107			`);`
108			`addr_d000 : FLEX9_D000 port map (`
109			`clk => clk,`
110			`rst => rst,`
111			`cs => cs2,`
112			`rw => rw,`
113			`addr => addr(10 downto 0),`
114			`wdata => wdata,`
115			`rdata => rdata2`
116			`);`
117			`addr_d800 : FLEX9_D800 port map (`
118			`clk => clk,`
119			`rst => rst,`
120			`cs => cs3,`
121			`rw => rw,`
122			`addr => addr(10 downto 0),`
123			`wdata => wdata,`
124			`rdata => rdata3`
125			`);`
126
127			`my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )`
128			`begin`
129			`we <= not rw;`
130			`case addr(12 downto 11) is`
131			`when "00" =>`
132			`cs0 <= cs;`
133			`cs1 <= '0';`
134			`cs2 <= '0';`
135			`cs3 <= '0';`
136			`rdata <= rdata0;`
137			`when "01" =>`
138			`cs0 <= '0';`
139			`cs1 <= cs;`
140			`cs2 <= '0';`
141			`cs3 <= '0';`
142			`rdata <= rdata1;`
143			`when "10" =>`
144			`cs0 <= '0';`
145			`cs1 <= '0';`
146			`cs2 <= cs;`
147			`cs3 <= '0';`
148			`rdata <= rdata2;`
149			`when "11" =>`
150			`cs0 <= '0';`
151			`cs1 <= '0';`
152			`cs2 <= '0';`
153			`cs3 <= cs;`
154			`rdata <= rdata3;`
155			`when others =>`
156			`null;`
157			`end case;`
158
159			`end process;`
160
161			`end architecture rtl;`
162

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[/] [System09/] [branches/] [mkfiles_rev1/] [src/] [Flex9/] [flex_ram_vhd] - Blame information for rev 117