URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [branches/] [mkfiles_rev1/] [src/] [sys09bug/] [mon_rom_vhd] - Blame information for rev 120

Go to most recent revision | Details | Compare with Previous | View Log


--
-- SYS09BUG Monitor Program
-- v1.0 - 21 November 2006 - John Knet
--
-- v1.1 - 22 december 2006 - John Kent
--        made into 4K ROM/RAM.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
        use unisim.vcomponents.all;
 
entity mon_rom is
    Port (
       clk   : in  std_logic;
                 rst   : in  std_logic;
                 cs    : in  std_logic;
                 rw    : in  std_logic;
       addr  : in  std_logic_vector (11 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end mon_rom;
 
architecture rtl of mon_rom is
 
  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
 
component SYS09BUG_F000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
 
component SYS09BUG_F800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
 
begin
 
   addr_f000 : SYS09BUG_F000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs0,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata0
    );
 
   addr_f800 : SYS09BUG_F800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs1,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata1
    );
 
my_mon : process ( rw, addr, cs, rdata0, rdata1 )
begin
         we    <= not rw;
         case addr(11) is
         when '0' =>
           cs0   <= cs;
                cs1   <= '0';
                rdata <= rdata0;
    when '1' =>
           cs0   <= '0';
                cs1   <= cs;
                rdata <= rdata1;
    when others =>
      null;
    end case;
 
end process;
 
end architecture rtl;
 

Line No.	Rev	Author	Line
1	28	davidgb	`--`
2			`-- SYS09BUG Monitor Program`
3			`-- v1.0 - 21 November 2006 - John Knet`
4			`--`
5			`-- v1.1 - 22 december 2006 - John Kent`
6			`-- made into 4K ROM/RAM.`
7			`--`
8			`library IEEE;`
9			`use IEEE.STD_LOGIC_1164.ALL;`
10			`use IEEE.STD_LOGIC_ARITH.ALL;`
11			`library unisim;`
12			`use unisim.vcomponents.all;`
13
14			`entity mon_rom is`
15			`Port (`
16			`clk : in std_logic;`
17			`rst : in std_logic;`
18			`cs : in std_logic;`
19			`rw : in std_logic;`
20			`addr : in std_logic_vector (11 downto 0);`
21			`rdata : out std_logic_vector (7 downto 0);`
22			`wdata : in std_logic_vector (7 downto 0)`
23			`);`
24			`end mon_rom;`
25
26			`architecture rtl of mon_rom is`
27
28			`signal we : std_logic;`
29			`signal cs0 : std_logic;`
30			`signal cs1 : std_logic;`
31			`signal dp0 : std_logic;`
32			`signal dp1 : std_logic;`
33			`signal rdata0 : std_logic_vector(7 downto 0);`
34			`signal rdata1 : std_logic_vector(7 downto 0);`
35
36			`component SYS09BUG_F000`
37			`Port (`
38			`clk : in std_logic;`
39			`rst : in std_logic;`
40			`cs : in std_logic;`
41			`rw : in std_logic;`
42			`addr : in std_logic_vector (10 downto 0);`
43			`rdata : out std_logic_vector (7 downto 0);`
44			`wdata : in std_logic_vector (7 downto 0)`
45			`);`
46			`end component;`
47
48			`component SYS09BUG_F800`
49			`Port (`
50			`clk : in std_logic;`
51			`rst : in std_logic;`
52			`cs : in std_logic;`
53			`rw : in std_logic;`
54			`addr : in std_logic_vector (10 downto 0);`
55			`rdata : out std_logic_vector (7 downto 0);`
56			`wdata : in std_logic_vector (7 downto 0)`
57			`);`
58			`end component;`
59
60			`begin`
61
62			`addr_f000 : SYS09BUG_F000 port map (`
63			`clk => clk,`
64			`rst => rst,`
65			`cs => cs0,`
66			`rw => rw,`
67			`addr => addr(10 downto 0),`
68			`wdata => wdata,`
69			`rdata => rdata0`
70			`);`
71
72			`addr_f800 : SYS09BUG_F800 port map (`
73			`clk => clk,`
74			`rst => rst,`
75			`cs => cs1,`
76			`rw => rw,`
77			`addr => addr(10 downto 0),`
78			`wdata => wdata,`
79			`rdata => rdata1`
80			`);`
81
82			`my_mon : process ( rw, addr, cs, rdata0, rdata1 )`
83			`begin`
84			`we <= not rw;`
85			`case addr(11) is`
86			`when '0' =>`
87			`cs0 <= cs;`
88			`cs1 <= '0';`
89			`rdata <= rdata0;`
90			`when '1' =>`
91			`cs0 <= '0';`
92			`cs1 <= cs;`
93			`rdata <= rdata1;`
94			`when others =>`
95			`null;`
96			`end case;`
97
98			`end process;`
99
100			`end architecture rtl;`
101

Browse

Tools

Subversion Repositories System09

[/] [System09/] [branches/] [mkfiles_rev1/] [src/] [sys09bug/] [mon_rom_vhd] - Blame information for rev 120