OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [rev_86/] [rtl/] [Spartan2/] [char_rom2k_b4.vhd] - Blame information for rev 123

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57 
--
2 
-- char_rom2k_b4.vhd
3 
--
4 
-- 2K Byte Character Generator ROM
5 
-- made out of 4 x 512 byte Block RAMs.
6 
-- John Kent
7 
-- 3 February 2007
8 
--
9 
library IEEE;
10 
use IEEE.STD_LOGIC_1164.ALL;
11 
use IEEE.STD_LOGIC_ARITH.ALL;
12 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
13 
library unisim;
14 
        use unisim.vcomponents.all;
15 
 
16 
entity char_rom is
17 
    Port (
18 
       clk   : in  std_logic;
19 
       rst   : in  std_logic;
20 
       cs    : in  std_logic;
21 
       rw    : in  std_logic;
22 
       addr  : in  std_logic_vector (10 downto 0);
23 
       wdata : in  std_logic_vector (7 downto 0);
24 
       rdata : out std_logic_vector (7 downto 0)
25 
    );
26 
end char_rom;
27 
 
28 
architecture rtl of char_rom is
29 
 
30 
   signal we       : std_logic;
31 
   signal reset    : std_logic;
32 
   signal rdata0   : std_logic_vector (7 downto 0);
33 
   signal rdata1   : std_logic_vector (7 downto 0);
34 
   signal rdata2   : std_logic_vector (7 downto 0);
35 
   signal rdata3   : std_logic_vector (7 downto 0);
36 
   signal ena0     : std_logic;
37 
   signal ena1     : std_logic;
38 
   signal ena2     : std_logic;
39 
   signal ena3     : std_logic;
40 
 
41 
   component RAMB4_S8
42 
    generic (
43 
      INIT_00, INIT_01, INIT_02, INIT_03,
44 
      INIT_04, INIT_05, INIT_06, INIT_07,
45 
      INIT_08, INIT_09, INIT_0A, INIT_0B,
46 
      INIT_0C, INIT_0D, INIT_0E, INIT_0F : bit_vector (255 downto 0) :=
47 
      x"0000000000000000000000000000000000000000000000000000000000000000"
48 
    );
49 
 
50 
    port (
51 
      clk, we, en, rst : in std_logic;
52 
      addr :  in std_logic_vector(8 downto 0);
53 
      di   :  in std_logic_vector(7 downto 0);
54 
      do   : out std_logic_vector(7 downto 0)
55 
    );
56 
  end component;
57 
 
58 
begin
59 
 
60 
  MY_RAM0 : RAMB4_S8
61 
    generic map (
62 
    INIT_00 => x"0000000009090F09090038043840380000000000070404040400444C54644400",
63 
    INIT_01 => x"00000000110A040A110078407040780000000000110A040A1100380438403800",
64 
    INIT_02 => x"000000000D1215110E0078407040780000000000040404041F00784070407800",
65 
    INIT_03 => x"000000000F080808080070487048700000000000090A0C0A0900487848483000",
66 
    INIT_04 => x"00000000040404041F0044447C444400000000000E010E100E00704870487000",
67 
    INIT_05 => x"00000000040404041F001028444444000000000010101E101F007C4040404000",
68 
    INIT_06 => x"0000000011111E111E003C4040403C000000000008080E080F00404070407800",
69 
    INIT_07 => x"00000000070202020700380438403800000000000E1111110E00380438403800",
70 
    INIT_08 => x"00000000070202060200704848487000000000000F080E080F00704848487000",
71 
    INIT_09 => x"000000000E0107020F00704848487000000000000F0806090700704848487000",
72 
    INIT_0a => x"00000000090A0C0A0900444C546444000000000001010F090900704848487000",
73 
    INIT_0b => x"000000000E090E090E0078407040780000000000111315191100380438403800",
74 
    INIT_0c => x"000000001111151B110078407040780000000000111315191100384040403800",
75 
    INIT_0d => x"000000000E1010100E00784070407800000000000E090E090E00380438403800",
76 
    INIT_0e => x"000000000E010E100E00384858403800000000000E010E100E00404070407800",
77 
    INIT_0f => x"000000000E010E100E00304848484800000000000E010E100E00485070487000"
78 
    )
79 
 
80 
    port map ( clk => clk,
81 
                    en  => ena0,
82 
                                   we  => we,
83 
                                   rst => reset,
84 
                                   addr(8 downto 0) => addr(8 downto 0),
85 
               di(7 downto 0)   => wdata(7 downto 0),
86 
                                   do(7 downto 0)   => rdata0(7 downto 0)
87 
        );
88 
 
89 
  MY_RAM1 : RAMB4_S8
90 
    generic map (
91 
    INIT_00 => x"0000000008080000080808080808080000000000000000000000000000000000",
92 
    INIT_01 => x"000000002424247E2424247E2424240000000000000000000000001212121200",
93 
    INIT_02 => x"0000000043434020100804020161610000000000083E4909093E4848493E0800",
94 
    INIT_03 => x"00000000000000000000002010080C00000000003D4244444438444444443800",
95 
    INIT_04 => x"0000000020100804040404040810200000000000020408101010101008040200",
96 
    INIT_05 => x"0000000000000808087F0808080000000000000000004122147F142241000000",
97 
    INIT_06 => x"0000000000000000007F00000000000000402010181800000000000000000000",
98 
    INIT_07 => x"0000000040404020100804020101010000000000181800000000000000000000",
99 
    INIT_08 => x"000000003E080808080808082818080000000000081422414141414122140800",
100 
    INIT_09 => x"000000003E410101010E010101413E00000000007F4020100804020141423C00",
101 
    INIT_0a => x"000000003E410101615E404040407F000000000002020202027F22120A060200",
102 
    INIT_0b => x"00000000404020100804020101017F00000000001E214141615E404040211E00",
103 
    INIT_0c => x"000000003C420101013D434141423C00000000003E414141413E414141413E00",
104 
    INIT_0d => x"0000402010181818000000181818000000000000001818180000001818180000",
105 
    INIT_0e => x"00000000000000007F00007F0000000000000000010204081020100804020100",
106 
    INIT_0f => x"00000000080800080808060101413E0000000000402010080402040810204000"
107 
    )
108 
 
109 
    port map ( clk => clk,
110 
                    en  => ena1,
111 
                                   we  => we,
112 
                                   rst => reset,
113 
                                   addr(8 downto 0) => addr(8 downto 0),
114 
               di(7 downto 0)   => wdata(7 downto 0),
115 
                                   do(7 downto 0)   => rdata1(7 downto 0)
116 
        );
117 
 
118 
  MY_RAM2 : RAMB4_S8
119 
    generic map (
120 
    INIT_00 => x"0000000041414141417F414122140800000000001C224140404E494541221C00",
121 
    INIT_01 => x"000000001E2141404040404041211E00000000007E212121213E212121217E00",
122 
    INIT_02 => x"000000007F404040407C404040407F00000000007C2221212121212121227C00",
123 
    INIT_03 => x"000000001E2141414147404040211E000000000040404040407C404040407F00",
124 
    INIT_04 => x"000000003E0808080808080808083E000000000041414141417F414141414100",
125 
    INIT_05 => x"00000000414244485060504844424100000000003C4202020202020202020700",
126 
    INIT_06 => x"00000000414141414141494955634100000000007F4040404040404040404000",
127 
    INIT_07 => x"000000003E4141414141414141413E0000000000414141434549495161414100",
128 
    INIT_08 => x"000000003D4245494141414141413E000000000040404040407E414141417E00",
129 
    INIT_09 => x"000000003E410101013E404040413E000000000041424448507E414141417E00",
130 
    INIT_0a => x"000000003E414141414141414141410000000000080808080808080808087F00",
131 
    INIT_0b => x"0000000022225555494941414141410000000000080814141422222241414100",
132 
    INIT_0c => x"0000000008080808080814224141410000000000414141221408142241414100",
133 
    INIT_0d => x"000000001E1010101010101010101E00000000007F4040201008040201017F00",
134 
    INIT_0e => x"000000003C0404040404040404043C0000000000010101020408102040404000",
135 
    INIT_0f => x"000000007F000000000000000000000000000000000000000000004122140800"
136 
    )
137 
 
138 
    port map ( clk => clk,
139 
                    en  => ena2,
140 
                                   we  => we,
141 
                                   rst => reset,
142 
                                   addr(8 downto 0) => addr(8 downto 0),
143 
               di(7 downto 0)   => wdata(7 downto 0),
144 
                                   do(7 downto 0)   => rdata2(7 downto 0)
145 
        );
146 
 
147 
  MY_RAM3 : RAMB4_S8
148 
    generic map (
149 
    INIT_00 => x"000000003F41413F01013E000000000000000000000000000000000204081800",
150 
    INIT_01 => x"000000001E21404040211E0000000000000000005E61616141615E4040404000",
151 
    INIT_02 => x"000000003E40407F41413E0000000000000000003D43414141433D0101010100",
152 
    INIT_03 => x"003C4202023E424242423D0100000000000000001010101010107C1010110E00",
153 
    INIT_04 => x"000000003E0808080808180000080800000000004141414141615E4040404000",
154 
    INIT_05 => x"00000000414448704844414040404000003C4202020202020202020000020200",
155 
    INIT_06 => x"00000000414141494955220000000000000000001C0808080808080808081800",
156 
    INIT_07 => x"000000003E41414141413E0000000000000000004141414141615E0000000000",
157 
    INIT_08 => x"00010101013D434343433D000000000000404040405E616161615E0000000000",
158 
    INIT_09 => x"000000003E01013E40403E0000000000000000002020202020314E0000000000",
159 
    INIT_0a => x"000000003D4242424242420000000000000000000C12101010107C1010101000",
160 
    INIT_0b => x"0000000022554949414141000000000000000000081414222241410000000000",
161 
    INIT_0c => x"003C4202023A4642424242000000000000000000412214081422410000000000",
162 
    INIT_0d => x"00000000070808081020100808080700000000007F20100804027F0000000000",
163 
    INIT_0e => x"0000000070080808040204080808700000000000080808080800080808080800",
164 
    INIT_0f => x"0000000049224922492249224922490000000000000000000000000046493100"
165 
    )
166 
 
167 
    port map ( clk => clk,
168 
                    en  => ena3,
169 
                                   we  => we,
170 
                                   rst => reset,
171 
                                   addr(8 downto 0) => addr(8 downto 0),
172 
               di(7 downto 0)   => wdata(7 downto 0),
173 
                                   do(7 downto 0)   => rdata3(7 downto 0)
174 
        );
175 
 
176 
my_char_rom2k_b4 : process ( clk, rst, cs, rw, addr, rdata0, rdata1, rdata2, rdata3 )
177 
begin
178 
         case addr(10 downto 9) is
179 
         when "00" =>
180 
      ena0 <= cs;
181 
           ena1 <= '0';
182 
      ena2 <= '0';
183 
           ena3 <= '0';
184 
                rdata <= rdata0;
185 
         when "01" =>
186 
      ena0 <= '0';
187 
           ena1 <= cs;
188 
      ena2 <= '0';
189 
           ena3 <= '0';
190 
                rdata <= rdata1;
191 
         when "10" =>
192 
      ena0 <= '0';
193 
           ena1 <= '0';
194 
      ena2 <= cs;
195 
           ena3 <= '0';
196 
                rdata <= rdata2;
197 
         when "11" =>
198 
      ena0 <= '0';
199 
           ena1 <= '0';
200 
      ena2 <= '0';
201 
           ena3 <= cs;
202 
                rdata <= rdata3;
203 
         when others =>
204 
      null;
205 
         end case;
206 
 
207 
         we <= cs and (not rw);
208 
    reset <= rst;
209 
 
210 
end process;
211 
 
212 
end;
213 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.