| 1 |
19 |
dilbert57 |
# XSA-3S1000 Board FPGA pin assignment constraints
|
| 2 |
|
|
#
|
| 3 |
|
|
# Clocks
|
| 4 |
|
|
#
|
| 5 |
|
|
#net CLKA loc=T9; # 100MHz
|
| 6 |
|
|
#net CLKB loc=P8; # 50MHz
|
| 7 |
|
|
#net CLKC loc=R9; # ??Mhz
|
| 8 |
|
|
net CLK100 loc=T9; # 100MHz Clock
|
| 9 |
|
|
#
|
| 10 |
|
|
# Push button switches
|
| 11 |
|
|
#
|
| 12 |
|
|
NET SW2_N loc=E11; # active-low pushbutton
|
| 13 |
|
|
NET SW3_N loc=A13; # active-low pushbutton
|
| 14 |
|
|
#
|
| 15 |
|
|
# PS/2 Keyboard
|
| 16 |
|
|
net PS2_CLK loc=B16;
|
| 17 |
|
|
net PS2_DAT loc=E13;
|
| 18 |
|
|
#
|
| 19 |
|
|
# Status LED
|
| 20 |
|
|
#
|
| 21 |
|
|
net STATUS_LED<0> loc=M6;
|
| 22 |
|
|
net STATUS_LED<1> loc=M11;
|
| 23 |
|
|
net STATUS_LED<2> loc=N6;
|
| 24 |
|
|
net STATUS_LED<3> loc=R7;
|
| 25 |
|
|
net STATUS_LED<4> loc=P10;
|
| 26 |
|
|
net STATUS_LED<5> loc=T7;
|
| 27 |
|
|
net STATUS_LED<6> loc=R10;
|
| 28 |
|
|
#
|
| 29 |
|
|
# VGA Outputs
|
| 30 |
|
|
#
|
| 31 |
|
|
NET VGA_BLUE<0> LOC=C9;
|
| 32 |
|
|
NET VGA_BLUE<1> LOC=E7;
|
| 33 |
|
|
NET VGA_BLUE<2> LOC=D5;
|
| 34 |
|
|
NET VGA_GREEN<0> LOC=A8;
|
| 35 |
|
|
NET VGA_GREEN<1> LOC=A5;
|
| 36 |
|
|
NET VGA_GREEN<2> LOC=C3;
|
| 37 |
|
|
NET VGA_RED<0> LOC=C8;
|
| 38 |
|
|
NET VGA_RED<1> LOC=D6;
|
| 39 |
|
|
NET VGA_RED<2> LOC=B1;
|
| 40 |
|
|
NET VGA_HSYNC_N LOC=B7;
|
| 41 |
|
|
NET VGA_VSYNC_N LOC=D8;
|
| 42 |
|
|
#
|
| 43 |
|
|
# Flash memory interface
|
| 44 |
|
|
#
|
| 45 |
|
|
#net FLASH_A<0> LOC=N5;
|
| 46 |
|
|
#net FLASH_A<1> LOC=K14;
|
| 47 |
|
|
#net FLASH_A<2> LOC=K13;
|
| 48 |
|
|
#net FLASH_A<3> LOC=K12;
|
| 49 |
|
|
#net FLASH_A<4> LOC=L14;
|
| 50 |
|
|
#net FLASH_A<5> LOC=M16;
|
| 51 |
|
|
#net FLASH_A<6> LOC=L13;
|
| 52 |
|
|
#net FLASH_A<7> LOC=N16;
|
| 53 |
|
|
#net FLASH_A<8> LOC=N14;
|
| 54 |
|
|
#net FLASH_A<9> LOC=P15;
|
| 55 |
|
|
#net FLASH_A<10> LOC=R16;
|
| 56 |
|
|
#net FLASH_A<11> LOC=P14;
|
| 57 |
|
|
#net FLASH_A<12> LOC=P13;
|
| 58 |
|
|
#net FLASH_A<13> LOC=N12;
|
| 59 |
|
|
#net FLASH_A<14> LOC=T14;
|
| 60 |
|
|
#net FLASH_A<15> LOC=R13;
|
| 61 |
|
|
#net FLASH_A<16> LOC=N10;
|
| 62 |
|
|
#net FLASH_A<17> LOC=M14;
|
| 63 |
|
|
#net FLASH_A<18> LOC=K3;
|
| 64 |
|
|
#net FLASH_A<19> LOC=K4;
|
| 65 |
|
|
#net FLASH_D<8> LOC=T4;
|
| 66 |
|
|
#net FLASH_D<9> LOC=R5;
|
| 67 |
|
|
#net FLASH_D<10> LOC=T5;
|
| 68 |
|
|
#net FLASH_D<11> LOC=P6;
|
| 69 |
|
|
#net FLASH_D<12> LOC=M7;
|
| 70 |
|
|
#net FLASH_D<13> LOC=R6;
|
| 71 |
|
|
#net FLASH_D<14> LOC=N7;
|
| 72 |
|
|
#net FLASH_D<15> LOC=P7;
|
| 73 |
|
|
#net FLASH_CE_N LOC=R4;
|
| 74 |
|
|
#net FLASH_OE_N LOC=P5;
|
| 75 |
|
|
#net FLASH_WE_N LOC=M13;
|
| 76 |
|
|
#net FLASH_BYTE_N LOC=T8;
|
| 77 |
|
|
#net FLASH_RDY LOC=L12;
|
| 78 |
|
|
#net FLASH_RST_N LOC=P16;
|
| 79 |
|
|
#
|
| 80 |
|
|
# Manually assign locations for the DCMs along the bottom of the FPGA
|
| 81 |
|
|
# because PAR sometimes places them in opposing corners and that ruins the clocks.
|
| 82 |
|
|
#INST "u2_dllint" LOC="DCM_X0Y0";
|
| 83 |
|
|
#INST "u2_dllext" LOC="DCM_X1Y0";
|
| 84 |
|
|
#
|
| 85 |
|
|
# SDRAM memory pin assignments
|
| 86 |
|
|
#
|
| 87 |
|
|
#net SDRAM_clkfb loc=N8; # feedback SDRAM clock after PCB delays
|
| 88 |
|
|
#net SDRAM_clkout loc=E10; # clock to SDRAM
|
| 89 |
|
|
#net SDRAM_CKE loc=D7; # SDRAM clock enable
|
| 90 |
|
|
#net SDRAM_CS_N loc=B8; # SDRAM chip-select
|
| 91 |
|
|
#net SDRAM_RAS_N loc=A9;
|
| 92 |
|
|
#net SDRAM_CAS_N loc=A10;
|
| 93 |
|
|
#net SDRAM_WE_N loc=B10;
|
| 94 |
|
|
#net SDRAM_DQMH loc=D9;
|
| 95 |
|
|
#net SDRAM_DQML loc=C10;
|
| 96 |
|
|
#net SDRAM_A<0> loc=B5;
|
| 97 |
|
|
#net SDRAM_A<1> loc=A4;
|
| 98 |
|
|
#net SDRAM_A<2> loc=B4;
|
| 99 |
|
|
#net SDRAM_A<3> loc=E6;
|
| 100 |
|
|
#net SDRAM_A<4> loc=E3;
|
| 101 |
|
|
#net SDRAM_A<5> loc=C1;
|
| 102 |
|
|
#net SDRAM_A<6> loc=E4;
|
| 103 |
|
|
#net SDRAM_A<7> loc=D3;
|
| 104 |
|
|
#net SDRAM_A<8> loc=C2;
|
| 105 |
|
|
#net SDRAM_A<9> loc=A3;
|
| 106 |
|
|
#net SDRAM_A<10> loc=B6;
|
| 107 |
|
|
#net SDRAM_A<11> loc=C5;
|
| 108 |
|
|
#net SDRAM_A<12> loc=C6;
|
| 109 |
|
|
#net SDRAM_D<0> loc=C15;
|
| 110 |
|
|
#net SDRAM_D<1> loc=D12;
|
| 111 |
|
|
#net SDRAM_D<2> loc=A14;
|
| 112 |
|
|
#net SDRAM_D<3> loc=B13;
|
| 113 |
|
|
#net SDRAM_D<4> loc=D11;
|
| 114 |
|
|
#net SDRAM_D<5> loc=A12;
|
| 115 |
|
|
#net SDRAM_D<6> loc=C11;
|
| 116 |
|
|
#net SDRAM_D<7> loc=D10;
|
| 117 |
|
|
#net SDRAM_D<8> loc=B11;
|
| 118 |
|
|
#net SDRAM_D<9> loc=B12;
|
| 119 |
|
|
#net SDRAM_D<10> loc=C12;
|
| 120 |
|
|
#net SDRAM_D<11> loc=B14;
|
| 121 |
|
|
#net SDRAM_D<12> loc=D14;
|
| 122 |
|
|
#net SDRAM_D<13> loc=C16;
|
| 123 |
|
|
#net SDRAM_D<14> loc=F12;
|
| 124 |
|
|
#net SDRAM_D<15> loc=F13;
|
| 125 |
|
|
#net SDRAM_BA<0> loc=A7;
|
| 126 |
|
|
#net SDRAM_BA<1> loc=C7;
|
| 127 |
|
|
#
|
| 128 |
|
|
# Parallel Port
|
| 129 |
|
|
#
|
| 130 |
|
|
#net PPORT_load loc=n14;
|
| 131 |
|
|
#net PPORT_clk loc=p15;
|
| 132 |
|
|
#net PPORT_din<0> loc=r16;
|
| 133 |
|
|
#net PPORT_din<1> loc=p14;
|
| 134 |
|
|
#net PPORT_din<2> loc=p13;
|
| 135 |
|
|
#net PPORT_din<3> loc=n12;
|
| 136 |
|
|
#net PPORT_dout<0> loc=n5;
|
| 137 |
|
|
#net PPORT_dout<1> loc=k14;
|
| 138 |
|
|
#net PPORT_dout<2> loc=k13;
|
| 139 |
|
|
#net PPORT_dout<3> loc=t10;
|
| 140 |
|
|
#
|
| 141 |
|
|
#
|
| 142 |
|
|
#net PPORT_d<0> loc=N14; # FLASH_A<8> / PPORT_LOAD
|
| 143 |
|
|
#net PPORT_d<1> loc=P15; # FLASH_A<9> / PPORT_CLK
|
| 144 |
|
|
#net PPORT_d<2> loc=R16; # FLASH_A<10> / PPORT_DIN<0>
|
| 145 |
|
|
#net PPORT_d<3> loc=P14; # FLASH_A<11> / PPORT_DIN<1>
|
| 146 |
|
|
#net PPORT_d<4> loc=P13; # FLASH_A<12> / PPORT_DIN<2>
|
| 147 |
|
|
#net PPORT_d<5> loc=N12; # FLASH_A<13> / PPORT_DIN<3>
|
| 148 |
|
|
## net PPORT_d<6> loc=T14; # FLASH_A<14>
|
| 149 |
|
|
## net PPORT_d<7> loc=R13; # FLASH_A<15>
|
| 150 |
|
|
#
|
| 151 |
|
|
#net PPORT_s<3> loc=N5; # FLASH_A<0> / PPORT_DOUT<0>
|
| 152 |
|
|
#net PPORT_s<4> loc=K14; # FLASH_A<1> / PPORT_DOUT<1>
|
| 153 |
|
|
#net PPORT_s<5> loc=K13; # FLASH_A<2> / PPORT_DOUT<2>
|
| 154 |
|
|
#net PPORT_s<6> loc=T10; # / PPORT_DOUT<3>
|
| 155 |
|
|
#
|
| 156 |
|
|
########################################################
|
| 157 |
|
|
#
|
| 158 |
|
|
# XST3.0 pins
|
| 159 |
|
|
#
|
| 160 |
|
|
########################################################
|
| 161 |
|
|
#
|
| 162 |
|
|
# BAR LED
|
| 163 |
|
|
#
|
| 164 |
|
|
#net BAR_LED<1> loc=L5; # barled 1
|
| 165 |
|
|
#net BAR_LED<2> loc=N2; # barled 2
|
| 166 |
|
|
#net BAR_LED<3> loc=M3; # barled 3
|
| 167 |
|
|
#net BAR_LED<4> loc=N1; # barled 4
|
| 168 |
|
|
#net BAR_LED<5> loc=T13; # barled 5
|
| 169 |
|
|
#net BAR_LED<6> loc=L15; # barled 6
|
| 170 |
|
|
#net BAR_LED<7> loc=J13; # barled 7
|
| 171 |
|
|
#net BAR_LED<8> loc=H15; # barled 8
|
| 172 |
|
|
#
|
| 173 |
|
|
# Push Buttons
|
| 174 |
|
|
#
|
| 175 |
|
|
#net PB1_N loc=H4; # pushbutton PB1
|
| 176 |
|
|
#
|
| 177 |
|
|
# RS232 PORT
|
| 178 |
|
|
#
|
| 179 |
|
|
net RS232_TXD loc=J2; # RS232 TD pin 3
|
| 180 |
|
|
net RS232_RXD loc=G5; # RS232 RD pin 2
|
| 181 |
|
|
net RS232_CTS loc=D1; # RS232 CTS
|
| 182 |
|
|
net RS232_RTS loc=F4; # RS232 RTS
|
| 183 |
|
|
#
|
| 184 |
|
|
# IDE Interface
|
| 185 |
|
|
#
|
| 186 |
|
|
net IDE_IOR_N loc=P2; # disk I/O read control
|
| 187 |
|
|
net IDE_IOW_N loc=R1; # disk I/O write control
|
| 188 |
|
|
net IDE_CS0_N loc=G15; # disk register-bank select
|
| 189 |
|
|
net IDE_CS1_N loc=G14; # disk register-bank select
|
| 190 |
|
|
net IDE_A<0> loc=L5; # 3-bit disk register address bus
|
| 191 |
|
|
net IDE_A<1> loc=N2;
|
| 192 |
|
|
net IDE_A<2> loc=M3;
|
| 193 |
|
|
net IDE_D<0> loc=P12; # 16-bit disk data bus
|
| 194 |
|
|
net IDE_D<1> loc=J1;
|
| 195 |
|
|
net IDE_D<2> loc=H1;
|
| 196 |
|
|
net IDE_D<3> loc=H3;
|
| 197 |
|
|
net IDE_D<4> loc=G2;
|
| 198 |
|
|
net IDE_D<5> loc=K15;
|
| 199 |
|
|
net IDE_D<6> loc=K16;
|
| 200 |
|
|
net IDE_D<7> loc=F15;
|
| 201 |
|
|
net IDE_D<8> loc=E2;
|
| 202 |
|
|
net IDE_D<9> loc=E1;
|
| 203 |
|
|
net IDE_D<10> loc=F3;
|
| 204 |
|
|
net IDE_D<11> loc=F2;
|
| 205 |
|
|
net IDE_D<12> loc=G4;
|
| 206 |
|
|
net IDE_D<13> loc=G3;
|
| 207 |
|
|
net IDE_D<14> loc=G1;
|
| 208 |
|
|
net IDE_D<15> loc=H4;
|
| 209 |
|
|
#net IDE_IRQ loc=H15; # IDE interrupt
|
| 210 |
|
|
#net IDE_DMACK_N loc=K1; # IDE DMA acknowledge
|
| 211 |
|
|
#
|
| 212 |
|
|
# Ethernet Controller
|
| 213 |
|
|
# Disable if not used
|
| 214 |
|
|
#
|
| 215 |
|
|
net ethernet_cs_n loc=G13; # Ethernet chip-enable
|
| 216 |
|
|
#
|
| 217 |
|
|
# Timing Constraints
|
| 218 |
|
|
#
|
| 219 |
|
|
NET "CLK100" TNM_NET="CLK100";
|
| 220 |
|
|
TIMESPEC "TS_clk"=PERIOD "CLK100" 10 ns HIGH 50 %;
|
