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59 |
davidgb |
#PACE: Start of Constraints generated by PACE
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2 |
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3 |
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#PACE: Start of PACE I/O Pin Assignments
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4 |
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# sys_clk = USER_CLK
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5 |
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NET sys_clk LOC="AH15"; # Bank 4, Vcco=3.3V, No DCI # sys_clk 100MHz clock
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6 |
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#
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7 |
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# PUSH BUTTONS
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8 |
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#
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9 |
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# rst_sw = FPGA_CPU_RESET_B
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10 |
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NET rst_sw LOC="E9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors # rst_sw
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11 |
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# nmi_sw = GPIO_SW_C
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12 |
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NET nmi_sw LOC="AJ6"; # Bank 18, Vcco=3.3V, No DCI # nmi_sw
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13 |
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#
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14 |
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# LEDs
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15 |
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#
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16 |
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# leds = GPIO_LED_...
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17 |
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NET leds<0> LOC="H18"; # Bank 3, Vcco=2.5V, No DCI # leds<0>
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18 |
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NET leds<1> LOC="L18"; # Bank 3, Vcco=2.5V, No DCI # leds<1>
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19 |
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NET leds<2> LOC="G15"; # Bank 3, Vcco=2.5V, No DCI # leds<2>
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20 |
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NET leds<3> LOC="AD26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<3>
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21 |
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NET leds<4> LOC="G16"; # Bank 3, Vcco=2.5V, No DCI # leds<4>
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22 |
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NET leds<5> LOC="AD25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<5>
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23 |
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NET leds<6> LOC="AD24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<6>
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24 |
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NET leds<7> LOC="AE24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # leds<7>
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25 |
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#
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26 |
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# Switches
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27 |
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#
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28 |
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# switches = GPIO_DIP_SW...
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29 |
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NET switches<0> LOC="U25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<0>
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30 |
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NET switches<1> LOC="AG27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<1>
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31 |
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NET switches<2> LOC="AF25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<2>
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32 |
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NET switches<3> LOC="AF26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<3>
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33 |
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NET switches<4> LOC="AE27"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<4>
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34 |
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NET switches<5> LOC="AE26"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<5>
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35 |
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NET switches<6> LOC="AC25"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<6>
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36 |
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NET switches<7> LOC="AC24"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors # switches<7>
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37 |
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#
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38 |
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# PS/2 KEYBOARD
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39 |
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#
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40 |
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NET ps2c LOC="T26"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors # ps2c
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41 |
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NET ps2d LOC="T25"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors # ps2d
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42 |
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#
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43 |
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# UART
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44 |
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#
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45 |
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NET rxd LOC="AG15"; # Bank 4, Vcco=3.3V, No DCI # rxd
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46 |
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NET txd LOC="AG20"; # Bank 4, Vcco=3.3V, No DCI # txd
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47 |
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#
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48 |
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# VDU
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49 |
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#
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50 |
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NET red LOC="AG23"; # Bank 2, Vcco=3.3V # red=GPIO_LED_E
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51 |
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NET green LOC="AF13"; # Bank 2, Vcco=3.3V # green=GPIO_LED_N
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NET blue LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors # blue=GPIO_LED_C
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NET hs LOC="AG12"; # Bank 2, Vcco=3.3V # hs=GPIO_LED_S
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NET vs LOC="AF23"; # Bank 2, Vcco=3.3V # vs=GPIO_LED_W
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56 |
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#
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# 7 SEGMENT DISPLAY
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#
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59 |
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#
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61 |
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# RAM Address bus
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#
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#NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V # ram_addr<0>
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#NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V # ram_addr<1>
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#NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V # ram_addr<2>
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66 |
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#NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V # ram_addr<3>
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#NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V # ram_addr<4>
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68 |
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#NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V # ram_addr<5>
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69 |
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#NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V # ram_addr<6>
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70 |
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#NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V # ram_addr<7>
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71 |
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#NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V # ram_addr<8>
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72 |
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#NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V # ram_addr<9>
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#NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V # ram_addr<10>
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#NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V # ram_addr<11>
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75 |
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#NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V # ram_addr<12>
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76 |
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#NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V # ram_addr<13>
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77 |
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#NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V # ram_addr<14>
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#NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V # ram_addr<15>
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#NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V # ram_addr<16>
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80 |
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#NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V # ram_addr<17>
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#NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V # ram_addr<18> <= GND
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82 |
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#NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V # ram_addr<19> <= GND
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83 |
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#NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V # ram_addr<20> <= GND
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84 |
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#NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V # ram_addr<21> <= GND
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85 |
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#NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V # ram_wen
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86 |
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#NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors # ram_oen
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#
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# RAM1
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#
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90 |
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91 |
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#NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V # ram1_data<0>
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92 |
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#NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V # ram1_data<1>
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93 |
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#NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V # ram1_data<2>
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94 |
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#NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V #
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95 |
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#NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V #
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96 |
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#NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V #
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97 |
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#NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V #
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98 |
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#NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V #
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99 |
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#NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI #
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100 |
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#NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI #
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101 |
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#NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI #
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102 |
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#NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI #
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103 |
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#NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI #
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104 |
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#NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI #
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105 |
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#NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI #
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106 |
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#NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI #
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107 |
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108 |
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109 |
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110 |
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#
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111 |
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# Timing Constraints
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112 |
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#
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NET "sys_clk" TNM_NET="sys_clk";
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TIMESPEC "TS_clk"=PERIOD "sys_clk" 10 ns HIGH 50 %;
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115 |
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116 |
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#NET SRAM_ADV_LD_B LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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117 |
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#NET SRAM_BW0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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118 |
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#NET SRAM_BW1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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119 |
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#NET SRAM_BW2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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120 |
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#NET SRAM_BW3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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121 |
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#NET SRAM_CLK LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI
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122 |
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#NET SRAM_CLK LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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123 |
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#NET SRAM_CS_B LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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124 |
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#NET SRAM_D16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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125 |
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#NET SRAM_D17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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126 |
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#NET SRAM_D18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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127 |
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#NET SRAM_D19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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128 |
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#NET SRAM_D20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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129 |
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#NET SRAM_D21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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130 |
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#NET SRAM_D22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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131 |
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#NET SRAM_D23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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132 |
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#NET SRAM_D24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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133 |
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#NET SRAM_D25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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134 |
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#NET SRAM_D26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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135 |
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#NET SRAM_D27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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136 |
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#NET SRAM_D28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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137 |
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#NET SRAM_D29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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138 |
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#NET SRAM_D30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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139 |
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#NET SRAM_D31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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140 |
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#NET SRAM_DQP0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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141 |
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#NET SRAM_DQP1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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142 |
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#NET SRAM_DQP2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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143 |
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#NET SRAM_DQP3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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144 |
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#NET SRAM_FLASH_A0 LOC="K12"; # Bank 1, Vcco=3.3V
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145 |
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#NET SRAM_FLASH_A1 LOC="K13"; # Bank 1, Vcco=3.3V
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146 |
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#NET SRAM_FLASH_A2 LOC="H23"; # Bank 1, Vcco=3.3V
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147 |
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#NET SRAM_FLASH_A3 LOC="G23"; # Bank 1, Vcco=3.3V
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148 |
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#NET SRAM_FLASH_A4 LOC="H12"; # Bank 1, Vcco=3.3V
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149 |
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#NET SRAM_FLASH_A5 LOC="J12"; # Bank 1, Vcco=3.3V
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150 |
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#NET SRAM_FLASH_A6 LOC="K22"; # Bank 1, Vcco=3.3V
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151 |
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#NET SRAM_FLASH_A7 LOC="K23"; # Bank 1, Vcco=3.3V
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152 |
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#NET SRAM_FLASH_A8 LOC="K14"; # Bank 1, Vcco=3.3V
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153 |
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#NET SRAM_FLASH_A9 LOC="L14"; # Bank 1, Vcco=3.3V
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154 |
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#NET SRAM_FLASH_A10 LOC="H22"; # Bank 1, Vcco=3.3V
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155 |
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#NET SRAM_FLASH_A11 LOC="G22"; # Bank 1, Vcco=3.3V
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156 |
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#NET SRAM_FLASH_A12 LOC="J15"; # Bank 1, Vcco=3.3V
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157 |
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#NET SRAM_FLASH_A13 LOC="K16"; # Bank 1, Vcco=3.3V
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158 |
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#NET SRAM_FLASH_A14 LOC="K21"; # Bank 1, Vcco=3.3V
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159 |
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#NET SRAM_FLASH_A15 LOC="J22"; # Bank 1, Vcco=3.3V
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160 |
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#NET SRAM_FLASH_A16 LOC="L16"; # Bank 1, Vcco=3.3V
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161 |
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#NET SRAM_FLASH_A17 LOC="L15"; # Bank 1, Vcco=3.3V
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162 |
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#NET SRAM_FLASH_A18 LOC="L20"; # Bank 1, Vcco=3.3V
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163 |
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#NET SRAM_FLASH_A19 LOC="L21"; # Bank 1, Vcco=3.3V
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164 |
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#NET SRAM_FLASH_A20 LOC="AE23"; # Bank 2, Vcco=3.3V
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165 |
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#NET SRAM_FLASH_A21 LOC="AE22"; # Bank 2, Vcco=3.3V
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166 |
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#NET SRAM_FLASH_D0 LOC="AD19"; # Bank 2, Vcco=3.3V
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167 |
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#NET SRAM_FLASH_D1 LOC="AE19"; # Bank 2, Vcco=3.3V
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168 |
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#NET SRAM_FLASH_D2 LOC="AE17"; # Bank 2, Vcco=3.3V
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169 |
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#NET SRAM_FLASH_D3 LOC="AF16"; # Bank 2, Vcco=3.3V
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170 |
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#NET SRAM_FLASH_D4 LOC="AD20"; # Bank 2, Vcco=3.3V
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171 |
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#NET SRAM_FLASH_D5 LOC="AE21"; # Bank 2, Vcco=3.3V
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172 |
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#NET SRAM_FLASH_D6 LOC="AE16"; # Bank 2, Vcco=3.3V
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173 |
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#NET SRAM_FLASH_D7 LOC="AF15"; # Bank 2, Vcco=3.3V
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174 |
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#NET SRAM_FLASH_D8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI
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175 |
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#NET SRAM_FLASH_D9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI
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176 |
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#NET SRAM_FLASH_D10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI
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177 |
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#NET SRAM_FLASH_D11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI
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178 |
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#NET SRAM_FLASH_D12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI
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179 |
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#NET SRAM_FLASH_D13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI
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180 |
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#NET SRAM_FLASH_D14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI
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181 |
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#NET SRAM_FLASH_D15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI
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182 |
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#NET SRAM_FLASH_WE_B LOC="AF20"; # Bank 2, Vcco=3.3V
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183 |
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#NET SRAM_MODE LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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184 |
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#NET SRAM_OE_B LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
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