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[/] [System09/] [rev_86/] [rtl/] [System09_base/] [my_system09.vhd] - Blame information for rev 189

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1 59 davidgb
--===========================================================================----
2
--
3
--  S Y N T H E Z I A B L E    System09 - SOC.
4
--
5
--  www.OpenCores.Org - February 2007
6
--  This core adheres to the GNU public license  
7
--
8
-- File name      : System09_Xess_XSA-3S1000.vhd
9
--
10
-- Purpose        : Top level file for 6809 compatible system on a chip
11
--                  Designed with Xilinx XC3S1000 Spartan 3 FPGA.
12
--                  Implemented With XESS XSA-3S1000 FPGA board.
13
--                  *** Note ***
14
--                  This configuration can run Flex9 however it only has
15
--                  32k bytes of user memory and the VDU is monochrome
16
--                  The design needs to be updated to use the SDRAM on 
17
--                  the XSA-3S1000 board.
18
--                  This configuration also lacks a DAT so cannot use
19
--                  the RAM Disk features of SYS09BUG.
20
--
21
-- Dependencies   : ieee.Std_Logic_1164
22
--                  ieee.std_logic_unsigned
23
--                  ieee.std_logic_arith
24
--                  ieee.numeric_std
25
--                  unisim.vcomponents
26
--
27
-- Uses           : mon_rom    (sys09bug_rom4k_b16.vhd) Sys09Bug Monitor ROM
28
--                  cpu09      (cpu09.vhd)          CPU core
29
--                  ACIA_6850  (ACIA_6850.vhd)      ACIA / UART
30
--                             (ACIA_RX.vhd)
31
--                             (ACIA_TX.vhd)
32
--                  ACIA_Clock (ACIA_Clock.vhd)      ACIA clock.
33
--                  keyboard   (keyboard.vhd)        PS/2 Keyboard interface
34
--                             (ps2_keyboard.vhd)
35
--                             (keymap_rom_slice.vhd) Key map table 
36
--                  vdu8_mono  (vdu8_mono.vhd)        Monochrome VDU
37
--                             (char_rom2k_b16.vhd)
38
--                             (ram2k_b16.vhd)
39
--                  timer      (timer.vhd)            Interrupt timer
40
--                  trap       (trap.vhd)             Bus condition trap logic
41
--                  flex_ram   (flex9_ram8k_b16.vhd)  Flex operating system
42
--                  ram_32K    (ram32k_b16.vhd)       32 KBytes of Block RAM
43
--                  
44
-- 
45
-- Author         : John E. Kent      
46
--                  dilbert57@opencores.org      
47
--
48
-- Memory Map     :
49
--
50
-- $0000 - User program RAM (32K Bytes)
51
-- $C000 - Flex Operating System memory (8K Bytes)
52
-- $E000 - ACIA (SWTPc)
53
-- $E010 - Reserved for FD1771 FDC (SWTPc)
54
-- $E020 - Keyboard
55
-- $E030 - VDU
56
-- $E040 - IDE / Compact Flash interface
57
-- $E050 - Timer
58
-- $E060 - Bus trap
59
-- $E070 - Reserced for Parallel I/O (B5-X300)
60
-- $E080 - Reserved for 6821 PIA (?) (SWTPc)
61
-- $E090 - Reserved for 6840 PTM (?) (SWTPc)
62
-- $F000 - Sys09Bug monitor Program (4K Bytes)
63
--
64
--===========================================================================----
65
--
66
-- Revision History:
67
--===========================================================================--
68
-- Version 0.1 - 20 March 2003
69
-- Version 0.2 - 30 March 2003
70
-- Version 0.3 - 29 April 2003
71
-- Version 0.4 - 29 June 2003
72
--
73
-- Version 0.5 - 19 July 2003
74
-- prints out "Hello World"
75
--
76
-- Version 0.6 - 5 September 2003
77
-- Runs SBUG
78
--
79
-- Version 1.0- 6 Sep 2003 - John Kent
80
-- Inverted SysClk
81
-- Initial release to Open Cores
82
--
83
-- Version 1.1 - 17 Jan 2004 - John Kent
84
-- Updated miniUart.
85
--
86
-- Version 1.2 - 25 Jan 2004 - John Kent
87
-- removed signals "test_alu" and "test_cc" 
88
-- Trap hardware re-instated.
89
--
90
-- Version 1.3 - 11 Feb 2004 - John Kent
91
-- Designed forked off to produce System09_VDU
92
-- Added VDU component
93
--      VDU runs at 25MHz and divides the clock by 2 for the CPU
94
-- UART Runs at 57.6 Kbps
95
--
96
-- Version 2.0 - 2 September 2004 - John Kent
97
-- ported to Digilent Xilinx Spartan3 starter board
98
--      removed Compact Flash and Trap Logic.
99
-- Replaced SBUG with KBug9s
100
--
101
-- Version 3.0 - 29th August 2006 - John Kent
102
-- Adapted to XSA-3S1000 board.
103
-- Removed DAT and miniUART.
104
-- Used 32KBytes of Block RAM.
105
--
106
-- Version 3.1 - 15th January 2007 - John Kent
107
-- Modified vdu8 interface
108
-- Added a clock divider
109
--
110
-- Version 3.2 - 25th February 2007 - John Kent
111
-- reinstated ACIA_6850 and ACIA_Clock
112
-- Updated VDU8 & Keyboard with generic parameters
113
-- Defined Constants for clock speed calculations
114
--
115
-- Version 3.3 - 1st July 2007 - John Kent
116
-- Made VDU mono to save on one RAMB16
117
-- Used distributed memory for Key Map ROM to save one RAMB16
118
-- Added Flex RAM at $C000 to $DFFF using 4 spare RAMB16s
119
-- Added timer and trap logic
120
-- Added IDE Interface for Compact Flash
121
-- Replaced KBug9s and stack with Sys09Bug.
122
--
123
-- Version 4.0 - 1st February 2008 - John kent
124
-- Replaced Block RAM with SDRAM Interface
125
-- Modified Hold timing for SDRAM
126
-- Added CF and Ethernet interface 
127
-- via the 16 bit peripheral bus at $E100
128
--
129
--===========================================================================--
130
library ieee;
131
   use ieee.std_logic_1164.all;
132
   use IEEE.STD_LOGIC_ARITH.ALL;
133
   use IEEE.STD_LOGIC_UNSIGNED.ALL;
134
   use ieee.numeric_std.all;
135
library work;
136
        use work.common.all;
137
        use WORK.xsasdram.all;
138
library unisim;
139
   use unisim.vcomponents.all;
140
 
141
entity my_system09 is
142
  port(
143
    CLKA       : in  Std_Logic;  -- 100MHz Clock input
144
         SW2_N        : in  Std_logic;  -- Master Reset input (active low)
145
         SW3_N        : in  Std_logic;  -- Non Maskable Interrupt input (active low)
146
 
147
         -- PS/2 Keyboard
148
         ps2_clk      : inout Std_logic;
149
         ps2_dat      : inout Std_Logic;
150
 
151
         -- CRTC output signals
152
         vga_vsync_n  : out Std_Logic;
153
    vga_hsync_n  : out Std_Logic;
154
    vga_blue     : out std_logic_vector(2 downto 0);
155
    vga_green    : out std_logic_vector(2 downto 0);
156
    vga_red      : out std_logic_vector(2 downto 0);
157
 
158
    -- RS232 Port
159
         RS232_RXD    : in  Std_Logic;
160
         RS232_TXD    : out Std_Logic;
161
    RS232_CTS    : in  Std_Logic;
162
    RS232_RTS    : out Std_Logic;
163
 
164
         -- Status 7 segment LED
165
--       S            : out std_logic_vector(7 downto 0);
166
 
167
    -- SDRAM side
168
    SDRAM_clkfb  : in  std_logic;            -- feedback SDRAM clock after PCB delays
169
    SDRAM_clkout : out std_logic;            -- clock to SDRAM
170
    SDRAM_CKE    : out std_logic;            -- clock-enable to SDRAM
171
    SDRAM_CS_N   : out std_logic;            -- chip-select to SDRAM
172
    SDRAM_RAS_N  : out std_logic;            -- SDRAM row address strobe
173
    SDRAM_CAS_N  : out std_logic;            -- SDRAM column address strobe
174
    SDRAM_WE_N   : out std_logic;            -- SDRAM write enable
175
    SDRAM_BA     : out std_logic_vector(1 downto 0);  -- SDRAM bank address
176
    SDRAM_A      : out std_logic_vector(12 downto 0);  -- SDRAM row/column address
177
    SDRAM_D      : inout  std_logic_vector(15 downto 0);  -- data from SDRAM
178
    SDRAM_DQMH   : out std_logic;            -- enable upper-byte of SDRAM databus if true
179
    SDRAM_DQML   : out std_logic;            -- enable lower-byte of SDRAM databus if true
180
 
181
         -- Peripheral I/O bus $E100 - $E1FF
182
    PB_RD_N      : out std_logic;
183
    PB_WR_N      : out std_logic;
184
    PB_A         : out std_logic_vector(4 downto 0);
185
    PB_D         : inout std_logic_vector(15 downto 0);
186
 
187
    -- IDE Compact Flash $E100 - $E13F
188
    ide_dmack_n  : out std_logic;
189
         ide_cs0_n    : out std_logic;
190
         ide_cs1_n    : out std_logic;
191
 
192
    -- Ethernet $E140 - $E17F
193
         ether_cs_n   : out std_logic;
194
    ether_aen    : out std_logic; -- Ethernet address enable not 
195
    ether_bhe_n  : out std_logic; -- Ethernet bus high enable 
196
    ether_clk    : in  std_logic; -- Ethernet clock 
197
    ether_rdy    : in  std_logic; -- Ethernet ready
198
         ether_irq    : in  std_logic; -- Ethernet irq - Shared with BAR6
199
 
200
    -- Slot 1 $E180 - $E1BF
201
         slot1_cs_n   : out std_logic;
202
--       slot1_irq    : in  std_logic;
203
 
204
    -- Slot 2 $E1C0 - $E1FF
205
         slot2_cs_n   : out std_logic;
206
--       slot2_irq    : in  std_logic;
207
 
208
         -- Disable Flash
209
         FLASH_CE_N   : out std_logic
210
         );
211
end My_System09;
212
 
213
-------------------------------------------------------------------------------
214
-- Architecture for System09
215
-------------------------------------------------------------------------------
216
architecture rtl of my_system09 is
217
 
218
  -----------------------------------------------------------------------------
219
  -- constants
220
  -----------------------------------------------------------------------------
221
  constant SYS_Clock_Frequency  : integer := 50000000;  -- FPGA System Clock
222
  constant PIX_Clock_Frequency  : integer := 25000000;  -- VGA Pixel Clock
223
  constant CPU_Clock_Frequency  : integer := 25000000;  -- CPU Clock
224
  constant BAUD_Rate            : integer := 57600;       -- Baud Rate
225
  constant ACIA_Clock_Frequency : integer := BAUD_Rate * 16;
226
 
227
  type hold_state_type is ( hold_release_state, hold_request_state );
228
 
229
  -----------------------------------------------------------------------------
230
  -- Signals
231
  -----------------------------------------------------------------------------
232
  signal rst_n          :  Std_logic;  -- Master Reset input (active low)
233
  signal nmi_n          :  Std_logic;  -- Non Maskable Interrupt input (active low)
234
 
235
  -- BOOT ROM
236
  signal rom_cs         : Std_logic;
237
  signal rom_data_out   : Std_Logic_Vector(7 downto 0);
238
 
239
  -- Flex Memory & Monitor Stack
240
  signal flex_cs        : Std_logic;
241
  signal flex_data_out  : Std_Logic_Vector(7 downto 0);
242
 
243
  -- ACIA/UART Interface signals
244
  signal acia_data_out  : Std_Logic_Vector(7 downto 0);
245
  signal acia_cs        : Std_Logic;
246
  signal acia_irq       : Std_Logic;
247
  signal acia_clk       : Std_Logic;
248
  signal rxd            : Std_Logic;
249
  signal txd            : Std_Logic;
250
  signal DCD_n          : Std_Logic;
251
  signal RTS_n          : Std_Logic;
252
  signal CTS_n          : Std_Logic;
253
 
254
  -- keyboard port
255
  signal keyboard_data_out : std_logic_vector(7 downto 0);
256
  signal keyboard_cs       : std_logic;
257
  signal keyboard_irq      : std_logic;
258
 
259
  -- RAM
260
  signal ram_cs         : std_logic; -- memory chip select
261
  signal ram_data_out   : std_logic_vector(7 downto 0);
262
  signal ram_hold       : std_logic; -- hold off slow accesses
263
 
264
  -- CPU Interface signals
265
  signal cpu_reset      : Std_Logic;
266
  signal cpu_clk        : Std_Logic;
267
  signal cpu_rw         : std_logic;
268
  signal cpu_vma        : std_logic;
269
  signal cpu_halt       : std_logic;
270
  signal cpu_hold       : std_logic;
271
  signal cpu_firq       : std_logic;
272
  signal cpu_irq        : std_logic;
273
  signal cpu_nmi        : std_logic;
274
  signal cpu_addr       : std_logic_vector(15 downto 0);
275
  signal cpu_data_in    : std_logic_vector(7 downto 0);
276
  signal cpu_data_out   : std_logic_vector(7 downto 0);
277
 
278
  -- Dynamic Address Translation
279
  signal dat_cs       : std_logic;
280
  signal dat_addr     : std_logic_vector(7 downto 0);
281
 
282
  -- Video Display Unit
283
  signal vdu_cs         : std_logic;
284
  signal vdu_data_out   : std_logic_vector(7 downto 0);
285
  signal vga_red_o      : std_logic;
286
  signal vga_green_o    : std_logic;
287
  signal vga_blue_o     : std_logic;
288
 
289
  -- timer
290
  signal timer_data_out : std_logic_vector(7 downto 0);
291
  signal timer_cs       : std_logic;
292
  signal timer_irq      : std_logic;
293
 
294
  -- trap
295
  signal trap_cs        : std_logic;
296
  signal trap_data_out  : std_logic_vector(7 downto 0);
297
  signal trap_irq       : std_logic;
298
 
299
  -- Peripheral Bus port
300
  signal pb_data_out   : std_logic_vector(7 downto 0);
301
  signal pb_cs         : std_logic;       -- peripheral bus chip select
302
  signal pb_wru        : std_logic;       -- upper byte write strobe
303
  signal pb_wrl        : std_logic;       -- lower byte write strobe
304
  signal pb_rdu        : std_logic;       -- upper byte read strobe
305
  signal pb_rdl        : std_logic;       -- lower byte read strobe
306
  signal pb_hold       : std_logic;       -- hold peripheral bus access
307
  signal pb_release    : std_logic;       -- release hold of peripheral bus
308
  signal pb_count      : std_logic_vector(3 downto 0); -- hold counter
309
  signal pb_hold_state : hold_state_type;
310
  signal pb_wreg       : std_logic_vector(7 downto 0); -- lower byte write register
311
  signal pb_rreg       : std_logic_vector(7 downto 0); -- lower byte read register
312
 
313
  -- Peripheral chip selects on Peripheral Bus
314
  signal ide_cs        : std_logic; -- IDE CF interface
315
  signal ether_cs      : std_logic;     -- Ethernet interface
316
  signal slot1_cs      : std_logic;     -- Expansion slot 1
317
  signal slot2_cs      : std_logic;     -- Expansion slot 2
318
 
319
 
320
-- SDRAM
321
 
322
  constant  FREQ                 :     natural := 100_000; -- operating frequency in KHz
323
  constant  CLK_DIV              :     real    := 2.0;    -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
324
  constant  PIPE_EN              :     boolean := false;  -- if true, enable pipelined read operations
325
  constant  MAX_NOP              :     natural := 10000;  -- number of NOPs before entering self-refresh
326
  constant  MULTIPLE_ACTIVE_ROWS :     boolean := false;  -- if true, allow an active row in each bank
327
  constant  DATA_WIDTH           :     natural := 16;     -- host & SDRAM data width
328
  constant  NROWS                :     natural := 8192;   -- number of rows in SDRAM array
329
  constant  NCOLS                :     natural := 512;    -- number of columns in SDRAM array
330
  constant  HADDR_WIDTH          :     natural := 24;     -- host-side address width
331
  constant  SADDR_WIDTH          :     natural := 13;     -- SDRAM-side address width
332
 
333
  signal   rst_i        : std_logic;     -- internal reset signal
334
  signal   clk_i        : std_logic;     -- internal master clock signal
335
  signal   lock         : std_logic;     -- SDRAM clock DLL lock indicator
336
 
337
  -- signals that go through the SDRAM host-side interface
338
  signal opBegun        : std_logic;        -- SDRAM operation started indicator
339
  signal earlyBegun     : std_logic;        -- SDRAM operation started indicator
340
  signal ramDone        : std_logic;        -- SDRAM operation complete indicator
341
  signal rdDone         : std_logic;        -- SDRAM read operation complete indicator
342
  signal wrDone         : std_logic;        -- SDRAM write operation complete indicator
343
  signal hAddr          : std_logic_vector(HADDR_WIDTH-1 downto 0);  -- host address bus
344
  signal hDIn           : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data to SDRAM
345
  signal hDOut          : std_logic_vector(DATA_WIDTH-1 downto 0);  -- host-side data from SDRAM
346
  signal hRd            : std_logic;        -- host-side read control signal
347
  signal hWr            : std_logic;        -- host-side write control signal
348
  signal rdPending      : std_logic;        -- read operation pending in SDRAM pipeline
349
  type ram_rd_type is (rd_state0, rd_state1, rd_state2, rd_state3);
350
  type ram_wr_type is (wr_state0, wr_state1, wr_state2, wr_state3, wr_state4);
351
  signal ram_rd_state   : ram_rd_type;
352
  signal ram_wr_state   : ram_wr_type;
353
 
354
--  signal BaudCount    : std_logic_vector(5 downto 0);
355
  signal CountL         : std_logic_vector(23 downto 0);
356
  signal clk_count      : std_logic_vector(0 downto 0);
357
  signal Clk25          : std_logic;
358
  signal pix_clk        : std_logic;
359
 
360
-----------------------------------------------------------------
361
--
362
-- CPU09 CPU core
363
--
364
-----------------------------------------------------------------
365
 
366
component cpu09
367
  port (
368
         clk:        in std_logic;
369
    rst:      in        std_logic;
370
    rw:      out        std_logic;              -- Asynchronous memory interface
371
    vma:             out        std_logic;
372
    address:  out       std_logic_vector(15 downto 0);
373
    data_in:  in        std_logic_vector(7 downto 0);
374
         data_out: out std_logic_vector(7 downto 0);
375
         halt:     in  std_logic;
376
         hold:     in  std_logic;
377
         irq:      in  std_logic;
378
         nmi:      in  std_logic;
379
         firq:     in  std_logic
380
  );
381
end component;
382
 
383
 
384
----------------------------------------
385
--
386
-- 4K Block RAM Monitor ROM
387
--
388
----------------------------------------
389
component mon_rom
390
    Port (
391
       clk   : in  std_logic;
392
                 rst   : in  std_logic;
393
                 cs    : in  std_logic;
394
                 rw    : in  std_logic;
395
       addr  : in  std_logic_vector (11 downto 0);
396
       rdata : out std_logic_vector (7 downto 0);
397
       wdata : in  std_logic_vector (7 downto 0)
398
    );
399
end component;
400
 
401
 
402
----------------------------------------
403
--
404
-- 8KBytes Block RAM for FLEX9
405
-- $C000 - $DFFF
406
--
407
----------------------------------------
408
component flex_ram
409
  Port (
410
    clk      : in  std_logic;
411
    rst      : in  std_logic;
412
    cs       : in  std_logic;
413
    rw       : in  std_logic;
414
    addr     : in  std_logic_vector (12 downto 0);
415
    rdata    : out std_logic_vector (7 downto 0);
416
    wdata    : in  std_logic_vector (7 downto 0)
417
    );
418
end component;
419
 
420
-----------------------------------------------------------------
421
--
422
-- 6850 Compatible ACIA / UART
423
--
424
-----------------------------------------------------------------
425
 
426
component ACIA_6850
427
  port (
428
     clk      : in  Std_Logic;  -- System Clock
429
     rst      : in  Std_Logic;  -- Reset input (active high)
430
     cs       : in  Std_Logic;  -- miniUART Chip Select
431
     rw       : in  Std_Logic;  -- Read / Not Write
432
     irq      : out Std_Logic;  -- Interrupt
433
     Addr     : in  Std_Logic;  -- Register Select
434
     DataIn   : in  Std_Logic_Vector(7 downto 0); -- Data Bus In 
435
     DataOut  : out Std_Logic_Vector(7 downto 0); -- Data Bus Out
436
     RxC      : in  Std_Logic;  -- Receive Baud Clock
437
     TxC      : in  Std_Logic;  -- Transmit Baud Clock
438
     RxD      : in  Std_Logic;  -- Receive Data
439
     TxD      : out Std_Logic;  -- Transmit Data
440
     DCD_n    : in  Std_Logic;  -- Data Carrier Detect
441
     CTS_n    : in  Std_Logic;  -- Clear To Send
442
     RTS_n    : out Std_Logic );  -- Request To send
443
end component;
444
 
445
 
446
-----------------------------------------------------------------
447
--
448
-- ACIA Clock divider
449
--
450
-----------------------------------------------------------------
451
 
452
component ACIA_Clock
453
  generic (
454
     SYS_Clock_Frequency  : integer :=  SYS_Clock_Frequency;
455
          ACIA_Clock_Frequency : integer := ACIA_Clock_Frequency
456
  );
457
  port (
458
     clk      : in  Std_Logic;  -- System Clock Input
459
          ACIA_clk : out Std_logic   -- ACIA Clock output
460
  );
461
end component;
462
 
463
 
464
----------------------------------------
465
--
466
-- PS/2 Keyboard
467
--
468
----------------------------------------
469
 
470
component keyboard
471
  generic(
472
  KBD_Clock_Frequency : integer := CPU_Clock_Frequency
473
  );
474
  port(
475
  clk             : in    std_logic;
476
  rst             : in    std_logic;
477
  cs              : in    std_logic;
478
  rw              : in    std_logic;
479
  addr            : in    std_logic;
480
  data_in         : in    std_logic_vector(7 downto 0);
481
  data_out        : out   std_logic_vector(7 downto 0);
482
  irq             : out   std_logic;
483
  kbd_clk         : inout std_logic;
484
  kbd_data        : inout std_logic
485
  );
486
end component;
487
 
488
----------------------------------------
489
--
490
-- Video Display Unit.
491
--
492
----------------------------------------
493
component vdu8
494
      generic(
495
        VDU_CLOCK_FREQUENCY    : integer := CPU_Clock_Frequency; -- HZ
496
        VGA_CLOCK_FREQUENCY    : integer := PIX_Clock_Frequency; -- HZ
497
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS
498
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS
499
             VGA_PIXELS_PER_CHAR    : integer := 8;  -- PIXELS
500
             VGA_LINES_PER_CHAR     : integer := 16; -- LINES
501
             VGA_HOR_BACK_PORCH     : integer := 40; -- PIXELS
502
             VGA_HOR_SYNC           : integer := 96; -- PIXELS
503
             VGA_HOR_FRONT_PORCH    : integer := 24; -- PIXELS
504
             VGA_VER_BACK_PORCH     : integer := 13; -- LINES
505
             VGA_VER_SYNC           : integer := 1;  -- LINES
506
             VGA_VER_FRONT_PORCH    : integer := 36  -- LINES
507
      );
508
      port(
509
                -- control register interface
510
      vdu_clk      : in  std_logic;      -- CPU Clock - 25MHz
511
      vdu_rst      : in  std_logic;
512
                vdu_cs       : in  std_logic;
513
                vdu_rw       : in  std_logic;
514
                vdu_addr     : in  std_logic_vector(2 downto 0);
515
      vdu_data_in  : in  std_logic_vector(7 downto 0);
516
      vdu_data_out : out std_logic_vector(7 downto 0);
517
 
518
      -- vga port connections
519
                vga_clk      : in  std_logic;   -- VGA Pixel Clock - 25 MHz
520
      vga_red_o    : out std_logic;
521
      vga_green_o  : out std_logic;
522
      vga_blue_o   : out std_logic;
523
      vga_hsync_o  : out std_logic;
524
      vga_vsync_o  : out std_logic
525
   );
526
end component;
527
 
528
 
529
----------------------------------------
530
--
531
-- Timer module
532
--
533
----------------------------------------
534
 
535
component timer
536
  port (
537
     clk       : in std_logic;
538
     rst       : in std_logic;
539
     cs        : in std_logic;
540
     rw        : in std_logic;
541
     addr      : in std_logic;
542
     data_in   : in std_logic_vector(7 downto 0);
543
          data_out  : out std_logic_vector(7 downto 0);
544
          irq       : out std_logic
545
          );
546
end component;
547
 
548
------------------------------------------------------------
549
--
550
-- Bus Trap logic
551
--
552
------------------------------------------------------------
553
 
554
component trap
555
        port (
556
         clk        : in  std_logic;
557
    rst        : in  std_logic;
558
    cs         : in  std_logic;
559
    rw         : in  std_logic;
560
    vma        : in  std_logic;
561
    addr       : in  std_logic_vector(15 downto 0);
562
    data_in    : in  std_logic_vector(7 downto 0);
563
         data_out   : out std_logic_vector(7 downto 0);
564
         irq        : out std_logic
565
  );
566
end component;
567
 
568
 
569
----------------------------------------
570
--
571
-- Dynamic Address Translation Registers
572
--
573
----------------------------------------
574
component dat_ram
575
  port (
576
    clk      : in  std_logic;
577
         rst      : in  std_logic;
578
         cs       : in  std_logic;
579
         rw       : in  std_logic;
580
         addr_lo  : in  std_logic_vector(3 downto 0);
581
         addr_hi  : in  std_logic_vector(3 downto 0);
582
    data_in  : in  std_logic_vector(7 downto 0);
583
         data_out : out std_logic_vector(7 downto 0)
584
  );
585
end component;
586
 
587
component XSASDRAMCntl
588
  generic(
589
    FREQ                 :     natural := FREQ;        -- operating frequency in KHz
590
    CLK_DIV              :     real    := CLK_DIV;     -- divisor for FREQ (can only be 1.0, 1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0 or 16.0)
591
    PIPE_EN              :     boolean := PIPE_EN;     -- if true, enable pipelined read operations
592
    MAX_NOP              :     natural := MAX_NOP;     -- number of NOPs before entering self-refresh
593
    MULTIPLE_ACTIVE_ROWS :     boolean := MULTIPLE_ACTIVE_ROWS;  -- if true, allow an active row in each bank
594
    DATA_WIDTH           :     natural := DATA_WIDTH;  -- host & SDRAM data width
595
    NROWS                :     natural := NROWS;       -- number of rows in SDRAM array
596
    NCOLS                :     natural := NCOLS;       -- number of columns in SDRAM array
597
    HADDR_WIDTH          :     natural := HADDR_WIDTH; -- host-side address width
598
    SADDR_WIDTH          :     natural := SADDR_WIDTH  -- SDRAM-side address width
599
    );
600
  port(
601
    -- host side
602
    clk                  : in  std_logic;  -- master clock
603
    bufclk               : out std_logic;  -- buffered master clock
604
    clk1x                : out std_logic;  -- host clock sync'ed to master clock (and divided if CLK_DIV>1)
605
    clk2x                : out std_logic;  -- double-speed host clock
606
    lock                 : out std_logic;  -- true when host clock is locked to master clock
607
    rst                  : in  std_logic;  -- reset
608
    rd                   : in  std_logic;  -- initiate read operation
609
    wr                   : in  std_logic;  -- initiate write operation
610
    earlyOpBegun         : out std_logic;  -- read/write/self-refresh op begun     (async)
611
    opBegun              : out std_logic;  -- read/write/self-refresh op begun (clocked)
612
    rdPending            : out std_logic;  -- read operation(s) are still in the pipeline
613
    done                 : out std_logic;  -- read or write operation is done
614
    rdDone               : out std_logic;  -- read done and data is available
615
    hAddr                : in  std_logic_vector(HADDR_WIDTH-1 downto 0);  -- address from host
616
    hDIn                 : in  std_logic_vector(DATA_WIDTH-1 downto 0);  -- data from host
617
    hDOut                : out std_logic_vector(DATA_WIDTH-1 downto 0);  -- data to host
618
    status               : out std_logic_vector(3 downto 0);  -- diagnostic status of the FSM         
619
 
620
    -- SDRAM side
621
    sclkfb               : in    std_logic;           -- clock from SDRAM after PCB delays
622
    sclk                 : out   std_logic;           -- SDRAM clock sync'ed to master clock
623
    cke                  : out   std_logic;           -- clock-enable to SDRAM
624
    cs_n                 : out   std_logic;           -- chip-select to SDRAM
625
    ras_n                : out   std_logic;           -- SDRAM row address strobe
626
    cas_n                : out   std_logic;           -- SDRAM column address strobe
627
    we_n                 : out   std_logic;           -- SDRAM write enable
628
    ba                   : out   std_logic_vector(1 downto 0);  -- SDRAM bank address bits
629
    sAddr                : out   std_logic_vector(SADDR_WIDTH-1 downto 0);  -- SDRAM row/column address
630
    sData                : inout std_logic_vector(DATA_WIDTH-1 downto 0);  -- SDRAM in/out databus
631
    dqmh                 : out   std_logic;           -- high databits I/O mask
632
    dqml                 : out   std_logic            -- low databits I/O mask
633
    );
634
end component;
635
 
636
--
637
-- Clock buffer
638
--
639
component BUFG
640
   Port (
641
     i: in std_logic;
642
          o: out std_logic
643
  );
644
end component;
645
 
646
begin
647
  -----------------------------------------------------------------------------
648
  -- Instantiation of internal components
649
  -----------------------------------------------------------------------------
650
 
651
my_cpu : cpu09  port map (
652
         clk         => cpu_clk,
653
    rst       => cpu_reset,
654
    rw       => cpu_rw,
655
    vma       => cpu_vma,
656
    address   => cpu_addr(15 downto 0),
657
    data_in   => cpu_data_in,
658
         data_out  => cpu_data_out,
659
         halt      => cpu_halt,
660
         hold      => cpu_hold,
661
         irq       => cpu_irq,
662
         nmi       => cpu_nmi,
663
         firq      => cpu_firq
664
  );
665
 
666
my_rom : mon_rom port map (
667
       clk   => cpu_clk,
668
                 rst   => cpu_reset,
669
                 cs    => rom_cs,
670
                 rw    => '1',
671
       addr  => cpu_addr(11 downto 0),
672
       wdata => cpu_data_out,
673
       rdata => rom_data_out
674
    );
675
 
676
my_flex : flex_ram port map (
677
    clk       => cpu_clk,
678
    rst       => cpu_reset,
679
         cs        => flex_cs,
680
         rw        => cpu_rw,
681
    addr      => cpu_addr(12 downto 0),
682
    rdata     => flex_data_out,
683
    wdata     => cpu_data_out
684
    );
685
 
686
my_acia  : ACIA_6850 port map (
687
         clk         => cpu_clk,
688
         rst       => cpu_reset,
689
    cs        => acia_cs,
690
         rw        => cpu_rw,
691
    irq       => acia_irq,
692
    Addr      => cpu_addr(0),
693
         Datain    => cpu_data_out,
694
         DataOut   => acia_data_out,
695
         RxC       => acia_clk,
696
         TxC       => acia_clk,
697
         RxD       => rxd,
698
         TxD       => txd,
699
         DCD_n     => dcd_n,
700
         CTS_n     => cts_n,
701
         RTS_n     => rts_n
702
         );
703
 
704
 
705
my_ACIA_Clock : ACIA_Clock
706
  generic map(
707
    SYS_Clock_Frequency  => SYS_Clock_Frequency,
708
         ACIA_Clock_Frequency => ACIA_Clock_Frequency
709
  )
710
  port map(
711
    clk        => Clk_i,
712
    acia_clk   => acia_clk
713
  );
714
 
715
----------------------------------------
716
--
717
-- PS/2 Keyboard Interface
718
--
719
----------------------------------------
720
my_keyboard : keyboard
721
   generic map (
722
        KBD_Clock_Frequency => CPU_Clock_frequency
723
        )
724
   port map(
725
        clk          => cpu_clk,
726
        rst          => cpu_reset,
727
        cs           => keyboard_cs,
728
        rw           => cpu_rw,
729
        addr         => cpu_addr(0),
730
        data_in      => cpu_data_out(7 downto 0),
731
        data_out     => keyboard_data_out(7 downto 0),
732
        irq          => keyboard_irq,
733
        kbd_clk      => ps2_clk,
734
        kbd_data     => ps2_dat
735
        );
736
 
737
----------------------------------------
738
--
739
-- Video Display Unit instantiation
740
--
741
----------------------------------------
742
my_vdu : vdu8
743
  generic map(
744
      VDU_CLOCK_FREQUENCY    => CPU_Clock_Frequency, -- HZ
745
      VGA_CLOCK_FREQUENCY    => PIX_Clock_Frequency, -- HZ
746
           VGA_HOR_CHARS          => 80, -- CHARACTERS
747
           VGA_VER_CHARS          => 25, -- CHARACTERS
748
           VGA_PIXELS_PER_CHAR    => 8,  -- PIXELS
749
           VGA_LINES_PER_CHAR     => 16, -- LINES
750
           VGA_HOR_BACK_PORCH     => 40, -- PIXELS
751
           VGA_HOR_SYNC           => 96, -- PIXELS
752
           VGA_HOR_FRONT_PORCH    => 24, -- PIXELS
753
           VGA_VER_BACK_PORCH     => 13, -- LINES
754
           VGA_VER_SYNC           => 1,  -- LINES
755
           VGA_VER_FRONT_PORCH    => 36  -- LINES
756
  )
757
  port map(
758
 
759
                -- Control Registers
760
                vdu_clk       => cpu_clk,                                        -- 12.5 MHz System Clock in
761
      vdu_rst       => cpu_reset,
762
                vdu_cs        => vdu_cs,
763
                vdu_rw        => cpu_rw,
764
                vdu_addr      => cpu_addr(2 downto 0),
765
                vdu_data_in   => cpu_data_out,
766
                vdu_data_out  => vdu_data_out,
767
 
768
      -- vga port connections
769
      vga_clk       => pix_clk,                                  -- 25 MHz VDU pixel clock
770
      vga_red_o     => vga_red_o,
771
      vga_green_o   => vga_green_o,
772
      vga_blue_o    => vga_blue_o,
773
      vga_hsync_o   => vga_hsync_n,
774
      vga_vsync_o   => vga_vsync_n
775
   );
776
 
777
----------------------------------------
778
--
779
-- Timer Module
780
--
781
----------------------------------------
782
my_timer  : timer port map (
783
    clk       => cpu_clk,
784
         rst       => cpu_reset,
785
    cs        => timer_cs,
786
         rw        => cpu_rw,
787
    addr      => cpu_addr(0),
788
         data_in   => cpu_data_out,
789
         data_out  => timer_data_out,
790
    irq       => timer_irq
791
    );
792
 
793
----------------------------------------
794
--
795
-- Bus Trap Interrupt logic
796
--
797
----------------------------------------
798
my_trap : trap port map (
799
         clk        => cpu_clk,
800
    rst        => cpu_reset,
801
    cs         => trap_cs,
802
    rw         => cpu_rw,
803
         vma        => cpu_vma,
804
    addr       => cpu_addr,
805
    data_in    => cpu_data_out,
806
         data_out   => trap_data_out,
807
         irq        => trap_irq
808
    );
809
 
810
 
811
my_dat : dat_ram port map (
812
    clk       => cpu_clk,
813
         rst       => cpu_reset,
814
         cs        => dat_cs,
815
         rw        => cpu_rw,
816
         addr_hi   => cpu_addr(15 downto 12),
817
         addr_lo   => cpu_addr(3 downto 0),
818
    data_in   => cpu_data_out,
819
         data_out  => dat_addr(7 downto 0)
820
         );
821
 
822
  ------------------------------------------------------------------------
823
  -- Instantiate the SDRAM controller that connects to the memory tester
824
  -- module and interfaces to the external SDRAM chip.
825
  ------------------------------------------------------------------------
826
  u1 : xsaSDRAMCntl
827
    generic map(
828
      FREQ                 => FREQ,
829
      PIPE_EN              => PIPE_EN,
830
      DATA_WIDTH           => DATA_WIDTH,
831
      MULTIPLE_ACTIVE_ROWS => MULTIPLE_ACTIVE_ROWS,
832
      NROWS                => NROWS,
833
      NCOLS                => NCOLS,
834
      HADDR_WIDTH          => HADDR_WIDTH,
835
      SADDR_WIDTH          => SADDR_WIDTH
836
      )
837
    port map(
838
           -- Host Side
839
      clk                  => CLKA,     -- master clock from external clock source (unbuffered)
840
      bufclk               => open,     -- buffered master clock output
841
      clk1x                => clk_i,    -- synchronized master clock (accounts for delays to external SDRAM)
842
      clk2x                => open,     -- synchronized doubled master clock
843
      lock                 => lock,     -- DLL lock indicator
844
      rst                  => rst_i,    -- reset
845
      rd                   => hRd,      -- host-side SDRAM read control from memory tester
846
      wr                   => hWr,      -- host-side SDRAM write control from memory tester
847
      rdPending            => rdPending,-- read operation to SDRAM is in progress
848
      opBegun              => opBegun,  -- indicates memory read/write has begun
849
      earlyOpBegun         => earlyBegun,  -- early indicator that memory operation has begun
850
      rdDone               => rdDone,   -- indicates SDRAM memory read operation is done
851
      done                 => ramDone, -- indicates SDRAM memory read or write operation is done
852
      hAddr                => hAddr,    -- host-side address from memory tester to SDRAM
853
      hDIn                 => hDIn,     -- test data pattern from memory tester to SDRAM
854
      hDOut                => hDOut,    -- SDRAM data output to memory tester
855
      status               => open,     -- SDRAM controller state (for diagnostics)
856
                -- SDRAM Side
857
      sclkfb               => SDRAM_clkfb,    -- clock feedback with added external PCB delays
858
      sclk                 => SDRAM_clkout,   -- synchronized clock to external SDRAM
859
      cke                  => SDRAM_cke,      -- SDRAM clock enable
860
      cs_n                 => SDRAM_cs_n,     -- SDRAM chip-select
861
      ras_n                => SDRAM_ras_n,    -- SDRAM RAS
862
      cas_n                => SDRAM_cas_n,    -- SDRAM CAS
863
      we_n                 => SDRAM_we_n,     -- SDRAM write-enable
864
      ba                   => SDRAM_ba,       -- SDRAM bank address
865
      sAddr                => SDRAM_A,        -- SDRAM address
866
      sData                => SDRAM_D,        -- SDRAM databus
867
      dqmh                 => SDRAM_dqmh,     -- SDRAM DQMH
868
      dqml                 => SDRAM_dqml      -- SDRAM DQML
869
      );
870
 
871
cpu_clk_buffer : BUFG port map(
872
    i => Clk25,
873
         o => cpu_clk
874
    );
875
 
876
pix_clk_buffer : BUFG port map(
877
    i => Clk25,
878
         o => pix_clk
879
    );
880
 
881
----------------------------------------------------------------------
882
--
883
-- Process to decode memory map
884
--
885
----------------------------------------------------------------------
886
 
887
mem_decode: process( cpu_clk,
888
                     cpu_addr, cpu_rw, cpu_vma,
889
                                                        dat_addr,
890
                                              rom_data_out,
891
                                                        flex_data_out,
892
                                                   acia_data_out,
893
                                                        keyboard_data_out,
894
                                                        vdu_data_out,
895
                                                        pb_data_out,
896
                                                        timer_data_out,
897
                                                        trap_data_out,
898
                                                        ram_data_out
899
                                                        )
900
begin
901
      cpu_data_in <= (others=>'0');
902
      dat_cs      <= '0';
903
      rom_cs      <= '0';
904
      flex_cs     <= '0';
905
           acia_cs     <= '0';
906
           keyboard_cs <= '0';
907
           vdu_cs      <= '0';
908
           timer_cs    <= '0';
909
           trap_cs     <= '0';
910
           pb_cs       <= '0';
911
           ide_cs      <= '0';
912
           ether_cs    <= '0';
913
           slot1_cs    <= '0';
914
           slot2_cs    <= '0';
915
           ram_cs      <= '0';
916
      if cpu_addr( 15 downto 8 ) = "11111111" then
917
              cpu_data_in <= rom_data_out;
918
         dat_cs      <= cpu_vma;              -- write DAT
919
         rom_cs      <= cpu_vma;              -- read  ROM
920
           --
921
                -- Sys09Bug Monitor ROM $F000 - $FFFF
922
                --
923
           elsif dat_addr(3 downto 0) = "1111" then -- $XF000 - $XFFFF
924
                   cpu_data_in <= rom_data_out;
925
                        rom_cs      <= cpu_vma;
926
 
927
      --
928
                -- IO Devices $E000 - $E7FF
929
                --
930
                elsif dat_addr(3 downto 0) = "1110" then -- $XE000 - $XEFFF
931
                        case cpu_addr(11 downto 8) is
932
                        --
933
                        -- SWTPC peripherals from $E000 to $E0FF
934
                        --
935
                        when "0000" =>
936
                     case cpu_addr(7 downto 4) is
937
                          --
938
                          -- Console Port ACIA $E000 - $E00F
939
                          --
940
                          when "0000" => -- $E000
941
                       cpu_data_in <= acia_data_out;
942
                            acia_cs     <= cpu_vma;
943
 
944
           --
945
           -- Reserved
946
                          -- Floppy Disk Controller port $E010 - $E01F
947
                          --
948
 
949
           --
950
           -- Keyboard port $E020 - $E02F
951
                          --
952
                          when "0010" => -- $E020
953
             cpu_data_in <= keyboard_data_out;
954
                            keyboard_cs <= cpu_vma;
955
 
956
           --
957
           -- VDU port $E030 - $E03F
958
                          --
959
                          when "0011" => -- $E030
960
             cpu_data_in <= vdu_data_out;
961
                            vdu_cs      <= cpu_vma;
962
 
963
           --
964
                          -- Reserved SWTPc MP-T Timer $E040 - $E04F
965
                          --
966
                          when "0100" => -- $E040
967
             cpu_data_in <= (others=> '0');
968
 
969
           --
970
           -- Timer $E050 - $E05F
971
                          --
972
                          when "0101" => -- $E050
973
             cpu_data_in <= timer_data_out;
974
             timer_cs    <= cpu_vma;
975
 
976
           --
977
           -- Bus Trap Logic $E060 - $E06F
978
                          --
979
                          when "0110" => -- $E060
980
             cpu_data_in <= trap_data_out;
981
                            trap_cs     <= cpu_vma;
982
 
983
           --
984
                          -- Reserved SWTPc MP-ID PIA Timer/Printer Port $E080 - $E08F
985
                          --
986
 
987
           --
988
                          -- Reserved SWTPc MP-ID PTM 6840 Timer Port $E090 - $E09F
989
                          --
990
 
991
                          --
992
                          -- Remaining 6 slots reserved for non SWTPc Peripherals
993
                          --
994
                          when others => -- $E0A0 to $E0FF
995
                            null;
996
                     end case;
997
                        --
998
                        -- XST-3.0 Peripheral Bus goes here
999
                        --      $E100 to $E1FF
1000
                        --      Four devices
1001
                        -- IDE, Ethernet, Slot1, Slot2
1002
                        --
1003
                        when "0001" =>
1004
                          cpu_data_in <= pb_data_out;
1005
                          pb_cs       <= cpu_vma;
1006
                     case cpu_addr(7 downto 6) is
1007
                          --
1008
                          -- IDE Interface $E100 to $E13F
1009
                          --
1010
                          when "00" =>
1011
                            ide_cs   <= cpu_vma;
1012
                          --
1013
                          -- Ethernet Interface $E140 to $E17F
1014
                          --
1015
                          when "01" =>
1016
                            ether_cs <= cpu_vma;
1017
                          --
1018
                          -- Slot 1 Interface $E180 to $E1BF
1019
                          --
1020
                          when "10" =>
1021
                            slot1_cs <= cpu_vma;
1022
                          --
1023
                          -- Slot 2 Interface $E1C0 to $E1FF
1024
                          --
1025
                          when "11" =>
1026
                            slot2_cs <= cpu_vma;
1027
           --
1028
                          -- Nothing else
1029
                          --
1030
           when others =>
1031
                            null;
1032
           end case;
1033
         --
1034
                        --      $E200 to $EFFF reserved for future use
1035
                        --
1036
                when others =>
1037
                          null;
1038
         end case;
1039
                --
1040
                -- Flex RAM $0C000 - $0DFFF
1041
                --
1042
                elsif dat_addr(7 downto 1) = "0000110" then -- $0C000 - $0DFFF
1043
                   cpu_data_in <= flex_data_out;
1044
                        flex_cs     <= cpu_vma;
1045
                --
1046
                -- Everything else is RAM
1047
                --
1048
                else
1049
                   cpu_data_in <= ram_data_out;
1050
                   ram_cs      <= cpu_vma;
1051
          end if;
1052
end process;
1053
 
1054
 
1055
--
1056
-- 16-bit Peripheral Bus
1057
-- 6809 Big endian
1058
-- ISA bus little endian
1059
-- Not sure about IDE interface
1060
--
1061
peripheral_bus: process( clk_i, cpu_reset, cpu_rw, cpu_addr, cpu_data_out )
1062
begin
1063
  pb_wru <= pb_cs and (not cpu_rw) and (not cpu_addr(0));
1064
  pb_wrl <= pb_cs and (not cpu_rw) and      cpu_addr(0) ;
1065
  pb_rdu <= pb_cs and      cpu_rw  and (not cpu_addr(0));
1066
  pb_rdl <= pb_cs and      cpu_rw  and      cpu_addr(0) ;
1067
  pb_a   <= cpu_addr(5 downto 1);
1068
 
1069
  --
1070
  -- Register upper byte from CPU on first CPU write
1071
  -- and lower byte from the peripheral bus on first CPU read
1072
  --
1073
  if cpu_reset = '1' then
1074
    pb_wreg <= (others => '0');
1075
    pb_rreg <= (others => '0');
1076
  elsif clk_i'event and clk_i ='1' then
1077
    if pb_wru = '1' then
1078
           pb_wreg <= cpu_data_out;
1079
    end if;
1080
    if pb_rdu = '1' then
1081
           pb_rreg <= pb_d(7 downto 0);
1082
    end if;
1083
   end if;
1084
  --
1085
  -- Peripheral bus read and write strobes are
1086
  -- Syncronized with the 50 MHz clock
1087
  -- and are asserted until the peripheral bus hold is released
1088
  --
1089
  if cpu_reset = '1' then
1090
    pb_wr_n <= '1';
1091
    pb_rd_n <= '1';
1092
  elsif clk_i'event and clk_i ='1' then
1093
         if pb_hold = '1' then
1094
           pb_wr_n  <= not pb_wrl;
1095
           pb_rd_n  <= not pb_rdu;
1096
    else
1097
      pb_wr_n <= '1';
1098
      pb_rd_n <= '1';
1099
    end if;
1100
  end if;
1101
  --
1102
  -- The peripheral bus will be an output 
1103
  -- the registered even byte on data(15 downto 8)
1104
  -- and the CPU odd bytes on data(7 downto 0)
1105
  -- on odd byte writes
1106
  --
1107
  if pb_wrl = '1' then
1108
    pb_d <= pb_wreg & cpu_data_out;
1109
  else
1110
    pb_d <= (others => 'Z');
1111
  end if;
1112
 
1113
  --
1114
  -- On even byte reads,
1115
  -- the CPU reads the low (even) byte of the peripheral bus
1116
  -- On odd byte reads,
1117
  -- the CPU reads the registered (odd byte) input from the peripheral bus
1118
  --
1119
  if pb_rdu = '1' then
1120
    pb_data_out <= pb_d(15 downto 8);
1121
  elsif pb_rdl = '1' then
1122
    pb_data_out <= pb_rreg;
1123
  else
1124
    pb_data_out <= (others => '0');
1125
  end if;
1126
 
1127
end process;
1128
 
1129
--
1130
-- Hold Peripheral bus accesses for a few cycles
1131
--
1132
peripheral_bus_hold: process( cpu_clk, cpu_reset, pb_rdu, pb_wrl, ether_rdy )
1133
begin
1134
    if cpu_reset = '1' then
1135
                 pb_release    <= '0';
1136
                 pb_count      <= "0000";
1137
            pb_hold_state <= hold_release_state;
1138
         elsif cpu_clk'event and cpu_clk='1' then
1139
  --
1140
  -- The perpheral bus hold signal should be generated on 
1141
  -- 16 bit bus read which will be on even byte reads or 
1142
  -- 16 bit bus write which will be on odd byte writes.
1143
  -- 
1144
            case pb_hold_state is
1145
                 when hold_release_state =>
1146
          pb_release <= '0';
1147
                    if (pb_rdu = '1') or (pb_wrl = '1') then
1148
                            pb_count      <= "0100";
1149
                                 pb_hold_state <= hold_request_state;
1150
          elsif (pb_rdl = '1') or (pb_wru = '1') then
1151
             pb_release    <= '1';
1152
                                 pb_hold_state <= hold_release_state;
1153
                         end if;
1154
 
1155
                 when hold_request_state =>
1156
                         if pb_count = "0000" then
1157
            if ether_rdy = '1' then
1158
              pb_release    <= '1';
1159
                                  pb_hold_state <= hold_release_state;
1160
            end if;
1161
          else
1162
                       pb_count <= pb_count - "0001";
1163
                         end if;
1164
       when others =>
1165
                    null;
1166
       end case;
1167
         end if;
1168
end process;
1169
 
1170
--
1171
-- Compact Flash Control
1172
--
1173
compact_flash: process( ide_cs, cpu_addr )
1174
begin
1175
         ide_cs0_n  <= not( ide_cs ) or cpu_addr(4);
1176
         ide_cs1_n  <= not( ide_cs and cpu_addr(4));
1177
         ide_dmack_n  <= '1';
1178
end process;
1179
 
1180
--
1181
-- Interrupts and other bus control signals
1182
--
1183
interrupts : process( lock, rst_n, nmi_n,
1184
                                                         pb_cs, pb_hold, pb_release,
1185
                                                         ram_cs, ram_hold,
1186
                                                         ether_irq,
1187
                      acia_irq,
1188
                                                         keyboard_irq,
1189
                                                         trap_irq,
1190
                                                         timer_irq
1191
                                                         )
1192
begin
1193
         cpu_reset <= (not rst_n) or (not lock); -- CPU reset is active high
1194
    pb_hold   <= pb_cs and (not pb_release);
1195
    cpu_irq   <= acia_irq or keyboard_irq;
1196
         cpu_nmi   <= trap_irq or not( nmi_n );
1197
         cpu_firq  <= timer_irq;
1198
         cpu_halt  <= '0';
1199
         cpu_hold  <= pb_hold or ram_hold;
1200
end process;
1201
 
1202
 
1203
--
1204
-- Flash 7 segment LEDS
1205
--
1206
my_led_flasher: process( Clk_i, rst_n, CountL )
1207
begin
1208
    if rst_n = '0' then
1209
                   CountL <= "000000000000000000000000";
1210
    elsif(Clk_i'event and Clk_i = '1') then
1211
                   CountL <= CountL + 1;
1212
    end if;
1213
--       S(7 downto 0) <= CountL(23 downto 16);
1214
end process;
1215
 
1216
--
1217
-- Generate a 25 MHz Clock from 50 MHz
1218
--
1219
my_prescaler : process( Clk_i, clk_count )
1220
begin
1221
  if Clk_i'event and Clk_i = '1' then
1222
    clk_count(0) <= not clk_count(0);
1223
  end if;
1224
  Clk25 <= clk_count(0);
1225
end process;
1226
 
1227
--
1228
-- Push buttons
1229
--
1230
my_switch_assignments : process( SW2_N, SW3_N, rst_n )
1231
begin
1232
  rst_n    <= SW2_N;
1233
  rst_i    <= not rst_n;
1234
  nmi_n    <= SW3_N;
1235
  --
1236
  -- Disable Flash memory
1237
  --
1238
  FLASH_CE_N    <= '1';
1239
end process;
1240
 
1241
--
1242
-- RS232 signals:
1243
--
1244
my_acia_assignments : process( RS232_RXD, RS232_CTS, txd, rts_n )
1245
begin
1246
  rxd       <= RS232_RXD;
1247
  cts_n     <= RS232_CTS;
1248
  dcd_n     <= '0';
1249
  RS232_TXD <= txd;
1250
  RS232_RTS <= rts_n;
1251
end process;
1252
 
1253
--
1254
-- Pin assignments for ethernet controller
1255
--
1256
my_ethernet_assignments : process( clk_i, cpu_reset, ether_cs )
1257
begin
1258
    ether_cs_n  <= not ether_cs;
1259
    ether_aen   <= not ether_cs; -- Ethernet address enable not 
1260
    ether_bhe_n <= '1';          -- Ethernet bus high enable - 8 bit access only
1261
end process;
1262
 
1263
--
1264
-- I/O expansion slot assignments
1265
--
1266
my_slot_assignments : process( slot1_cs, slot2_cs)
1267
begin
1268
    slot1_cs_n <= not slot1_cs;
1269
    slot2_cs_n <= not slot2_cs;
1270
end process;
1271
 
1272
--
1273
-- VGA ouputs
1274
--
1275
my_vga_assignments : process( vga_red_o, vga_green_o, vga_blue_o )
1276
begin
1277
  VGA_red(0)   <= vga_red_o;
1278
  VGA_red(1)   <= vga_red_o;
1279
  VGA_red(2)   <= vga_red_o;
1280
  VGA_green(0) <= vga_green_o;
1281
  VGA_green(1) <= vga_green_o;
1282
  VGA_green(2) <= vga_green_o;
1283
  VGA_blue(0)  <= vga_blue_o;
1284
  VGA_blue(1)  <= vga_blue_o;
1285
  VGA_blue(2)  <= vga_blue_o;
1286
end process;
1287
 
1288
--
1289
-- SDRAM assignments
1290
--
1291
my_sdram_assignments : process( cpu_clk, clk_i, cpu_reset,
1292
                                opBegun, rdDone, wrDone,
1293
                                                                                  ram_rd_state, ram_wr_state,
1294
                                cpu_addr, dat_addr,
1295
                                cpu_data_out, hDout,
1296
                                                                                  ram_cs, cpu_rw, ram_hold )
1297
begin
1298
  if( cpu_reset = '1' ) then
1299
    hWr    <= '0';
1300
         hRd    <= '0';
1301
         wrDone <= '0';
1302
         ram_wr_state <= wr_state0;
1303
         ram_rd_state <= rd_state0;
1304
 
1305
  elsif( clk_i'event and clk_i='0' ) then
1306
    --
1307
         -- read state machine
1308
         --
1309
    case ram_rd_state is
1310
 
1311
    when rd_state0 =>
1312
           if (ram_hold = '1') and (cpu_rw = '1') then
1313
                  hRd          <= '1';
1314
                  ram_rd_state <= rd_state1;
1315
      end if;
1316
 
1317
    when rd_state1 =>
1318
           if opBegun = '1' then
1319
                  ram_rd_state <= rd_state2;
1320
      end if;
1321
 
1322
    when rd_state2 =>
1323
           if rdDone = '1' then
1324
                  hRd <= '0';
1325
                  ram_rd_state <= rd_state3;
1326
                end if;
1327
 
1328
    when rd_state3 =>
1329
           if rdDone = '0' then
1330
                  ram_rd_state <= rd_state0;
1331
      end if;
1332
 
1333
         when others =>
1334
                hRd          <= '0';
1335
                ram_rd_state <= rd_state0;
1336
         end case;
1337
 
1338
         --
1339
         -- Write state machine
1340
         --
1341
    case ram_wr_state is
1342
 
1343
    when wr_state0 =>
1344
           if (ram_hold = '1') and (cpu_rw = '0') then
1345
                  hWr          <= '1';
1346
        wrDone       <= '0';
1347
                  ram_wr_state <= wr_state1;
1348
      end if;
1349
 
1350
    when wr_state1 =>
1351
           if opBegun = '1' then
1352
                  hWr          <= '0';
1353
        wrDone       <= '0';
1354
                  ram_wr_state <= wr_state2;
1355
      end if;
1356
 
1357
    when wr_state2 =>
1358
                hWr          <= '0';
1359
      wrDone       <= '0';
1360
                ram_wr_state <= wr_state3;
1361
 
1362
    when wr_state3 =>
1363
                hWr          <= '0';
1364
      wrDone       <= '1';
1365
                ram_wr_state <= wr_state4;
1366
 
1367
    when wr_state4 =>
1368
                hWr          <= '0';
1369
      wrDone       <= '0';
1370
                ram_wr_state <= wr_state0;
1371
 
1372
         when others =>
1373
                hWr          <= '0';
1374
      wrDone       <= '0';
1375
                ram_wr_state <= wr_state0;
1376
 
1377
         end case;
1378
 
1379
  end if;
1380
  --
1381
  -- Strobe host RD and WR signals high on RAM select
1382
  -- Return low when cycle has started
1383
  --
1384
  if( cpu_reset = '1' ) then
1385
         ram_hold     <= '0';
1386
  elsif( cpu_clk'event and cpu_clk='1' ) then
1387
    --
1388
    -- Hold is intitiated when the RAM is selected
1389
    -- and released when access cycle is complete
1390
    -- 
1391
         if (ram_hold = '0') and (ram_cs = '1') then
1392
                ram_hold <= '1';
1393
    elsif (ram_hold = '1') and ((rdDone = '1') or (wrDone = '1')) then
1394
                ram_hold <= '0';
1395
    end if;
1396
  end if;
1397
 
1398
  hAddr(23 downto 20) <= "0000";
1399
  hAddr(19 downto 12) <= dat_addr;
1400
  hAddr(11 downto 0)  <= cpu_addr(11 downto 0);
1401
  hDin(7 downto 0)    <= cpu_data_out;
1402
  hDin(15 downto 8)   <= (others => '0');
1403
  ram_data_out        <= hDout(7 downto 0);
1404
 
1405
end process;
1406
 
1407
end rtl; --===================== End of architecture =======================--
1408
 

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