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[/] [System09/] [rev_86/] [rtl/] [VHDL/] [SevenSegment.vhd] - Blame information for rev 147

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1 19 dilbert57 
--===========================================================================--
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--
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--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
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--
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--  www.OpenCores.Org - December 2002
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--  This core adheres to the GNU public license
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--
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-- File name      : SevenSegment.vhd
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--
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-- entity name    : SevenSegment
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--
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-- Purpose        : 4 x 8 bit lathes to display 7 segments
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--
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-- Dependencies   : ieee.Std_Logic_1164
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--                  ieee.std_logic_unsigned
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--
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-- Author         : John E. Kent
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--
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--===========================================================================----
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--
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-- Revision History:
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--
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-- Date          Revision  Author
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-- 19 Oct 2004   0.1       John Kent
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--
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-- 21 Nov 2006   0.2       John Kent
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-- Inverted segment registers
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-- so '0' in segment registers switches segment OFF
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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entity seven_segment is
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        port (
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         clk       : in  std_logic;
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    rst       : in  std_logic;
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    cs        : in  std_logic;
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    rw        : in  std_logic;
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    addr      : in  std_logic_vector(1 downto 0);
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    data_in   : in  std_logic_vector(7 downto 0);
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         data_out  : out std_logic_vector(7 downto 0);
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         segments  : out std_logic_vector(7 downto 0);
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         digits   : out std_logic_vector(3 downto 0)
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         );
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end;
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architecture rtl of seven_segment is
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signal seg_reg0 : std_logic_vector(7 downto 0);
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signal seg_reg1 : std_logic_vector(7 downto 0);
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signal seg_reg2 : std_logic_vector(7 downto 0);
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signal seg_reg3 : std_logic_vector(7 downto 0);
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signal ClockDivider             : std_logic_vector(13 downto 0);
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signal WhichDigit                       : std_logic_vector(1 downto 0);
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begin
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---------------------------------
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--
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-- Write Segment registers
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--
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---------------------------------
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seg_write : process( clk, rst, addr, cs, rw, data_in )
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begin
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  if clk'event and clk = '0' then
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    if rst = '1' then
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      seg_reg0 <= "00000000";
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      seg_reg1 <= "00000000";
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      seg_reg2 <= "00000000";
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      seg_reg3 <= "00000000";
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    else
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           if cs = '1' and rw = '0' then
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        case addr is
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             when "00" =>
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                    seg_reg0 <= data_in;
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             when "01" =>
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                    seg_reg1 <= data_in;
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             when "10" =>
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                    seg_reg2 <= data_in;
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             when "11" =>
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                    seg_reg3 <= data_in;
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        when others =>
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                    null;
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                  end case;
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           end if;
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         end if;
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  end if;
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end process;
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---------------------------------
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--
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-- Read Segment registers
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--
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---------------------------------
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seg_read : process(  addr,
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                     seg_reg0, seg_reg1, seg_reg2, seg_reg3 )
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begin
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      case addr is
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             when "00" =>
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                    data_out <= seg_reg0;
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             when "01" =>
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                    data_out <= seg_reg1;
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             when "10" =>
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                    data_out <= seg_reg2;
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             when "11" =>
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                    data_out <= seg_reg3;
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        when others =>
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                    null;
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                end case;
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end process;
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---------------------------------
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--
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-- Output Segment registers
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--
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---------------------------------
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seg_out : process( rst, Clk)
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begin
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                if rst = '1' then
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                        ClockDivider <= (others => '0');
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                        WhichDigit   <= "00";
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                        Segments     <= "00000000";
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                        Digits      <= "1111";
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                elsif Clk'Event and Clk = '0' then
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                        if ClockDivider = "11000011010011" then
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                                ClockDivider <= (others => '0');
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                                case WhichDigit is      -- note that everything is pipelined
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                                        when "00" =>
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                                                Digits   <= "1110";
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                                                Segments <= not( seg_reg0 );
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                                        when "01" =>
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                                                Digits <= "1101";
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                                                Segments <= not( seg_reg1 );
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                                        when "10" =>
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                                                Digits <= "1011";
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                                                Segments <= not( seg_reg2 );
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                                        when "11" =>
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                                                Digits <= "0111";
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                                                Segments <= not( seg_reg3 );
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                                        when others =>
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                                           null;
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                                end case;
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                                WhichDigit <= WhichDigit + 1;
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                        else
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                                ClockDivider <= ClockDivider + 1;
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                        end if;
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                end if;
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end process;
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end rtl;
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