OpenCores
URL https://opencores.org/ocsvn/System09/System09/trunk

Subversion Repositories System09

[/] [System09/] [rev_86/] [rtl/] [VHDL/] [SevenSegment.vhd] - Blame information for rev 159

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 19 dilbert57 
--===========================================================================--
2 
--
3 
--  S Y N T H E Z I A B L E    Dynamic Address Translation Registers
4 
--
5 
--  www.OpenCores.Org - December 2002
6 
--  This core adheres to the GNU public license
7 
--
8 
-- File name      : SevenSegment.vhd
9 
--
10 
-- entity name    : SevenSegment
11 
--
12 
-- Purpose        : 4 x 8 bit lathes to display 7 segments
13 
--
14 
-- Dependencies   : ieee.Std_Logic_1164
15 
--                  ieee.std_logic_unsigned
16 
--
17 
-- Author         : John E. Kent
18 
--
19 
--===========================================================================----
20 
--
21 
-- Revision History:
22 
--
23 
-- Date          Revision  Author
24 
-- 19 Oct 2004   0.1       John Kent
25 
--
26 
-- 21 Nov 2006   0.2       John Kent
27 
-- Inverted segment registers
28 
-- so '0' in segment registers switches segment OFF
29 
--
30 
 
31 
library ieee;
32 
use ieee.std_logic_1164.all;
33 
use ieee.std_logic_unsigned.all;
34 
 
35 
entity seven_segment is
36 
        port (
37 
         clk       : in  std_logic;
38 
    rst       : in  std_logic;
39 
    cs        : in  std_logic;
40 
    rw        : in  std_logic;
41 
    addr      : in  std_logic_vector(1 downto 0);
42 
    data_in   : in  std_logic_vector(7 downto 0);
43 
         data_out  : out std_logic_vector(7 downto 0);
44 
         segments  : out std_logic_vector(7 downto 0);
45 
         digits   : out std_logic_vector(3 downto 0)
46 
         );
47 
end;
48 
 
49 
architecture rtl of seven_segment is
50 
signal seg_reg0 : std_logic_vector(7 downto 0);
51 
signal seg_reg1 : std_logic_vector(7 downto 0);
52 
signal seg_reg2 : std_logic_vector(7 downto 0);
53 
signal seg_reg3 : std_logic_vector(7 downto 0);
54 
 
55 
signal ClockDivider             : std_logic_vector(13 downto 0);
56 
signal WhichDigit                       : std_logic_vector(1 downto 0);
57 
 
58 
begin
59 
 
60 
---------------------------------
61 
--
62 
-- Write Segment registers
63 
--
64 
---------------------------------
65 
 
66 
seg_write : process( clk, rst, addr, cs, rw, data_in )
67 
begin
68 
  if clk'event and clk = '0' then
69 
    if rst = '1' then
70 
      seg_reg0 <= "00000000";
71 
      seg_reg1 <= "00000000";
72 
      seg_reg2 <= "00000000";
73 
      seg_reg3 <= "00000000";
74 
    else
75 
           if cs = '1' and rw = '0' then
76 
        case addr is
77 
             when "00" =>
78 
                    seg_reg0 <= data_in;
79 
             when "01" =>
80 
                    seg_reg1 <= data_in;
81 
             when "10" =>
82 
                    seg_reg2 <= data_in;
83 
             when "11" =>
84 
                    seg_reg3 <= data_in;
85 
        when others =>
86 
                    null;
87 
                  end case;
88 
           end if;
89 
         end if;
90 
  end if;
91 
end process;
92 
 
93 
---------------------------------
94 
--
95 
-- Read Segment registers
96 
--
97 
---------------------------------
98 
 
99 
seg_read : process(  addr,
100 
                     seg_reg0, seg_reg1, seg_reg2, seg_reg3 )
101 
begin
102 
      case addr is
103 
             when "00" =>
104 
                    data_out <= seg_reg0;
105 
             when "01" =>
106 
                    data_out <= seg_reg1;
107 
             when "10" =>
108 
                    data_out <= seg_reg2;
109 
             when "11" =>
110 
                    data_out <= seg_reg3;
111 
        when others =>
112 
                    null;
113 
                end case;
114 
end process;
115 
 
116 
---------------------------------
117 
--
118 
-- Output Segment registers
119 
--
120 
---------------------------------
121 
 
122 
seg_out : process( rst, Clk)
123 
begin
124 
                if rst = '1' then
125 
                        ClockDivider <= (others => '0');
126 
                        WhichDigit   <= "00";
127 
                        Segments     <= "00000000";
128 
                        Digits      <= "1111";
129 
                elsif Clk'Event and Clk = '0' then
130 
                        if ClockDivider = "11000011010011" then
131 
                                ClockDivider <= (others => '0');
132 
                                case WhichDigit is      -- note that everything is pipelined
133 
                                        when "00" =>
134 
                                                Digits   <= "1110";
135 
                                                Segments <= not( seg_reg0 );
136 
                                        when "01" =>
137 
                                                Digits <= "1101";
138 
                                                Segments <= not( seg_reg1 );
139 
                                        when "10" =>
140 
                                                Digits <= "1011";
141 
                                                Segments <= not( seg_reg2 );
142 
                                        when "11" =>
143 
                                                Digits <= "0111";
144 
                                                Segments <= not( seg_reg3 );
145 
                                        when others =>
146 
                                           null;
147 
                                end case;
148 
                                WhichDigit <= WhichDigit + 1;
149 
                        else
150 
                                ClockDivider <= ClockDivider + 1;
151 
                        end if;
152 
                end if;
153 
end process;
154 
 
155 
end rtl;
156 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.