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[/] [System09/] [rev_86/] [rtl/] [VHDL/] [clock_div.vhd] - Blame information for rev 66

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1 65 davidgb
--===========================================================================----
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--
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--  S Y N T H E Z I A B L E    Clock_dll for System09 - SOC.
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--
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--===========================================================================----
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--
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-- This core adheres to the GNU public license
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-- No responsibility is taken for this design.
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-- Use at own risk.  
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--
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-- File name       : Clock_dll.vhd
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--
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-- Purpose         : Generates Clocks for System09
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--                   For BurchED B3-Spartan2+ and B5-X300
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--                   Assumes a 12.5 MHz system clock input
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--                   Generates a x1 (12.5 MHz) CPU clock 
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--                   Generates a x2 (25.0 MHz) VGA clock 
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--                   Generates a x4 (50.0 MHz) MEM clock 
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--
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-- Dependencies    : ieee.Std_Logic_1164
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--                   ieee.std_logic_unsigned
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--                   ieee.std_logic_arith
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--                   ieee.numeric_std
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--
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--
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-- Revision History :
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--
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--   Rev         : 0.1
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--   Date        : 7th September 2008
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--   Description : Initial version.                 
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-- 
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--
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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library unisim;
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        use unisim.vcomponents.all;
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entity clock_div is
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  port(
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    clk_in      : in  std_Logic;  -- System Clock input
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         sys_clk     : out std_logic;  -- System Clock Out    (1/1)
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         vga_clk     : out std_logic;  -- VGA Pixel Clock Out (1/2)
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    cpu_clk     : out std_logic   -- CPU Clock Out       (1/4)
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  );
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end entity;
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architecture RTL of clock_div is
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signal div_clk     : std_logic;
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signal div_count   : std_logic_vector(1 downto 0);
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component IBUFG
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  port (
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                i: in  std_logic;
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                o: out std_logic
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  );
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end component;
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component BUFG
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  port (
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                i: in  std_logic;
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                o: out std_logic
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  );
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end component;
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--
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-- Start instantiation
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--
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begin
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--
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-- 50.0MHz  system clock
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--
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sys_clk_buffer : IBUFG
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  port map(
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    i => clk_in,
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         o => div_clk
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  );
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--
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-- 25 MHz VGA clock output
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--
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vga_clk_buffer : BUFG
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  port map(
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    i => div_count(0),
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         o => vga_clk
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  );
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--
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-- 12.5MHz CPU clock 
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--
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cpu_clk_buffer : BUFG
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  port map(
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    i => div_count(1),
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         o => cpu_clk
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  );
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--
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-- Clock divider
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--
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clock_div : process( div_clk )
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begin
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  if rising_edge( div_clk) then
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    div_count <= div_count + "01";
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  end if;
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  sys_clk <= div_clk;
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end process;
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end architecture;
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