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[/] [System09/] [rev_86/] [rtl/] [VHDL/] [clock_dll.vhd] - Blame information for rev 158

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Line No. Rev Author Line
1 65 davidgb
--===========================================================================----
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--
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--  S Y N T H E Z I A B L E    Clock_dll for System09 - SOC.
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--
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--===========================================================================----
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--
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-- This core adheres to the GNU public license
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-- No responsibility is taken for this design.
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-- Use at own risk.  
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--
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-- File name       : Clock_dll.vhd
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--
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-- Purpose         : Generates Clocks for System09
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--                   For BurchED B3-Spartan2+ and B5-X300
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--                   Assumes a 12.5 MHz system clock input
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--                   Generates a x1 (12.5 MHz) CPU clock 
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--                   Generates a x2 (25.0 MHz) VGA clock 
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--                   Generates a x4 (50.0 MHz) MEM clock 
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--
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-- Dependencies    : ieee.Std_Logic_1164
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--                   ieee.std_logic_unsigned
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--                   ieee.std_logic_arith
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--                   ieee.numeric_std
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--
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--
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-- Revision History :
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--
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--   Rev         : 0.1
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--   Date        : 7th September 2008
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--   Description : Initial version.                 
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-- 
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--
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library ieee;
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   use ieee.std_logic_1164.all;
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   use IEEE.STD_LOGIC_ARITH.ALL;
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   use IEEE.STD_LOGIC_UNSIGNED.ALL;
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   use ieee.numeric_std.all;
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library unisim;
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        use unisim.vcomponents.all;
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entity clock_dll is
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  port(
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    clk_in      : in  std_Logic;  -- System Clock input
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    clk_cpu     : out std_logic;  -- CPU Clock Out       (x1)
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         clk_vga     : out std_logic;  -- VGA Pixel Clock Out (x2)
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         clk_mem     : out std_logic;   -- Memory Clock Out    (x4)
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         locked      : out std_logic   -- DLL in lock
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  );
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end entity;
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architecture RTL of clock_dll is
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  signal CPU_CLK0    : std_ulogic;
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  signal CPU_CLK90   : std_ulogic;
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  signal CPU_CLK180  : std_ulogic;
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  signal CPU_CLK270  : std_ulogic;
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  signal CPU_CLK2X   : std_ulogic;
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  signal CPU_CLKDV   : std_ulogic;
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  signal CPU_LOCKED  : std_ulogic;
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  signal CPU_CLKFB   : std_ulogic;
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  signal CPU_CLKIN   : std_ulogic;
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  signal CPU_RESET   : std_ulogic;
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  signal VGA_CLK0    : std_ulogic;
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  signal VGA_CLK90   : std_ulogic;
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  signal VGA_CLK180  : std_ulogic;
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  signal VGA_CLK270  : std_ulogic;
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  signal VGA_CLK2X   : std_ulogic;
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  signal VGA_CLKDV   : std_ulogic;
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  signal VGA_LOCKED  : std_ulogic;
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  signal VGA_CLKFB   : std_ulogic;
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  signal VGA_CLKIN   : std_ulogic;
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  signal VGA_RESET   : std_ulogic;
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  signal VGA_RESET_N : std_ulogic;
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-- Component Declaration for CLKDLL should be placed
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-- after architecture statement but before begin keyword
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component CLKDLL
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  -- synthesis translate_off
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  generic (
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    CLKDV_DIVIDE          : real    := 2.0;  -- (1.5, 2.0, 2.5, 3.0, 4.0, 5.0, 8.0, 16.0)
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    DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
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    STARTUP_WAIT          : boolean := FALSE -- (TRUE, FALSE)
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  );
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  -- synthesis translate_on
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  port (
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    CLK0   : out STD_ULOGIC;
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    CLK180 : out STD_ULOGIC;
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    CLK270 : out STD_ULOGIC;
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    CLK2X  : out STD_ULOGIC;
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    CLK90  : out STD_ULOGIC;
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    CLKDV  : out STD_ULOGIC;
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    LOCKED : out STD_ULOGIC;
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    CLKFB  : in  STD_ULOGIC;
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    CLKIN  : in  STD_ULOGIC;
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    RST    : in  STD_ULOGIC
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  );
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end component;
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component IBUFG
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  port (
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                i: in  std_logic;
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                o: out std_logic
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  );
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end component;
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component BUFG
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  port (
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                i: in  std_logic;
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                o: out std_logic
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  );
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end component;
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component SRL16
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  port (
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    Q   : out std_logic;
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    D   : in  std_logic;
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    CLK : in  std_logic;
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    A0  : in  std_logic;
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    A1  : in  std_logic;
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    A2  : in  std_logic;
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    A3  : in  std_logic
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  );
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end component;
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--
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-- Start instantiation
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--
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begin
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--
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-- 12.5MHz CPU clock input
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--
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cpu_clkin_buffer : IBUFG
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  port map(
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    i => clk_in,
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         o => CPU_CLKIN
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  );
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--
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-- 12.5MHz CPU clock input
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--
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cpu_clkout_buffer : BUFG
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  port map(
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    i => CPU_CLKIN,
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         o => clk_cpu
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  );
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--
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-- 25 MHz VGA clock input
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--
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cpu_clkfb_buffer : BUFG
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  port map(
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    i => CPU_CLK2X,
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         o => CPU_CLKFB
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  );
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CLKDLL_CPU : CLKDLL
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  -- synthesis translate_off
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  generic map (
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    CLKDV_DIVIDE          => 2.0,  -- (1.5,2,2.5,3,4,5,8,16)
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    DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
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    STARTUP_WAIT          => FALSE  -- (TRUE, FALSE)
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  );
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  -- synthesis translate_on
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  port map (
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    CLK0   => CPU_CLK0,
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    CLK90  => CPU_CLK90,
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    CLK180 => CPU_CLK180,
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    CLK270 => CPU_CLK270,
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    CLK2X  => CPU_CLK2X,
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    CLKDV  => CPU_CLKDV,
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    LOCKED => CPU_LOCKED,
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    CLKFB  => CPU_CLKFB,
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    CLKIN  => CPU_CLKIN,
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    RST    => CPU_RESET
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  );
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--
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-- 25 MHz VGA clock output
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--
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vga_clkfb_buffer : BUFG
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  port map(
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    i => VGA_CLK2X,
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         o => VGA_CLKFB
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  );
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CLKDLL_VGA : CLKDLL
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  -- synthesis translate_off
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  generic map (
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    CLKDV_DIVIDE          => 2.0,    -- (1.5,2,2.5,3,4,5,8,16)
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    DUTY_CYCLE_CORRECTION => TRUE, -- (TRUE, FALSE)
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    STARTUP_WAIT          => FALSE  -- (TRUE, FALSE)
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  );
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  -- synthesis translate_on
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  port map (
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    CLK0   => VGA_CLK0,
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    CLK90  => VGA_CLK90,
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    CLK180 => VGA_CLK180,
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    CLK270 => VGA_CLK270,
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    CLK2X  => VGA_CLK2X,
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    CLKDV  => VGA_CLKDV,
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    LOCKED => VGA_LOCKED,
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    CLKFB  => VGA_CLKFB,
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    CLKIN  => VGA_CLKIN,
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    RST    => VGA_RESET
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  );
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my_srl16 : SRL16 port map (
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  Q   => VGA_RESET_N,
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  D   => CPU_LOCKED,
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  CLK => CPU_CLKFB,
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  A0  => '1',
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  A1  => '1',
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  A2  => '1',
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  A3  => '1'
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  );
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clock_dll_assign : process( VGA_RESET_N, VGA_LOCKED,
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                            clk_in, CPU_CLKFB, VGA_CLKFB )
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begin
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  VGA_RESET <= not VGA_RESET_N;
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  VGA_CLKIN <= CPU_CLKFB;
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  CPU_RESET <= '0';
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  clk_vga   <= CPU_CLKFB;
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  clk_mem   <= VGA_CLKFB;
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  locked    <= VGA_LOCKED;
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end process;
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end architecture;
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